CN103367281B - Semiconductor structure and its manufacture method that there is silicon through hole and test circuit - Google Patents
Semiconductor structure and its manufacture method that there is silicon through hole and test circuit Download PDFInfo
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- CN103367281B CN103367281B CN201210092744.1A CN201210092744A CN103367281B CN 103367281 B CN103367281 B CN 103367281B CN 201210092744 A CN201210092744 A CN 201210092744A CN 103367281 B CN103367281 B CN 103367281B
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Abstract
The invention discloses a kind of semiconductor structure, there is a silicon through hole and testing and patching circuit.Wherein, silicon through hole is arranged in substrate and runs through active face and the back side of substrate.Testing and patching circuit is arranged on the back side of substrate, is electrically connected with silicon through hole, so as to providing testing and patching function.Embodiment according to another preferred, invention additionally provides a kind of method forming semiconductor structure.
Description
Technical field
The present invention is about a kind of semiconductor structure and its manufacture method, particularly, is about a kind of semiconductor structure with testing and patching circuit and silicon through hole and its method of testing.
Background technology
In modern information society, by integrated circuit (integratedcircuit, IC) microprocessing systems constituted generally is applied to the every aspect of life already, for instance the electrical home appliances that automatically controls, mobile communication equipment, personal computer etc., has the use of integrated circuit.And day by day progressing greatly along with science and technology, and human society is for the various imaginations of electronic product so that integrated circuit also develops toward more polynary, more accurate, more small-sized direction.
General alleged integrated circuit, is the crystal grain (die) by producing in existing semiconductor technology and is formed.Manufacture the process of crystal grain, it is produced by a wafer (wafer) to start: first, wafer distinguishes multiple region, and on each zone, by various semiconductor technologies such as deposition, photoetching, etching or flatening process, to form various required circuit traces.Then, carrying out general testing procedure whether can smooth operation with testing inner element.Then, again the regional on wafer is carried out cutting and form each crystal grain, and it is packaged into chip (chip), finally again chip is electrically connected to a circuit board, such as a printed circuit board (PCB) (printedcircuitboard, PCB), after making pin (pin) electrical connection of chip and printed circuit board (PCB), the various process stylized can just be performed.
In order to improve chip functions and usefulness, increase integrated level more semiconductor element can be held under the confined space, relevant manufactures develops the Stack Technology of many semiconductor wafers, include chip package (flip-chip) technology, multi-die package (multi-chippackage, MCP) technology, encapsulation stacking (packageonpackage, PoP) technology, encapsulate built-in packaging body (packageinpackage, PiP) technology etc., increase the integrated level of semiconductor element in unit volume such as through each other stacking between wafer or packaging body.Development one is called the technology of silicon through hole (throughsiliconvia, TSV) again in recent years, can promote the interior bonds (interconnect) of each chip chamber in packaging body, stacking efficiency up to be promoted further.
In existing technology, very convenient stack mode owing to silicon through hole provides, therefore used in a large number, also open the imagination of different chip design.
Summary of the invention
The present invention then discloses a kind of structure by the formation of testing and patching circuit at backside of substrate, and coordinates silicon through hole, it is possible to test bit semiconductor element on substrate active face.
According to an embodiment of the invention, the present invention is to provide a kind of semiconductor structure, has a silicon through hole and testing and patching circuit.Wherein, silicon through hole is arranged in substrate and runs through active face and the back side of substrate.Testing and patching circuit is arranged on the back side of substrate, is electrically connected with silicon through hole.
Embodiment according to another preferred, invention additionally provides a kind of method forming semiconductor structure.First providing substrate, it has active face and the back side.Then silicon through hole, its active face running through substrate and the back side are formed in the substrate.Last formation testing and patching circuit on the back side of substrate.
The present invention and be formation testing and patching circuit on the back side of substrate, and by the design of silicon through hole, it is possible to the circuit on wafer active face is carried out testing and patching.By by testing and patching circuit design mode overleaf, and silicon through hole of arranging in pairs or groups, it is possible to save the volume of chip, and make the design of testing and patching circuit more flexible.
Accompanying drawing explanation
Fig. 1 to Fig. 6, it is shown that for having the manufacture method of silicon through hole and the semiconductor structure of testing and patching circuit in the present invention.
Wherein, description of reference numerals is as follows:
300 substrate 318 metal interconnecting systems
302 first surface 320 engagement pads
304 second surface 322 silicon through hole
306 perforate 324 testing and patching circuit
312 insulating barrier 326 metal interconnecting systems
314 conductive layer 328 engagement pads
316 semiconductor element 330 fuses
317 the 3rd surfaces
Detailed description of the invention
For making those skilled in the art can further appreciate that the present invention, the following description has enumerated the several preferred implementation of the present invention, and coordinates accompanying drawing and explanation, with describe in detail present disclosure and desire realize effect.
Refer to Fig. 1 to Fig. 6, it is shown that for the present invention has the manufacture method of silicon through hole and the semiconductor structure of testing and patching circuit.As shown in Figure 1, first one substrate 300 is provided, it is such as silicon base (siliconsubstrate), epitaxial silicon substrate (epitaxialsiliconsubstrate), silicon germanium semiconductor substrate (silicongermaniumsubstrate), silicon carbide substrate (siliconcarbidesubstrate) or silicon-coated insulated (silicon-on-insulator, SOI).Substrate 300 has first surface 302 and a second surface 304.In the preferred embodiment of the present invention, first surface 302 is such as the active face (activesurface) of substrate 300, and second surface 304 is such as the back side (backsurface) of substrate 300.Substrate 300 thickness substantially 700 to 1000 microns (micrometer).Then, the first surface 302 of substrate 300 forms a perforate 306, for instance in the way of dry ecthing, form perforate 306.About 5 to 10 microns of the aperture of perforate 306, and the degree of depth is about 50 to 100 microns, but the forming method of perforate 306 and embodiment are not limited to this, and visible product does different adjustment.
As in figure 2 it is shown, first form an insulating barrier 312 on the first surface 302 of substrate 300, for instance be a silicon dioxide layer.Insulating barrier 312 can be formed on the surface of perforate 306 but not fill up perforate 306.Then, at first surface 302 up one-tenth one conductive layer 314 of substrate 300, wherein conductive layer 314 can be fully filled with perforate 306.In an embodiment, conductive layer 314 is such as metallic copper, and the method formed is such as electroplating technology.
As shown in Figure 3, the first surface 302 of substrate 300 is carried out a flatening process, it is such as etch back process or chemically mechanical polishing (chemicalmechanicalpolish, CMP) technique is to remove insulating barrier beyond perforate 306 312 and conductive layer 314 so that insulating barrier 312, conductive layer 314 generally flush with first surface 302.
As shown in Figure 4, optionally can also form various semiconductor element and structure on the first surface 302 of substrate 300 before.For example, at least one semiconductor element 316 can be formed on first surface 302, it is such as gold oxygen compound semiconductor transistor (metaloxidesemiconductortransistor, MOStransistor), and forms a metal interconnecting system 318 thereon.Metal interconnecting system 318 can connect semiconductor element 316 in an engagement pad 320 so that semiconductor element 316 can pass through engagement pad 320 and receives outer signals and do the action of input/output.On the other hand, metal interconnecting system 318 can also connecting conductive layer 314 and other semiconductor element 316.
As it is shown in figure 5, formed after metal interconnecting system, the second surface 304 of substrate 300 is carried out a thinning technique, and be thinned to and expose conductive layer 314.Now, the second surface 304 after thinning becomes the 3rd surface 317.And the conductive layer 314 that position is in perforate 306 also form conductive electrode 315.Consequently, it is possible to namely define the structure of silicon through hole 322 in substrate 300.
The present invention is characterised by one of them, after defining silicon through hole 322, on the 3rd surface 317 of substrate 300, namely can form a testing and patching circuit 324 on the back side of substrate 300.In an embodiment of the invention, testing and patching circuit 324 such as can comprise metal interconnecting system 326, engagement pad 328 and a fuse 330.Silicon through hole 318 can pass through metal interconnecting system 326 and engagement pad 328 or fuse 330 connects.Therefore when subsequent wafer testing and patching step, the silicon through hole 318 that engagement pad 328 turns on can be utilized, semiconductor element 316 on substrate 300 first surface 302 is carried out testing and patching, has, if follow-up, the circuit detecting defect, it is also possible to repaired by structures such as fuses 330.It should be noted that the testing and patching circuit 324 of the present invention is not limited to the structures such as aforesaid fuse 330 engagement pad 328, it is also possible to be other semiconductor structure.But, in other embodiments, can be provided with testing and patching circuit at active face 302 and the back side 304 of substrate 300, this depends on the different designs of product.
As shown in Figure 6, the present invention is in there is provided a kind of semiconductor structure with testing and patching circuit and silicon through hole.Semiconductor structure includes substrate 300, silicon through hole 322, testing and patching circuit 324.Silicon through hole 322 is arranged in substrate 300, and runs through active face 302 and the 3rd surface 317 of substrate.Testing and patching circuit 324 is arranged on the 3rd surface 317 of substrate 300, is electrically connected with silicon through hole 322.In an embodiment, semiconductor structure also comprises semiconductor element 316 and metal interconnecting system arranges 318 on the first surface 302 of substrate 300.In another embodiment of the present invention, testing and patching circuit 324 is provided only on the 3rd surface 317 of substrate 300, does not namely provide the circuit of testing and patching step on first surface 302.But, in other embodiments, can be provided with testing and patching circuit at active face 302 and the back side 304 of substrate 300, this depends on the different designs of product.In one embodiment of the present of invention, testing and patching circuit 324 includes engagement pad 328, fuse 330 or metal interconnecting system.
Comprehensive above description, the present invention and be formation testing and patching circuit on the back side of substrate, and by the design of silicon through hole, it is possible to the circuit on wafer active face is carried out testing and patching.By by testing and patching circuit design mode overleaf, and silicon through hole of arranging in pairs or groups, it is possible to save the volume of chip, and make the design of testing and patching circuit more flexible.
The foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, for a person skilled in the art, the present invention can have various modifications and variations.All within the spirit and principles in the present invention, any amendment of making, equivalent replacement, improvement etc., should be included within protection scope of the present invention.
Claims (9)
1. a semiconductor structure, it is characterised in that including:
Substrate, has active face and the back side；
Silicon through hole is arranged in substrate, and runs through the described active face of described substrate and the described back side；
Semiconductor element and metal interconnecting system are arranged on the described active face of described substrate；And
Testing and patching circuit is arranged on the described back side of described substrate, and is directly electrically connected with described silicon through hole.
2. semiconductor structure according to claim 1, it is characterised in that described testing and patching circuit is provided only on the described back side of described substrate.
3. semiconductor structure according to claim 1, it is characterised in that described testing and patching circuit includes engagement pad or fuse.
4. the method forming semiconductor structure, it is characterised in that including:
Thering is provided substrate, it has active face and the back side；
Forming silicon through hole in described substrate, and form semiconductor element and metal interconnecting system on described active face, wherein said silicon through hole runs through the described active face of described substrate and the described back side；And
Forming testing and patching circuit on the described back side of described substrate, wherein said testing and patching circuit is directly electrically connected with described silicon through hole.
5. the method forming semiconductor structure according to claim 4, it is characterised in that described testing and patching circuit comprises engagement pad or fuse.
6. the method forming semiconductor structure according to claim 4, it is characterised in that the step forming described silicon through hole comprises:
A perforate is formed in the side of the described active face of described substrate；
Insulating barrier and conductive layer is formed, to fill up described perforate on the surface of described perforate；And
Thinning technique is carried out, to expose described conductive layer from the described back side of described substrate.
7. the method forming semiconductor structure according to claim 6, it is characterised in that described semiconductor element and described metal interconnecting system are to be previously formed carrying out described thinning technique.
8. the method forming semiconductor structure according to claim 7, it is characterised in that: described testing and patching circuit is carried out testing procedure, by described silicon through hole so that described semiconductor element to be tested.
9. the method forming semiconductor structure according to claim 7, it is characterised in that described semiconductor element comprises MOS transistor.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201210092744.1A CN103367281B (en) | 2012-03-31 | 2012-03-31 | Semiconductor structure and its manufacture method that there is silicon through hole and test circuit |
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| CN201210092744.1A CN103367281B (en) | 2012-03-31 | 2012-03-31 | Semiconductor structure and its manufacture method that there is silicon through hole and test circuit |
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| CN103367281A CN103367281A (en) | 2013-10-23 |
| CN103367281B true CN103367281B (en) | 2016-07-06 |
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Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10340203B2 (en) | 2014-02-07 | 2019-07-02 | United Microelectronics Corp. | Semiconductor structure with through silicon via and method for fabricating and testing the same |
| CN104851875B (en) * | 2014-02-18 | 2019-07-23 | 联华电子股份有限公司 | Semiconductor structure with through silicon via and preparation method thereof and test method |
| CN108288613B (en) * | 2018-02-08 | 2020-03-06 | 武汉新芯集成电路制造有限公司 | Integrated circuit structure and method for realizing modification of back-end connecting line of integrated circuit |
| CN115373926B (en) * | 2022-08-31 | 2023-05-16 | 西安微电子技术研究所 | Self-test and self-repair method and system based on physical layer IP |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101924040A (en) * | 2009-06-10 | 2010-12-22 | 财团法人工业技术研究院 | Chip repairing method and chip stack structure |
| EP2302403A1 (en) * | 2009-09-28 | 2011-03-30 | Imec | Method and device for testing TSVs in a 3D chip stack |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US8432038B2 (en) * | 2009-06-12 | 2013-04-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Through-silicon via structure and a process for forming the same |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101924040A (en) * | 2009-06-10 | 2010-12-22 | 财团法人工业技术研究院 | Chip repairing method and chip stack structure |
| EP2302403A1 (en) * | 2009-09-28 | 2011-03-30 | Imec | Method and device for testing TSVs in a 3D chip stack |
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