CN103377994A - Method for manufacturing through silicon hole - Google Patents
Method for manufacturing through silicon hole Download PDFInfo
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- CN103377994A CN103377994A CN2012101286346A CN201210128634A CN103377994A CN 103377994 A CN103377994 A CN 103377994A CN 2012101286346 A CN2012101286346 A CN 2012101286346A CN 201210128634 A CN201210128634 A CN 201210128634A CN 103377994 A CN103377994 A CN 103377994A
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Abstract
The invention discloses a method for manufacturing a through silicon hole. The method includes the steps that firstly, a substrate is provided, secondly, an opening is formed in the substrate, a first oxide layer is formed on the surface of the opening through the high temperature rapid thermal oxidation process, then a sedimentation technique is performed, so that a second oxide layer is formed on the first oxide layer, and finally a conductive layer is formed on the second oxide layer, and the opening is filled with the conductive layer.
Description
Technical field
The present invention relates to the method that the silicon through hole is worn in a kind of making, and is special, related to the method for wearing the silicon through hole that a kind of making has two-layer oxide layer.
Background technology
In the information society in modern times, by integrated circuit (integrated circuit, IC) microprocessing systems that consists of is already by the every aspect that generally applies to live, and such as the electrical home appliances of automatic control, mobile communication equipment, personal computer etc., the use of integrated circuit arranged.And along with day by day the progressing greatly of science and technology, and human society is for the various imaginations of electronic product, so that integrated circuit is also toward more polynary, more accurate, more small-sized future development.
General alleged integrated circuit is to form by the crystal grain (die) of producing in the existing semiconductor technology.Make the process of crystal grain, by producing a wafer (wafer) beginning: at first, distinguish a plurality of zones in a wafer, and on each zone, by various semiconductor technologies such as deposition, photoetching, etching or flatening process, to form various required circuit routes.Then, whether can operate smoothly with the testing inner element carrying out general testing procedure.Then, again the regional cutting on the wafer is formed each crystal grain, and be packaged into chip (chip), chip is electrically connected to a circuit board more at last, such as a printed circuit board (PCB) (printed circuit board, PCB), make pin (pin) electrically connect of chip and printed circuit board (PCB) after, just can carry out the various processing that stylize.
In order to improve chip functions and usefulness, increase integrated level in order under the confined space, can hold more multiple semiconductor element, relevant manufacturer develops the Stack Technology of many semiconductor wafers, comprised chip package (flip-chip) technology, multi-die package (multi-chip package, MCP) technology, encapsulation stacking (package on package, PoP) technology, encapsulate built-in packaging body (package in package, PiP) technology etc. can be by each other the stacking integrated level that increases semiconductor element in the unit volume between chip or packaging body.Develop again in recent years a kind of technology of wearing silicon through hole (through silicon via, TSV) that is called, can promote the interior bonds (interconnect) of each chip chamber in packaging body, so that stacking efficient is further up promoted.
In the existing technology, provide very convenient stack manner owing to wear the silicon through hole, therefore used in a large number, also opened the imagination of different chip designs.
Summary of the invention
The present invention proposes a kind of making and wear the method for silicon through hole, can form quality good wear through-silicon via structure.
According to an embodiment of the invention, the method for silicon through hole is worn in making of the present invention, at first provides a substrate, then forms perforate in substrate.Then a high-temperature quick oxidation technology forms one first oxide layer with the surface in perforate, and the follow-up depositing operation that carries out is to form the second oxide layer in the first oxide layer.At last, form conductive layer on the second oxide layer, conductive layer can fill up perforate.
The method of wearing the silicon through hole that forms provided by the present invention, one of them characteristic is to form the first oxide layer with the high-temperature quick oxidation technology, and collocation forms the second oxide layer with depositing operation.Only form oxide layer with single oxidation technology compared to prior art, the present invention forms the mode of two oxide layers with two different steps, not only can save cost, also can obtain the oxide layer of better quality, and can not consume the silicon atom in the substrate excessively.In addition, the electroplating technology when such mode also can be guaranteed to form conductive layer can carry out under oligosaprobic environment, has significantly promoted the degree of fine qualities of wearing the silicon through hole.
Description of drawings
Fig. 1 is to Figure 9 shows that the step schematic diagram that forms the method for wearing the silicon through hole among the present invention.
Wherein, description of reference numerals is as follows:
300 substrates, 312 first oxide layers
302 first surfaces, 314 second oxide layers
303 the 3rd surperficial 318 barrier layers
304 second surfaces, 320 conductive layers
306 patterning photoresists 322 are worn the silicon through hole
308 openings, 324 tin balls
310 perforates
Embodiment
For making those skilled in the art can further understand the present invention, the following description has been enumerated the several preferred implementations of the present invention, and cooperates accompanying drawing and explanation, the effect that realizes to describe content of the present invention and institute's wish in detail.
Please refer to Fig. 1 to Fig. 9, be depicted as the step schematic diagram that forms the method for wearing the silicon through hole among the present invention.As shown in Figure 1, one substrate 300 at first is provided, for example be silicon base (silicon substrate), epitaxial silicon substrate (epitaxial silicon substrate), SiGe semiconductor base (silicon germanium substrate), silicon carbide substrate (silicon carbide substrate) or silicon-coated insulated (silicon-on-insulator, SOI).Substrate 300 has a first surface 302 and a second surface 304.In the preferred embodiment of the present invention, first surface 302 for example is the active face (active surface) of substrate 300, and second surface 304 for example is the back side (back surface) of substrate 300.Substrate 300 thickness are substantially 700 to 1000 microns (micro meter), but not as limit.
As shown in Figure 2, at the first surface 302 formation one patterning photoresist 306 of substrate 300, wherein patterning photoresist 306 has an opening 308.The step that forms patterning photoresist 306 for example comprises a lithography step and a development step.In an embodiment of the invention, about 5 to 10 microns of the aperture of opening 308, but not as limit.
As shown in Figure 3, utilizing patterning photoresist 306 to carry out an etch process for mask, for example is a dry etching process, forms perforate 310 with the first surface 302 in substrate 300, and then strip pattern photoresist 306.In one embodiment of the invention, the degree of depth of perforate 310 for example is 50 to 100 microns, but is not limited to this, and visual product is done different the adjustment.
As shown in Figure 4, carry out a high-temperature quick oxidation (rapid thermal oxidation, RTO) technique, form one first oxide layer 312 with the side at the first surface 302 of substrate 300.In the preferred embodiment of the invention, the high-temperature quick oxidation technology for example is to carry out in the environment that is higher than 700 degree Celsius.The first oxide skin(coating) 312 can be formed uniformly on the surface of perforate 310 but can not fill up perforate 310.In an embodiment, the thickness of the first oxide layer 312 for example is 1 micron.
As shown in Figure 5, after forming the first oxide layer 312, then carry out again a depositing operation, for example be chemical vapour deposition (CVD) (chemical vapor deposition, CVD) technique or ald (atomic layer deposition, ALD) technique is to form one second oxide layer 314 in the first oxide layer 312.In a preferred embodiment of the invention, the material of the first oxide layer 312 and the second oxide layer 314 can be identical, for example all comprises silicon dioxide, but two material also can be different.In an embodiment, the thickness of the second oxide layer 314 is identical with the first oxide layer 312, for example is 1 micron.But in other embodiment, the thickness of the second oxide layer 314 can be different with the first oxide layer 312.
As shown in Figure 6, then form in substrate 300 and optionally form a barrier layer (barrier layer) 318 and one conductive layer 320, so that conductive layer 320 fills up perforate 310 fully.In one embodiment of the present invention, barrier layer 318 for example is metal tantalum (Tantalum, Ta), and can form by depositing operation; The material of conductive layer 320 for example is metallic copper, and it can form by the mode of electroplating.
As shown in Figure 7, carry out at last a flatening process, for example be chemico-mechanical polishing (chemical mechanical polish, CMP) technique or etch process or above-mentioned two combination, to remove perforate 310 conductive layer 320 and barrier layer 318 in addition, and preferably also can remove the first oxide layer 312 and the second oxide layer 314, so that the conductive layer 320 in the perforate 310 flushes haply with the first surface 302 of substrate 300.
As shown in Figure 8, carry out a thinning technique from a side of substrate 300 second surfaces 304, and be thinned to and expose conductive layer 320 or barrier layer 318.At this moment, the second surface after the thinning 304 becomes the 3rd surface 303.Thus, namely finished structure of wearing silicon through hole 322 of the present invention, wherein wearing silicon through hole 322 is first surface 302 and the 3rd surfaces 303 of running through substrate 300, and has the first oxide layer 312 and the second oxide layer 314 is arranged between substrate 300 and the conductive layer 320.
As shown in Figure 9, the follow-up conductive layer 320 that can also optionally wear silicon through hole 322 with electric connection at first surface 302 or the 3rd surface 303 formation tin balls 324 of substrate 300.Tin ball 324 can follow-up conduct and the signal contact point of other semiconductor chip (not shown).In other execution mode of the present invention, can also form other signal contact structures, for example be the structures such as re-wiring layer (redistribution layer, RLD).
The method that the silicon through hole is worn in aforementioned making can form technique with existing semiconductor element and be combined, for example can form the semiconductor element (not shown) in substrate 300 first for example is metal oxide semiconductor transistor (metal oxide semiconductor transistor, MOS transistor) or dynamic random access memory (Dynamic Random Access Memory, DRAM) after, form with step of the present invention again and wear the silicon through hole.After can also forming metal interconnecting system (not shown) at the first surface 302 of substrate 300, carry out again the thinning technique such as Fig. 8.
The method of silicon through hole is worn in formation provided by the present invention, and one of them characteristic is to form the first oxide layer with the high-temperature quick oxidation technology, and collocation forms the second oxide layer with depositing operation.Only form single oxide layer with single oxidation technology compared to prior art, the present invention forms the mode of two oxide layers with two different steps, not only can save cost, also can obtain the oxide layer of better quality, and can not consume the silicon atom in the substrate excessively.In addition, the electroplating technology when such mode also can be guaranteed to form conductive layer can carry out under oligosaprobic environment, has significantly promoted the degree of fine qualities of wearing the silicon through hole.
The above is the preferred embodiments of the present invention only, is not limited to the present invention, and for a person skilled in the art, the present invention can have various modifications and variations.Within the spirit and principles in the present invention all, any modification of doing, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (5)
1. the method that the silicon through hole is worn in making is characterized in that, comprising:
Substrate is provided;
In described substrate, form perforate;
Carry out the high-temperature quick oxidation technology, form the first oxide layer with the surface in described perforate;
Carry out depositing operation, to form the second oxide layer in described the first oxide layer; And
Form conductive layer on described the second oxide layer, described conductive layer fills up described perforate.
2. the method for silicon through hole is worn in making according to claim 1, it is characterized in that, described high-temperature quick oxidation technology is to carry out under the environment that is higher than 700 degree Celsius.
3. the method for silicon through hole is worn in making according to claim 1, it is characterized in that, described depositing operation comprises chemical vapor deposition method or atom layer deposition process.
4. the method for silicon through hole is worn in making according to claim 1, it is characterized in that, also comprises forming barrier layer between described the second oxide layer and described conductive layer.
5. the method for silicon through hole is worn in making according to claim 1, it is characterized in that also comprising and carrying out thinning technique, so that described conductive layer runs through described substrate after forming described conductive layer.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012101286346A CN103377994A (en) | 2012-04-27 | 2012-04-27 | Method for manufacturing through silicon hole |
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| Application Number | Priority Date | Filing Date | Title |
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| CN2012101286346A CN103377994A (en) | 2012-04-27 | 2012-04-27 | Method for manufacturing through silicon hole |
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| CN103377994A true CN103377994A (en) | 2013-10-30 |
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| CN2012101286346A Pending CN103377994A (en) | 2012-04-27 | 2012-04-27 | Method for manufacturing through silicon hole |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103943490A (en) * | 2014-05-08 | 2014-07-23 | 上海华力微电子有限公司 | Silicon through hole insulating layer production method |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102420210A (en) * | 2010-09-28 | 2012-04-18 | 台湾积体电路制造股份有限公司 | Device with through-silicon via (tsv) and method of forming the same |
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- 2012-04-27 CN CN2012101286346A patent/CN103377994A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102420210A (en) * | 2010-09-28 | 2012-04-18 | 台湾积体电路制造股份有限公司 | Device with through-silicon via (tsv) and method of forming the same |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103943490A (en) * | 2014-05-08 | 2014-07-23 | 上海华力微电子有限公司 | Silicon through hole insulating layer production method |
| CN103943490B (en) * | 2014-05-08 | 2017-01-18 | 上海华力微电子有限公司 | Silicon through hole insulating layer production method |
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Application publication date: 20131030 |