CN103378028B - There is semiconductor structure and its formation method of stress protection structure - Google Patents
There is semiconductor structure and its formation method of stress protection structure Download PDFInfo
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- CN103378028B CN103378028B CN201210108912.1A CN201210108912A CN103378028B CN 103378028 B CN103378028 B CN 103378028B CN 201210108912 A CN201210108912 A CN 201210108912A CN 103378028 B CN103378028 B CN 103378028B
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Abstract
The invention discloses a kind of semiconductor structure with stress protection structure, include substrate, stress producing component and stress protection device.Substrate has first surface and second surface, and two are oppositely arranged.Stress producing component is arranged in the substrate.Stress protection structure, is arranged on the side of substrate first surface, stress protection structure ambient stress producing component, and the Packed air space of stress protection inside configuration tool.Present invention also offers a kind of method that formation has the semiconductor structure of stress protection structure.
Description
Technical field
The present invention relates to a kind of semiconductor structure and its formation method with stress protection structure, special, this stress protection structure has airtight air space, can provide stress buffer effect.
Background technology
In the information society in modern times, by integrated circuit (integratedcircuit, IC) microprocessing systems formed is already by the every aspect generally applying to live, the electrical home appliances, mobile communication equipment, personal computer etc. that such as automatically control, have the use of integrated circuit.And day by day progressing greatly along with science and technology, and human society is for the various imaginations of electronic product, makes integrated circuit also toward more polynary, more accurate, more small-sized future development.
General alleged integrated circuit, is crystal grain (die) by producing in existing semiconductor technology and is formed.Manufacture the process of crystal grain, by production one wafer (wafer): first, a wafer distinguishes multiple region, and on each zone, by various semiconductor technology as deposition, photoetching, etching or flatening process, to form various required circuit traces.Then, carrying out general testing procedure whether can smooth operation with testing inner element.Then, again cutting is carried out to the regional on wafer and form each crystal grain, and be packaged into chip (chip), last again by chip electrical to circuit board, as a printed circuit board (PCB) (printedcircuitboard, PCB), after making pin (pin) electrically connect of chip and printed circuit board (PCB), the various process stylized can just be performed.
In order to improve chip functions and usefulness, increase integrated level more multiple semiconductor element can be held under the confined space, relevant manufactures develops the Stack Technology of many semiconductor wafers, include chip package (flip-chip) technology, multi-die package (multi-chippackage, MCP) technology, encapsulation stacking (packageonpackage, PoP) technology, encapsulate built-in packaging body (packageinpackage, PiP) technology etc., can by the stacking integrated level increasing semiconductor element in unit volume each other between wafer or packaging body.Develop again one in recent years and be called the technology of wearing silicon through hole (throughsiliconvia, TSV), the interior bonds (interconnect) of each chip chamber in packaging body can be promoted, stacking efficiency up to be promoted further.
But, in existing encapsulation technology, utilize and wear silicon through hole to stack the structure of encapsulation, be still faced with many problems.Please refer to Fig. 1, be depicted as in known technology the end face schematic diagram wearing silicon through hole.As shown in Figure 1, known silicon through hole 102 of wearing is arranged in substrate 100.But, owing to wearing the material such as metallic copper in silicon through hole 102, with the material of substrate 100 such as semiconductor silicon, between can there is thermal coefficient of expansion (coefficientofthermalexpansion, CTE) difference, the thermal coefficient of expansion of such as copper is about 17.5 × 10
-6k
-1and the thermal coefficient of expansion of silicon is about 2.5 × 10
-6k
-1, such situation can make substrate 300 can have the stress of different directions and intensity when different temperatures.In prior art, the external zones (keepoutregion) 104 of wearing around silicon through hole 102 is that stress produces the most seriously and the most complicated place to have manufacturer to propose.The chances are in external zones 104 from the place of wearing beyond silicon through hole 102 10 millimeters to 20 millimeters, element in this region can suffer complicated stress when high temperature and low temperature, such as, are expansion force (tensile) annular sections on external zones 104 from the radiation direction outward of wearing silicon through hole 102 be then compression stress (compressive).The stress system of such complexity is also not suitable for the setting of element, and easily causes the damage of element.
But in the integrated circuit that current size reduces day by day, the existence of external zones 104 will certainly limit the integrated of semiconductor element, and is unfavorable for the design of more advanced technologies.Therefore, a kind of semiconductor technology and structure of novelty is also needed, to solve the problem.
Summary of the invention
The present invention in there is provided a kind of semiconductor structure with stress protection structure with and preparation method thereof, to solve the problem of stress in prior art.
According to an embodiment of the invention, the present invention is to provide a kind of semiconductor structure with stress protection structure, includes substrate, stress producing component and stress protection device.Substrate has first surface and second surface, and two are oppositely arranged.Stress producing component is arranged in the substrate.Stress protection structure, is arranged on the side of substrate first surface, stress protection structure ambient stress producing component, and the Packed air space of stress protection inside configuration tool.
Execution mode according to another preferred, invention provides a kind of method that formation has the semiconductor structure of stress protection structure.First provide substrate, it has first surface and second surface, and two are oppositely arranged.Then on the first surface side of substrate, form continuous print irrigation canals and ditches, irrigation canals and ditches surround presumptive area.Then dielectric layer, the first metal layer and the second metal level is formed in the trench successively, to form air space in the trench.Finally, dielectric layer, the first metal layer and the second metal level beyond irrigation canals and ditches is removed, to form stress protection structure.
Stress protection structure provided by the present invention, has air space in it, therefore can provide suitable stress buffer, to reach protection stress producing component, such as, wears effect of silicon through hole.
Accompanying drawing explanation
Figure 1 shows that the end face schematic diagram being depicted as in known technology and wearing silicon through hole.
Fig. 2 is to Figure 8 shows that the present invention forms the step schematic diagram of the semiconductor structure with stress protection structure.
Fig. 9 and the vertical view that Figure 10 shows that stress protection structure of the present invention.
Wherein, description of reference numerals is as follows:
100 substrate 314 presumptive areas
102 wear silicon through hole 316 dielectric layer
104 external zones 318 barrier layers
300 substrate 320 the first metal layers
302 first surface 322 second metal levels
304 second surface 324 air spaces
306 semiconductor element 326 stress protection structures
308 impure wells 328 wear silicon through hole
310 inner layer dielectric layers 330 the 3rd surface
312 irrigation canals and ditches
Embodiment
For making those skilled in the art can understand the present invention further, the following description has enumerated the several preferred implementation of the present invention, and coordinates accompanying drawing and explanation, with describe in detail content of the present invention and wish realize effect.
In order to overcome the above-mentioned problem wearing complex stress near silicon through hole, the present invention defines a stress protection structure, the Packed air space of tool in it wearing around silicon through hole, and is enclosed in and wears around silicon through hole.Please refer to Fig. 2 to Fig. 8, be depicted as the present invention and form the step schematic diagram with the semiconductor structure of stress protection structure.As shown in Figure 2, first one substrate 300 is provided, such as silicon base (siliconsubstrate), epitaxial silicon substrate (epitaxialsiliconsubstrate), silicon germanium semiconductor substrate (silicongermaniumsubstrate), silicon carbide substrate (siliconcarbidesubstrate) or silicon-coated insulated (silicon-on-insulator, SOI).Substrate 300 has first surface 302 and a second surface 304.In the preferred embodiment of the present invention, first surface 302 is such as the active face (activesurface) of substrate 300, and second surface 304 is such as the back side (backsurface) of substrate 300.Substrate 300 thickness is substantially 700 to 1000 microns (micrometer), but not as limit.Then, the first surface 302 of substrate 300 forms semiconductor element 306 by various semiconductor technology, it can be the structure such as MOS (metal-oxide-semiconductor) transistor (metaloxidesemiconductortransistor, MOStransistor) or dynamic random access memory (DRAM).Preferably, semiconductor element 306 can have an admixture well (dopingwell) 308, such as, be N-type admixture well or P type admixture well.Then, after completing semiconductor element 306, on the first surface 302 of substrate 300, then form an inner layer dielectric layer (interlayerdielectric, ILD) 310 cover on semiconductor element 306, its material is such as silicon dioxide.Then can be formed to insert in inner layer dielectric layer 310 and fasten and ohmic contact (Ohmcontact) (not shown), to be electrically connected semiconductor element 306.
As shown in Figure 3, then in inner layer dielectric layer 310 and substrate 300, form irrigation canals and ditches 312, wherein irrigation canals and ditches 312 are understood continuously and are surrounded a presumptive area 314.Forming the method for irrigation canals and ditches 312 is such as formed by photoetching and dry etching process, and dry etching process can etch inner layer dielectric layer 310 goes forward side by side a step etching to substrate 300.In the preferred embodiments of the present invention, the width of irrigation canals and ditches 312 is 0.4 micron to 1 micron substantially, and the degree of depth can be deeper than the degree of depth of impure well 308 in semiconductor element 306, such as (if having data ask inventor can provide) micron darker in impure well 308.
As shown in Figure 4, the surface of irrigation canals and ditches 312 is formed a dielectric layer 316, but dielectric layer 316 can't fill up irrigation canals and ditches 312.The method forming dielectric layer 316 can pass through chemical vapour deposition (CVD) (chemicalvapordeposition, CVD), such as, be ald (AtomicLayerDeposition, ALD) technique.The thickness of the dielectric layer 316 formed is greatly between 500 dust to 750 dusts.
As shown in Figure 5, formation one optionally barrier layer 320 and a first metal layer 318 on the surface of irrigation canals and ditches 312, wherein barrier layer 320 and the first metal layer 318 can't fill up irrigation canals and ditches 312.The method forming barrier layer 320 and the first metal layer 318 can pass through chemical vapor deposition method.The material of barrier layer 320 is such as titanium/titanium nitride (Ti/TiN), and the material of the first metal layer 318 is such as tungsten (W), and the first metal layer 318 thickness is greatly about 500 dust to 1000 dusts.
As shown in Figure 6, utilize another one depositing operation in substrate 300, form the second metal level 322.In the preferred embodiment of the present invention, this depositing operation is physical gas-phase deposition (physicalvapordeposition, PVD), such as, be sputtering (sputtering) technique.And the preferred material of the second metal level 322 is identical with the first metal layer 318, such as, it is all tungsten.Thus, if the thickness that suitable adjustment second metal level 322 is formed, the top of irrigation canals and ditches 312 just can be made to be sealed by the second metal level 322, but an air space (void) 324 can be formed in the inside of irrigation canals and ditches 312.In the preferred embodiment of the invention, air space 324 occupies the position of most of irrigation canals and ditches 316, and the degree of depth bottom it also can be deeper than the degree of depth of impure well 308.
As shown in Figure 7, carry out a flatening process, such as chemico-mechanical polishing (chemicalmechanicalpolish, CMP) technique or etch back process, or above-mentioned combination, to remove the second metal level 322, the first metal layer 318 and the barrier layer 320 beyond irrigation canals and ditches 312.Thus, namely complete stress protection structure 326 of the present invention, wherein stress protection structure 326 can surround presumptive area 314.
As shown in Figure 8, forming semiconductor structure in the follow-up presumptive area 314 can surrounded in stress protection structure 326 is such as wear silicon through hole 328.Forming the step of wearing silicon through hole 328 is such as after first surface 302 up one-tenth one irrigation canals and ditches of substrate 300, again irrigation canals and ditches are inserted suitable isolation material and conductive material successively, preferably, a thinning technique can also be carried out further from the second surface 304 of substrate 300, second surface 304 is made to become the 3rd surface 330, to expose conductive material, described wear silicon through hole 328 to be formed.
It should be noted that forming stress protection structure 326 can adjust with the order of wearing silicon through hole 328, such as, first formed after wearing silicon through hole 328, then form stress protection structure 326.Or after first carrying out being formed the part manufacture craft of wearing silicon through hole 328, then form stress protection structure 326, finally carry out part manufacture craft again and wear silicon through hole 328 to be fully formed.In addition, stress protection structure 326 of the present invention can provide stress protection, is not only for wearing silicon through hole 328, also may be that other easily produce devices of stress.
And in another one embodiment; when the step of the barrier layer 320 forming aforesaid stresses operator guards 326 and the first metal layer 318 or the second metal level 322; also can be formed, to save time and the cost of manufacture craft with being formed together with the structures such as the ohmic contact (not shown) in semiconductor element 306.
As shown in Figure 8, the invention provides a kind of semiconductor structure with stress protection device, comprise substrate 300, inner layer dielectric layer 310, wear silicon through hole 328 and stress protection structure 326.Substrate 300 has first surface 302 and the 3rd surface 330, and both are oppositely arranged.Wear silicon through hole 328 to be arranged in substrate 300 and to run through first surface 302 and the 3rd surface 330.Stress protection structure 326 is arranged in substrate 300 and inner layer dielectric layer 310, its air space 324 comprising dielectric layer 316, the first metal layer 320 from outside to inside successively and seal.In addition, in stress protection structure 326, air space 324 top is the second metal level 322, and in an embodiment, the first metal layer 320 and the second metal level 322 have identical material.Owing to there is air space 324 in stress protection structure 326; little next relative to other materials of its thermal coefficient of expansion; therefore suitable buffer capacity can be provided, for wearing the contiguous place such as semiconductor element 306 of silicon through hole 328, effect of stress protection can be provided.In an embodiment, the degree of depth of stress protection structure 326 can be greater than the degree of depth of impure well 308 in semiconductor element 306.In an execution mode, stress protection structure 326 is continuous print ring type structures, and it can be various geometry.Please refer to Fig. 9 and Figure 10, be depicted as the vertical view of stress protection structure of the present invention.As shown in Figure 9, stress protection structure 326 can be circular, or as shown in Figure 10, stress protection structure 326 also can be square.
In sum, stress protection structure provided by the present invention, has air space in it, therefore can provide suitable stress buffer, to reach protection stress producing component, such as, wears effect of silicon through hole.
The foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, for a person skilled in the art, the present invention can have various modifications and variations.Within the spirit and principles in the present invention all, any amendment done, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (14)
1. there is a semiconductor structure for stress protection structure, it is characterized in that, comprising:
Substrate, has first surface and second surface, and two are oppositely arranged;
Stress producing component, is arranged in described substrate; And
Stress protection structure, is arranged on the side of the described first surface of described substrate, and described stress protection structure surrounds described stress producing component, and described stress protection structure comprises the air space of dielectric layer, metal level and sealing from outside to inside successively.
2. the semiconductor structure with stress protection structure according to claim 1, is characterized in that also having inner layer dielectric layer, is arranged on the side of the described first surface of described substrate.
3. the semiconductor structure with stress protection structure according to claim 2, is characterized in that, described stress protection structure position is in described inner layer dielectric layer and described substrate.
4. the semiconductor structure with stress protection structure according to claim 1, is characterized in that, described stress protection structure also comprises barrier layer, is arranged on described dielectric layer and described metal interlevel.
5. the semiconductor structure with stress protection structure according to claim 1, is characterized in that, described stress protection structure is continuous structure, to surround described stress producing component completely.
6. the semiconductor structure with stress protection structure according to claim 1, is characterized in that, described stress producing component for wearing silicon through hole, described in wear silicon through hole and run through described first surface and described second surface.
7. formation has a method for the semiconductor structure of stress protection structure, it is characterized in that, comprising:
There is provided substrate, it has first surface and second surface, and two are oppositely arranged, and wherein said substrate has a presumptive area of a stress producing component;
The described first surface side of described substrate forms continuous print irrigation canals and ditches, and described irrigation canals and ditches surround described presumptive area;
Dielectric layer, the first metal layer and the second metal level is formed successively, to form the air space of sealing in described irrigation canals and ditches in described irrigation canals and ditches; And
Remove dielectric layer, the first metal layer and the second metal level beyond irrigation canals and ditches, to form described stress protection structure.
8. formation according to claim 7 has the method for the semiconductor structure of stress protection structure; it is characterized in that; form inner layer dielectric layer being formed on the side being also included in described first surface before described irrigation canals and ditches, and described irrigation canals and ditches can be formed in described inner layer dielectric layer and described substrate.
9. formation according to claim 7 has the method for the semiconductor structure of stress protection structure, it is characterized in that, also comprises and forms barrier layer in the trench, between described dielectric layer and described the first metal layer.
10. formation according to claim 7 has the method for the semiconductor structure of stress protection structure, it is characterized in that, described the first metal layer and described second metal level comprise identical material.
11. formation according to claim 7 have the method for the semiconductor structure of stress protection structure, it is characterized in that, the step forming described the first metal layer comprises chemical vapor deposition method.
12. formation according to claim 7 have the method for the semiconductor structure of stress protection structure, it is characterized in that, the step forming described second metal level comprises physical gas-phase deposition.
13. formation according to claim 7 have the method for the semiconductor structure of stress protection structure, it is characterized in that, are also included in described presumptive area and form stress producing component.
14. formation according to claim 13 have the method for the semiconductor structure of stress protection structure, it is characterized in that, described stress producing component for wearing silicon through hole, described in wear silicon through hole and run through described first surface and described second surface.
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| CN103824758A (en) * | 2014-03-13 | 2014-05-28 | 华进半导体封装先导技术研发中心有限公司 | Method for reducing stress on peripheral region of silicon through hole |
| CN107980171B (en) * | 2016-12-23 | 2022-06-24 | 苏州能讯高能半导体有限公司 | Semiconductor chip, semiconductor wafer, and method for manufacturing semiconductor wafer |
| CN109560039A (en) * | 2018-10-31 | 2019-04-02 | 西安理工大学 | A method of TSV thermal stress is weakened by STI |
| CN115602647A (en) * | 2021-07-08 | 2023-01-13 | 长鑫存储技术有限公司（Cn） | Semiconductor structure and forming method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101783329A (en) * | 2009-01-13 | 2010-07-21 | 台湾积体电路制造股份有限公司 | Semiconductor component and manufacturing method thereof |
| CN102222654A (en) * | 2010-04-16 | 2011-10-19 | 南亚科技股份有限公司 | Semiconductor device with through substrate via and its production method |
| CN102412197A (en) * | 2010-09-22 | 2012-04-11 | 新科金朋有限公司 | Semiconductor device and method of forming conductive tsv with insulating annular ring |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101783329A (en) * | 2009-01-13 | 2010-07-21 | 台湾积体电路制造股份有限公司 | Semiconductor component and manufacturing method thereof |
| CN102222654A (en) * | 2010-04-16 | 2011-10-19 | 南亚科技股份有限公司 | Semiconductor device with through substrate via and its production method |
| CN102412197A (en) * | 2010-09-22 | 2012-04-11 | 新科金朋有限公司 | Semiconductor device and method of forming conductive tsv with insulating annular ring |
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