CN103824758A - Method for reducing stress on peripheral region of silicon through hole - Google Patents
Method for reducing stress on peripheral region of silicon through hole Download PDFInfo
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- CN103824758A CN103824758A CN201410091123.0A CN201410091123A CN103824758A CN 103824758 A CN103824758 A CN 103824758A CN 201410091123 A CN201410091123 A CN 201410091123A CN 103824758 A CN103824758 A CN 103824758A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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Abstract
The invention relates to a method for reducing stress on the peripheral region of a silicon through hole. The silicon through hole can be subjected to etching, side wall insulation, seed layer deposition, through hole filling and other process steps in a preparation process to generate process residual stress; in addition, the thermal expansion coefficient of copper is greatly different from that of a peripheral material, therefore, a certain stress concentration phenomenon is generated on the periphery region of the silicon through hole, and the stress can bring adverse effects on the performances and reliabilities of semiconductor devices around the silicon through hole. The invention provides a solution for processing a stress eliminating structure with a certain depth and specific shape within a certain region at the periphery of the silicon through hole in order to overcome the limitation of reducing the stress at the periphery of the hole and the stress influence range in an annealing way adopted at present. Compared with the prior art, the method has the beneficial effects that the process complexity of the annealing way for eliminating the stress is lowered, the area of a stress influence region is greatly reduced, the service life of the silicon through hole can be remarkably prolonged and the working stability of peripheral devices can be remarkably improved through arranging the specific stress eliminating structure within a certain region at the periphery of the silicon through hole by using the traditional etching way, and the method has the advantages of simple and reliable process and easiness for realization.
Description
Technical field
The present invention relates to a kind of method of manufacturing or processing semiconductor or solid state device of microelectronics technology, relate in particular to a kind of method that how to reduce silicon through hole peripheral region stress.
Background technology
Along with the development electronic device of semiconductor technology does less and less, integrated level is more and more higher, and the function comprising is more and more, and the overall performance of device is more and more stronger.Semiconductor technology characteristic size has reached nanoscale, and the limitation that integrated circuit continues scaled down is day by day serious, more and more approaches the limit of physics.Therefore, the integrated or integrated integrated important technology direction of microelectronic system level that becomes of 3D of density three-dimensional, it can effectively meet the requirement of the high-frequency high-speed of electronic device, multi-functional, high-performance, low-power consumption, small size and high reliability.
Silicon through hole or pentration hole (TSV) technology are one of guardian techniques of realizing 3D system-level integrated (System in package).3D TSV be by between chip and chip, between wafer and wafer, make vertical through hole and realize the state-of-the-art technology interconnecting between chip.It is advantageous that the perpendicular interconnection path that provides the shortest, reduce circuit delay and power consumption, reduce the restriction to I/O Pin locations, improve I/O bandwidth chahnel.But the manufacturing process of silicon through hole is comparatively complicated, mainly comprises silicon hole etching, insulating barrier/barrier/seed layers deposition, filling through hole, cmp, wafer bonding, tear bonding open, wafer attenuate, metal connect up making, Solder bumping etc. again.Above-mentioned steps all can cause the peripheral region of silicon through hole as etching, filling through hole and follow-up heat treatment, the particularly region within 50 microns, occur certain stress phenomena, this stress can bring adverse effect to the normal work of the adjacent devices of the useful life of silicon through hole and silicon through hole perimeter.The main mode adopting copper annealing at present, reduce hole ambient stress and influence range of stress (KOZ, Keep-Out-Zone), this method belongs to traditional method, heat treatment itself will bring certain stress, therefore can have influence on the elimination of stress.Publication number is that the United States Patent (USP) of US2013/0049220A1 proposes the solution that stress bolt (stress plug) is set around TSV and reduces above-mentioned stress by the specific space arrangement of the two, but need to consider the direction of silicon crystal lattice, the difficulty that technology realizes is very large.
Summary of the invention
In order to solve the concentrated problem of above-mentioned silicon through hole peripheral region stress, the present invention proposes a kind of method that reduces silicon through hole peripheral region stress, and technical scheme is as follows:
A method that reduces silicon through hole peripheral region stress, comprises the following steps:
A, provides substrate;
B carries out silicon through hole preparation technology on substrate;
C processes the stress relief structure of certain depth and given shape on the peripheral substrate of above-mentioned silicon through hole in certain area.
As preferably, the stress relief structure in above-mentioned steps c is circular groove.
Stress relief structure in above-mentioned steps c can also be square groove, or the deep-slotted chip breaker not sealing, trough with straight angle.Further, the stress relief structure in above-mentioned steps c can also be made up of discrete aperture annulus, square, deep-slotted chip breaker, right angle or other shapes of not sealing.
The scope of the certain area in above-mentioned steps c be silicon through hole around 50 microns with inner region.
The scope of the certain depth in above-mentioned steps c is downward 1-100 micron from substrate surface.
In above-mentioned steps c, the processing technology of stress relief structure can be dry etching or wet etching.
Compared with prior art, beneficial effect of the present invention has been to overcome the process complexity that annealing way eliminates stress, only need in certain area around silicon through hole, utilize traditional etching mode to offer the stress relief structure of ad hoc structure, just can significantly improve the useful life of silicon through hole and the job stability of peripheral components, there is simple and reliable process, easily realize.
Accompanying drawing explanation
Below in conjunction with accompanying drawing, specific embodiment of the invention is described further.
Fig. 1 is that stress relief structure is the vertical view of circular groove.
Fig. 2 is that stress relief structure is the vertical view of square shape groove.
Fig. 3 is that stress relief structure is the vertical view of the deep-slotted chip breaker that do not seal.
Fig. 4 is that stress relief structure is the vertical view of the annulus of discrete hole composition.
Fig. 5 is the cutaway view of silicon through hole and stress relief structure.
Embodiment
In Fig. 1,1 is silicon through hole, 2 stress relief structures that are circular groove.This annulus and silicon through hole are concentric structure, but in actual design process, can be also non-concentric circles.Circular groove 2 depends on the factors such as silicon through-hole diameter, height with the distance of silicon through hole 1, conventionally can be at 0-50 micrometer range, and the degree of depth of circular groove 2 also depends on the factors such as silicon through-hole diameter, height, is generally 0-100 micrometer range.This stress relief structure is eliminated more even for the stress of silicon through hole peripheral region, be applicable to also more uniform occasion of device distribution.Fig. 2 and Fig. 1 are very similar, and difference is to have replaced circular groove with a square groove 2.In Fig. 3,1 is silicon through hole, 2 stress relief structures that are the deep-slotted chip breaker that do not seal.Deep-slotted chip breaker is around silicon through hole symmetric arrays, but also can only have a deep-slotted chip breaker or multiple deep-slotted chip breaker depending on concrete condition.In Fig. 4,2 represent the stress relief structure that the annulus that is made up of discrete aperture forms, because a schematic diagram just, the shape of the discrete aperture here can be not limited to circle, can be square, rectangle or other shapes.
And the stress relief structure providing in above-mentioned Fig. 1 to 4 can also be in the depth bounds of the area of 0-50 micrometer range around silicon through hole and substrate surface 0-100 micron combination in any, be not limited to and use a kind of structure.
Fig. 5 is a profile, demonstrates stress relief structure and silicon through hole position relation in vertical direction.
Stress relief structure in above-mentioned Fig. 1 to 5, can be by the processing technology preparation of dry etching or wet etching.
Compared with prior art, beneficial effect of the present invention has been to overcome the process complexity that annealing way eliminates stress, only need in certain area around silicon through hole, utilize traditional etching mode to offer the stress relief structure of ad hoc structure, just can significantly improve the useful life of silicon through hole and the job stability of peripheral components, there is simple and reliable process, easily realize.
For those of ordinary skills, obviously the invention is not restricted to the details of above-mentioned one exemplary embodiment, in the situation that not deviating from spirit of the present invention or essential characteristic, also can realize the present invention with other concrete form.Therefore, all should regard above-described embodiment as exemplary, and be nonrestrictive.
Claims (6)
1. a method that reduces silicon through hole peripheral region stress, is characterized in that comprising the following steps:
A, provides substrate;
B carries out silicon through hole preparation technology on substrate;
C processes the stress relief structure of certain depth and given shape on the peripheral substrate of above-mentioned silicon through hole in certain area.
2. method according to claim 1, is characterized in that the stress relief structure in above-mentioned steps c is circular groove.
3. method according to claim 1, it is characterized in that the stress relief structure in above-mentioned steps c can also be square groove, the deep-slotted chip breaker not sealing, trough with straight angle, the annulus being formed by discrete aperture, square, deep-slotted chip breaker, right angle or other shapes of not sealing.
4. method according to claim 1, the scope that it is characterized in that the certain area described in above-mentioned steps c be silicon through hole around 50 microns with inner region.
5. method according to claim 1, the scope that it is characterized in that the certain depth described in above-mentioned steps c is downward 1-100 micron from substrate surface.
6. method according to claim 1, the processing technology that it is characterized in that stress relief structure in above-mentioned steps c can be by dry etching or wet etching.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201410091123.0A CN103824758A (en) | 2014-03-13 | 2014-03-13 | Method for reducing stress on peripheral region of silicon through hole |
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| CN201410091123.0A CN103824758A (en) | 2014-03-13 | 2014-03-13 | Method for reducing stress on peripheral region of silicon through hole |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105157735A (en) * | 2015-08-20 | 2015-12-16 | 龙微科技无锡有限公司 | Sensor chip, manufacturing method thereof, encapsulation method and sensor core |
| CN105633013A (en) * | 2014-11-21 | 2016-06-01 | 格罗方德半导体U.S.2有限责任公司 | Non-contiguous dummy structure surrounding through-substrate via near integrated circuit wires |
| CN105967137A (en) * | 2015-03-12 | 2016-09-28 | 台湾积体电路制造股份有限公司 | Structure and method to mitigate soldering offset for wafer-level chip scale package (WLCSP) applications |
| CN107293522A (en) * | 2016-04-11 | 2017-10-24 | 南亚科技股份有限公司 | Semiconductor device and its manufacture method |
| CN107611081A (en) * | 2016-07-12 | 2018-01-19 | 蔡佳勋 | Semiconductor structure and its manufacture method |
| CN109560039A (en) * | 2018-10-31 | 2019-04-02 | 西安理工大学 | A method of TSV thermal stress is weakened by STI |
| CN113903724A (en) * | 2020-07-06 | 2022-01-07 | 长鑫存储技术有限公司 | Semiconductor structure |
| US11990390B2 (en) | 2020-07-06 | 2024-05-21 | Changxin Memory Technologies, Inc. | Semiconductor structure |
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| US20120001330A1 (en) * | 2010-06-30 | 2012-01-05 | Globalfoundries Inc. | Semiconductor Device Comprising Through Hole Vias Having a Stress Relaxation Mechanism |
| CN102938396A (en) * | 2012-11-07 | 2013-02-20 | 清华大学 | Silicon through hole structure and manufacture method thereof |
| CN103378028A (en) * | 2012-04-13 | 2013-10-30 | 南亚科技股份有限公司 | Semiconductor structure with stress protection structure and forming method of semiconductor structure |
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2014
- 2014-03-13 CN CN201410091123.0A patent/CN103824758A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US20120001330A1 (en) * | 2010-06-30 | 2012-01-05 | Globalfoundries Inc. | Semiconductor Device Comprising Through Hole Vias Having a Stress Relaxation Mechanism |
| CN103378028A (en) * | 2012-04-13 | 2013-10-30 | 南亚科技股份有限公司 | Semiconductor structure with stress protection structure and forming method of semiconductor structure |
| CN102938396A (en) * | 2012-11-07 | 2013-02-20 | 清华大学 | Silicon through hole structure and manufacture method thereof |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105633013A (en) * | 2014-11-21 | 2016-06-01 | 格罗方德半导体U.S.2有限责任公司 | Non-contiguous dummy structure surrounding through-substrate via near integrated circuit wires |
| CN105967137A (en) * | 2015-03-12 | 2016-09-28 | 台湾积体电路制造股份有限公司 | Structure and method to mitigate soldering offset for wafer-level chip scale package (WLCSP) applications |
| CN105967137B (en) * | 2015-03-12 | 2018-10-23 | 台湾积体电路制造股份有限公司 | Alleviate the structures and methods of welding offset for crystal wafer chip dimension encapsulation part (WLCSP) application |
| US10131540B2 (en) | 2015-03-12 | 2018-11-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Structure and method to mitigate soldering offset for wafer-level chip scale package (WLCSP) applications |
| CN105157735A (en) * | 2015-08-20 | 2015-12-16 | 龙微科技无锡有限公司 | Sensor chip, manufacturing method thereof, encapsulation method and sensor core |
| CN107293522A (en) * | 2016-04-11 | 2017-10-24 | 南亚科技股份有限公司 | Semiconductor device and its manufacture method |
| CN107611081A (en) * | 2016-07-12 | 2018-01-19 | 蔡佳勋 | Semiconductor structure and its manufacture method |
| CN109560039A (en) * | 2018-10-31 | 2019-04-02 | 西安理工大学 | A method of TSV thermal stress is weakened by STI |
| CN113903724A (en) * | 2020-07-06 | 2022-01-07 | 长鑫存储技术有限公司 | Semiconductor structure |
| WO2022007611A1 (en) * | 2020-07-06 | 2022-01-13 | 长鑫存储技术有限公司 | Semiconductor structure |
| CN113903724B (en) * | 2020-07-06 | 2023-03-24 | 长鑫存储技术有限公司 | Semiconductor structure |
| US11990390B2 (en) | 2020-07-06 | 2024-05-21 | Changxin Memory Technologies, Inc. | Semiconductor structure |
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Application publication date: 20140528 |