CN108109996B - Diode-based antistatic adapter plate for integrated circuit and preparation method thereof - Google Patents
Diode-based antistatic adapter plate for integrated circuit and preparation method thereof Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 72
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 61
- 239000000463 material Substances 0.000 claims abstract description 61
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 61
- 239000010703 silicon Substances 0.000 claims abstract description 61
- 238000002955 isolation Methods 0.000 claims abstract description 56
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 45
- 238000004519 manufacturing process Methods 0.000 claims abstract description 34
- 238000011049 filling Methods 0.000 claims abstract description 29
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 23
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 22
- 229910052751 metal Inorganic materials 0.000 claims abstract description 15
- 239000002184 metal Substances 0.000 claims abstract description 15
- 239000007769 metal material Substances 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 97
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 23
- 229910052802 copper Inorganic materials 0.000 claims description 23
- 239000010949 copper Substances 0.000 claims description 23
- 238000000151 deposition Methods 0.000 claims description 21
- 238000001259 photo etching Methods 0.000 claims description 20
- 238000002161 passivation Methods 0.000 claims description 19
- 238000005530 etching Methods 0.000 claims description 16
- 150000002500 ions Chemical class 0.000 claims description 14
- 238000005229 chemical vapour deposition Methods 0.000 claims description 10
- 238000005468 ion implantation Methods 0.000 claims description 10
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 10
- 238000007747 plating Methods 0.000 claims description 7
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 7
- 229910052721 tungsten Inorganic materials 0.000 claims description 7
- 239000010937 tungsten Substances 0.000 claims description 7
- 238000001312 dry etching Methods 0.000 claims description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 4
- 238000000137 annealing Methods 0.000 claims description 4
- 229910052796 boron Inorganic materials 0.000 claims description 4
- 238000000708 deep reactive-ion etching Methods 0.000 claims description 4
- 238000000227 grinding Methods 0.000 claims description 4
- 239000012535 impurity Substances 0.000 claims description 4
- 229910052698 phosphorus Inorganic materials 0.000 claims description 4
- 239000011574 phosphorus Substances 0.000 claims description 4
- 238000005240 physical vapour deposition Methods 0.000 claims description 4
- 238000007517 polishing process Methods 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 4
- 238000001039 wet etching Methods 0.000 claims description 4
- 229910052681 coesite Inorganic materials 0.000 claims 1
- 229910052906 cristobalite Inorganic materials 0.000 claims 1
- 229910052682 stishovite Inorganic materials 0.000 claims 1
- 229910052905 tridymite Inorganic materials 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
- 230000003071 parasitic effect Effects 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 239000003292 glue Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
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- 238000006467 substitution reaction Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
Abstract
The invention relates to an integrated circuit antistatic adapter plate based on a diode and a preparation method thereof, wherein the preparation method comprises the following steps: (a) selecting a silicon-based substrate; (b) manufacturing a diode in a first appointed area in the silicon-based substrate; (c) respectively manufacturing a TVS hole and an isolation groove in a second designated area and a third designated area in the silicon-based substrate; (d) filling the isolation trench and the TVS hole with a silicon dioxide material and a metal material respectively; (e) manufacturing metal interconnection lines on the TSV holes and the upper surfaces of the diodes so that the TSV holes are connected with the diodes; (f) removing partial material on the bottom of the silicon-based substrate to expose the TSV hole, the isolation trench and the diode on the bottom of the silicon-based substrate; (g) and manufacturing salient points on the TSV hole and the lower surface of the diode. According to the diode-based antistatic adapter plate for the integrated circuit, provided by the invention, the diode is processed on the TSV adapter plate to serve as an ESD protection device, so that the antistatic capability of the stacked and packaged chip is enhanced.
Description
Technical Field
The invention relates to the field of design and manufacture of semiconductor devices, in particular to an integrated circuit antistatic adapter plate based on a diode and a preparation method thereof.
Background
The characteristic size of an integrated circuit is as low as 7nm so far, the number of transistors integrated on a single chip reaches the billion level, along with the requirement of the number of transistors at the billion level, the problem of on-chip resources and the length of interconnection lines become the bottleneck of the development of the field of the integrated circuit at present, a 3D integrated circuit is considered as the development direction of the future integrated circuit, the 3D integrated circuit is laminated on the Z axis on the basis of the original circuit so as to integrate more functions on the minimum area, the method overcomes the limitation of the original integration level, and the performance of the integrated circuit is greatly improved, the on-line delay is reduced, and the power consumption of the chip is reduced by adopting a Silicon Through hole (TSV) which is an emerging technology.
The potential for damage caused by electrostatic discharge in integrated circuits has become more apparent within the semiconductor industry as the integration of integrated circuits has increased and the feature sizes of devices have decreased. It is reported that nearly 35% of failures in the field of integrated circuits are caused by Electro-Static discharge (ESD), so that ESD protection structures are designed inside chips to improve the reliability of devices. However, different chips have different antistatic capabilities, and a chip with a weak antistatic capability affects the antistatic capability of the whole system after packaging when three-dimensionally stacked, so how to improve the antistatic capability of the 3D integrated circuit based on the TSV process becomes a problem to be solved urgently in the semiconductor industry.
Disclosure of Invention
In order to solve the technical defects and shortcomings in the prior art, the invention provides an adapter plate capable of improving the antistatic capacity of an integrated circuit and a preparation method thereof.
In one embodiment of the invention, a method for preparing a diode-based integrated circuit antistatic adapter plate is provided. The preparation method comprises the following steps:
(a) selecting a silicon-based substrate;
(b) manufacturing a diode in a first appointed area in the silicon-based substrate;
(c) respectively manufacturing a TVS hole and an isolation groove in a second designated area and a third designated area in the silicon-based substrate;
(d) filling the isolation trench and the TVS hole with a silicon dioxide material and a metal material respectively;
(e) manufacturing metal interconnection lines on the TSV holes and the upper surfaces of the diodes so that the TSV holes are connected with the diodes;
(f) removing partial material on the bottom of the silicon-based substrate to expose the TSV hole, the isolation trench and the diode on the bottom of the silicon-based substrate;
(g) and manufacturing salient points on the TSV hole and the lower surface of the diode.
In one embodiment of the invention, the doping concentration of the silicon-based substrate is 3 x 1014～5×1017cm-3。
In one embodiment of the present invention, step (b) comprises:
(b1) manufacturing a first ion to-be-implanted area on the upper surface of the silicon-based substrate by adopting a photoetching process;
(b2) doping boron into the region to be implanted through the first ions by adopting a glue-carrying ion implantation process so as to form a P + region in the silicon-based substrate;
(b3) manufacturing a second ion region to be implanted on the lower surface of the silicon-based substrate by adopting a photoetching process;
(b4) doping phosphorus into the region to be implanted by the second ions by adopting a glue-carrying ion implantation process to form an N + region in the silicon-based substrate;
(b5) annealing the whole material including the P + region and the N + region at 950-1100 ℃ to activate the impurities doped in the P + region and the N + region; the P + region, the N + region and the silicon-based substrate between the P + region and the N + region form a diode structure.
In one embodiment of the present invention, step (c) comprises:
(c1) manufacturing a first region to be etched and a second region to be etched on the silicon-based substrate by adopting a photoetching process;
(c2) etching the silicon-based substrate in the first region to be etched and the second region to be etched by adopting a deep reactive ion etching process to form the TSV hole and the isolation groove respectively;
(c3) depositing a silicon dioxide material on the inner walls of the TSV hole and the isolation trench as an insulating layer by adopting a plasma enhanced chemical vapor deposition process;
(c4) and selectively etching the oxide layer by adopting a wet etching process to enable the TSV hole and the inner wall of the isolation groove to be smooth.
In one embodiment of the present invention, step (d) comprises:
(d11) forming a first filling area on the surface of the isolation groove by adopting a photoetching process;
(d12) and filling a silicon dioxide material in the isolation trench through the first filling area by adopting a chemical vapor deposition process at the temperature of 690-710 ℃.
In one embodiment of the present invention, step (d) further comprises:
(d21) forming a second filling area on the surface of the TSV hole by adopting a photoetching process;
(d22) and filling a copper material in the TSV hole through the second filling area by adopting a physical vapor deposition process.
In one embodiment of the present invention, step (e) comprises:
(e1) depositing a silicon dioxide material on the whole material upper surface including the TSV hole, the isolation trench and the P + region by adopting a plasma enhanced chemical vapor deposition process to serve as a first passivation layer;
(e2) selectively etching the first passivation layer by adopting a dry etching process, and forming a first plug hole on the surfaces of the TSV hole and the P + region;
(e3) depositing a tungsten material in the first plug hole as a first plug by adopting a chemical vapor deposition process;
(e4) and adopting an electrochemical copper plating process to grow a copper material on the surface of the first plug to serve as a metal interconnection line so as to connect the TSV hole with the diode.
In one embodiment of the present invention, step (f) comprises:
(f1) thinning the silicon-based substrate by adopting a mechanical grinding process;
(f2) and flattening the bottom of the silicon-based substrate by adopting a chemical mechanical polishing process to expose the TSV hole, the isolation groove and the diode.
In one embodiment of the present invention, step (g) comprises:
(g1) depositing a silicon dioxide material on the lower surface of the whole material including the TSV hole, the isolation trench and the N + region by adopting a plasma enhanced chemical vapor deposition process to serve as a second passivation layer;
(g2) selectively etching the second passivation layer by adopting a dry etching process to form a second plug hole on the surfaces of the TSV hole and the N + region;
(g3) depositing a tungsten material in the second plug hole as a second plug by adopting a chemical vapor deposition process;
(g4) and growing a copper material on the surface of the second plug as a bump by adopting an electrochemical copper plating process.
In another embodiment of the present invention, there is provided a diode-based integrated circuit anti-static interposer, the interposer comprising: the device comprises a substrate, TSV holes, an isolation groove, a diode, a plug, a metal interconnection line, salient points and a passivation layer; wherein the interposer is prepared by any one of the methods described above.
Compared with the prior art, the invention has at least the following beneficial effects:
1. the preparation process of the antistatic adapter plate of the integrated circuit, provided by the invention, has the advantages of simple process steps and high feasibility;
2. according to the antistatic adapter plate for the integrated circuit, the diode is processed on the TSV adapter plate to serve as an ESD protection device, so that the antistatic capacity of the stacked and packaged chip is enhanced; in addition, the diode is surrounded by an isolation groove which is penetrated up and down, so that the leakage current and the parasitic capacitance are smaller.
Drawings
The following detailed description of embodiments of the invention will be made with reference to the accompanying drawings.
Fig. 1 is a flowchart of a method for manufacturing an antistatic interposer of an integrated circuit based on a diode according to an embodiment of the present invention;
fig. 2a to fig. 2g are schematic diagrams illustrating a method for manufacturing an antistatic interposer of an integrated circuit based on a diode according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of an integrated circuit antistatic interposer based on a diode according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.
Example one
Referring to fig. 1, fig. 1 is a flowchart of a method for manufacturing an antistatic interposer for an integrated circuit based on a diode according to an embodiment of the present invention, where the method includes:
(a) selecting a silicon-based substrate;
(b) manufacturing a diode in a first appointed area in the silicon-based substrate;
(c) respectively manufacturing a TVS hole and an isolation groove in a second designated area and a third designated area in the silicon-based substrate;
(d) filling the isolation trench and the TVS hole with a silicon dioxide material and a metal material respectively;
(e) manufacturing metal interconnection lines on the TSV holes and the upper surfaces of the diodes so that the TSV holes are connected with the diodes;
(f) removing partial material on the bottom of the silicon-based substrate to expose the TSV hole, the isolation trench and the diode on the bottom of the silicon-based substrate;
(g) and manufacturing salient points on the TSV hole and the lower surface of the diode.
Wherein the doping concentration of the silicon-based substrate is 3 multiplied by 1014～5×1017cm-3。
The step (b) may include:
(b1) manufacturing a first ion to-be-implanted area on the upper surface of the silicon-based substrate by adopting a photoetching process;
(b2) doping boron into the region to be implanted through the first ions by adopting a glue-carrying ion implantation process so as to form a P + region in the silicon-based substrate;
(b3) manufacturing a second ion region to be implanted on the lower surface of the silicon-based substrate by adopting a photoetching process;
(b4) doping phosphorus into the region to be implanted by the second ions by adopting a glue-carrying ion implantation process to form an N + region in the silicon-based substrate;
(b5) annealing the whole material including the P + region and the N + region at 950-1100 ℃ to activate the impurities doped in the P + region and the N + region; the P + region, the N + region and the silicon-based substrate between the P + region and the N + region form a diode structure.
Step (c) may include:
(c1) manufacturing a first region to be etched and a second region to be etched on the silicon-based substrate by adopting a photoetching process;
(c2) etching the silicon-based substrate in the first region to be etched and the second region to be etched by adopting a deep reactive ion etching process to form the TSV hole and the isolation groove respectively;
(c3) depositing a silicon dioxide material on the inner walls of the TSV hole and the isolation trench as an insulating layer by adopting a plasma enhanced chemical vapor deposition process;
(c4) and selectively etching the oxide layer by adopting a wet etching process to enable the TSV hole and the inner wall of the isolation groove to be smooth.
Step (d) may include:
(d11) forming a first filling area on the surface of the isolation groove by adopting a photoetching process;
(d12) and filling a silicon dioxide material in the isolation trench through the first filling area by adopting a chemical vapor deposition process at the temperature of 690-710 ℃.
Step (d) may further comprise:
(d21) forming a second filling area on the surface of the TSV hole by adopting a photoetching process;
(d22) and filling a copper material in the TSV hole through the second filling area by adopting a physical vapor deposition process.
Step (e) may include:
(e1) depositing a silicon dioxide material on the whole material upper surface including the TSV hole, the isolation trench and the P + region by adopting a plasma enhanced chemical vapor deposition process to serve as a first passivation layer;
(e2) selectively etching the first passivation layer by adopting a dry etching process, and forming a first plug hole on the surfaces of the TSV hole and the P + region;
(e3) depositing a tungsten material in the first plug hole as a first plug by adopting a chemical vapor deposition process;
(e4) and adopting an electrochemical copper plating process to grow a copper material on the surface of the first plug to serve as a metal interconnection line so as to connect the TSV hole with the diode.
Step (f) may include:
(f1) thinning the silicon-based substrate by adopting a mechanical grinding process;
(f2) and flattening the bottom of the silicon-based substrate by adopting a chemical mechanical polishing process to expose the TSV hole, the isolation groove and the diode.
Step (g) may comprise:
(g1) depositing a silicon dioxide material on the lower surface of the whole material including the TSV hole, the isolation trench and the N + region by adopting a plasma enhanced chemical vapor deposition process to serve as a second passivation layer;
(g2) selectively etching the second passivation layer by adopting a dry etching process to form a second plug hole on the surfaces of the TSV hole and the N + region;
(g3) depositing a tungsten material in the second plug hole as a second plug by adopting a chemical vapor deposition process;
(g4) and growing a copper material on the surface of the second plug as a bump by adopting an electrochemical copper plating process.
According to the preparation method of the diode-based antistatic adapter plate of the integrated circuit, the diode is processed on the TSV adapter plate to serve as the ESD protection device, so that the antistatic capacity of the stacked and packaged integrated circuit chip is enhanced; in addition, the preparation method is relatively simple and has high feasibility.
Example two
In this embodiment, an implementation of the present invention is described on the basis of the first embodiment.
Specifically, referring to fig. 2a to 2g, fig. 2a to 2g are schematic diagrams of a method for manufacturing an antistatic interposer of an integrated circuit based on a diode according to an embodiment of the present invention, the method includes the following steps:
s1, selecting the substrate 201, as shown in fig. 2 a.
Wherein the thickness of the substrate 201 is 450-550 μm, the doping type can be N type or P type, and the doping concentration is 3 × 1014～5×1017cm-3In addition, the crystal orientation of the substrate 201 may be (100) or (110) or (111), which is not limited herein.
S2, manufacturing a diode 202 in a first appointed area in the silicon-based substrate 201; as shown in fig. 2 b. Specifically, S2 may include the following steps:
s21, manufacturing a first ion implantation waiting area on the upper surface of the silicon substrate by adopting a photoetching process;
s22, doping boron into the region to be implanted through the first ions by adopting a glue ion implantation process to form a P + region 2021 in the silicon-based substrate;
s23, manufacturing a second ion implantation area on the lower surface of the silicon-based substrate by adopting a photoetching process;
s24, doping phosphorus through the second ion to-be-implanted region by using a glue ion implantation process to form an N + region 2022 in the silicon-based substrate;
s25, annealing the whole material including the P + region 2021 and the N + region 2022 at 950-1100 ℃ to activate the doped impurities in the P + region and the N + region; the P + region, the N + region and the silicon-based substrate between the P + region and the N + region form a diode structure.
S3, respectively forming a TVS hole 203 and an isolation trench 204 in the second designated region and the third designated region of the silicon-based substrate 201, as shown in fig. 2 c. Specifically, S3 may include the following steps:
s31, manufacturing a first region to be etched and a second region to be etched on the silicon-based substrate by adopting a photoetching process;
s32, etching the silicon-based substrate 201 in the first region to be etched and the second region to be etched by using a deep reactive ion etching process to form the TSV hole 203 and the isolation trench 204, respectively;
s33, depositing a silicon dioxide material on the inner walls of the TSV hole 203 and the isolation trench 204 to serve as an insulating layer by adopting a plasma enhanced chemical vapor deposition process;
s34, selectively etching the oxide layer by adopting a wet etching process to enable the TSV hole 203 and the inner wall of the isolation trench 204 to be smooth; through this step, the TSV hole 203 sidewall protrusion can be prevented from forming an electric field concentration region.
S4, filling the TVS hole 203 and the isolation trench 204 with a silicon dioxide material and a copper material, respectively; as shown in fig. 2 d. Specifically, S4 may include the following steps:
s41, forming a first filling area on the surface of the isolation trench by adopting a photoetching process;
s42, filling a silicon dioxide material in the isolation trench through the first filling area by adopting a chemical vapor deposition process at the temperature of 690-710 ℃;
s43, forming a second filling area on the surface of the TSV hole by adopting a photoetching process;
and S44, filling a copper material in the TSV hole through the second filling area by adopting a physical vapor deposition process.
S5, forming metal interconnection lines 205 on the TSV holes 203 and the upper surfaces of the diodes 202 to connect the TSV holes 203 and the diodes 202, as shown in fig. 2 e. Specifically, S5 may include the following steps:
s51, depositing a silicon dioxide material on the TSV hole 203 and the upper surface of the diode 202 as a first passivation layer 206, selectively etching the first passivation layer 206, and forming a first plug hole on the TSV hole 202 and the upper surface of the diode 202; depositing tungsten material in the first plug hole as a first plug 207;
s52, growing a copper material on the surface of the first plug 207 as a metal interconnection line by using an electrochemical copper plating process, so as to connect the TSV hole with the diode 202; meanwhile, the metal interconnection line can be used to be wound into a spiral shape, so that the metal interconnection line has the characteristic of inductance and is better used for electrostatic protection of the radio frequency integrated circuit.
S6, removing a part of the material on the bottom of the substrate 201 to expose the TSV hole 203, the isolation trench 204 and the diode 202 on the bottom of the substrate 201; as shown in fig. 2 f. Specifically, S6 may include:
s61, thinning the lower surface of the substrate 201 by adopting a mechanical grinding process;
s62, performing a planarization process on the lower surface of the substrate 201 by using a chemical mechanical polishing process to expose the TSV hole 203, the isolation trench 204 and the diode 202 at the bottom of the substrate 201. After the treatment of the step, the thickness of the substrate 201 is 300-400 μm.
S7, forming a bump 208 on the TSV hole 203 and the lower surface of the diode 202, as shown in fig. 2 g. Specifically, S7 may include:
s71, depositing a silicon dioxide material as a second passivation layer 209 on the TSV hole 203 and the lower surface of the diode 202, selectively etching the second passivation layer 209, and forming a second plug hole on the TSV hole 203 and the lower surface of the diode 202; depositing a copper material in the second plug hole as a second plug 210;
s72, depositing a copper material as a bump 208 on the TSV hole 203 and the second plug 210 on the lower surface of the diode 202.
It should be noted that the isolation trench is to isolate the diode from other structures in the interposer, so the isolation trench may be made as a closed structure (e.g., a ring structure) and penetrate through the substrate material, and the diode is located inside the closed structure.
According to the preparation method of the diode-based antistatic adapter plate of the integrated circuit, the diode is manufactured on the TSV adapter plate to serve as the ESD protection device, so that the antistatic capacity of the integrated circuit is enhanced; in addition, the isolating groove which penetrates up and down is adopted around the diode, so that the leakage current and the parasitic capacitance are smaller.
EXAMPLE III
In this embodiment, the structure of the diode-based antistatic interposer of the integrated circuit is described with emphasis on the manufacturing method described in the above embodiment.
Referring to fig. 3, fig. 3 is a schematic structural diagram of an integrated circuit antistatic interposer based on a diode according to an embodiment of the present invention. The diode-based integrated circuit antistatic adapter plate is prepared by the preparation method in the embodiment. Specifically, the interposer 300 includes: the structure comprises a substrate 301, TSV holes 302, an isolation groove 303, a diode 304, plugs 305, metal interconnection lines 306, bumps 307 and a passivation layer 308; the TSV hole 302 is filled with a copper material, and the isolation trench 303 is filled with a silicon dioxide material.
According to the diode-based antistatic adapter plate for the integrated circuit, the diode is manufactured in the adapter plate to serve as an ESD protection device, so that the antistatic capacity of the integrated circuit is enhanced; in addition, the isolation groove which penetrates up and down is arranged around the diode, so that the leakage current and the parasitic capacitance of the adapter plate can be reduced.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.
Claims (9)
1. A preparation method of an integrated circuit antistatic adapter plate based on a diode is characterized by comprising the following steps:
(a) selecting a silicon-based substrate;
(b) fabricating a diode in a first designated area of said silicon-based substrate, step (b) comprising:
(b1) manufacturing a first ion to-be-implanted area on the upper surface of the silicon-based substrate by adopting a photoetching process;
(b2) doping boron into the region to be implanted through the first ions by adopting a glue-carrying ion implantation process so as to form a P + region in the silicon-based substrate;
(b3) manufacturing a second ion region to be implanted on the lower surface of the silicon-based substrate by adopting a photoetching process;
(b4) doping phosphorus into the region to be implanted by the second ions by adopting a glue-carrying ion implantation process to form an N + region in the silicon-based substrate;
(b5) annealing the whole material including the P + region and the N + region at 950-1100 ℃ to activate the impurities doped in the P + region and the N + region; the P + region, the N + region and the silicon-based substrate between the P + region and the N + region form a diode structure;
(c) respectively manufacturing a TSV hole and an isolation trench in a second designated area and a third designated area in the silicon-based substrate, wherein the depth of the TSV hole is consistent with that of the isolation trench, and the isolation trench is positioned between the TSV hole and the diode;
(d) filling the isolation trench and the TSV hole with a silicon dioxide material and a metal material respectively;
(e) manufacturing metal interconnection lines on the TSV holes and the upper surface of the diode so as to enable the TSV holes to be connected with the diode, wherein the metal interconnection lines are wound into a spiral shape;
(f) removing partial material on the bottom of the silicon-based substrate to expose the TSV hole, the isolation trench and the diode on the bottom of the silicon-based substrate;
(g) manufacturing salient points on the TSV holes and the lower surface of the diode;
SiO is filled in the isolation groove2The periphery of the diode is SiO2The insulating layer surrounds the TSV hole, and the copper material is filled in the TSV hole.
2. The method according to claim 1, wherein the silicon-based substrate has a doping concentration of 3 x 1014～5×1017cm-3。
3. The method of claim 1, wherein step (c) comprises:
(c1) manufacturing a first region to be etched and a second region to be etched on the silicon-based substrate by adopting a photoetching process;
(c2) etching the silicon-based substrate in the first region to be etched and the second region to be etched by adopting a deep reactive ion etching process to form the TSV hole and the isolation groove respectively;
(c3) depositing a silicon dioxide material on the inner walls of the TSV hole and the isolation trench as an insulating layer by adopting a plasma enhanced chemical vapor deposition process;
(c4) and selectively etching the oxide layer by adopting a wet etching process to enable the TSV hole and the inner wall of the isolation groove to be smooth.
4. The method of claim 3, wherein step (d) comprises:
(d11) forming a first filling area on the surface of the isolation groove by adopting a photoetching process;
(d12) and filling a silicon dioxide material in the isolation trench through the first filling area by adopting a chemical vapor deposition process at the temperature of 690-710 ℃.
5. The method of claim 4, wherein step (d) further comprises:
(d21) forming a second filling area on the surface of the TSV hole by adopting a photoetching process;
(d22) and filling a copper material in the TSV hole through the second filling area by adopting a physical vapor deposition process.
6. The method of claim 5, wherein step (e) comprises:
(e1) depositing a silicon dioxide material on the whole material upper surface including the TSV hole, the isolation trench and the P + region by adopting a plasma enhanced chemical vapor deposition process to serve as a first passivation layer;
(e2) selectively etching the first passivation layer by adopting a dry etching process, and forming a first plug hole on the surfaces of the TSV hole and the P + region;
(e3) depositing a tungsten material in the first plug hole as a first plug by adopting a chemical vapor deposition process;
(e4) and adopting an electrochemical copper plating process to grow a copper material on the surface of the first plug to serve as a metal interconnection line so as to connect the TSV hole with the diode.
7. The method of claim 6, wherein step (f) comprises:
(f1) thinning the silicon-based substrate by adopting a mechanical grinding process;
(f2) and flattening the bottom of the silicon-based substrate by adopting a chemical mechanical polishing process to expose the TSV hole, the isolation groove and the diode.
8. The method of claim 7, wherein step (g) comprises:
(g1) depositing a silicon dioxide material on the lower surface of the whole material including the TSV hole, the isolation trench and the N + region by adopting a plasma enhanced chemical vapor deposition process to serve as a second passivation layer;
(g2) selectively etching the second passivation layer by adopting a dry etching process to form a second plug hole on the surfaces of the TSV hole and the N + region;
(g3) depositing a tungsten material in the second plug hole as a second plug by adopting a chemical vapor deposition process;
(g4) and growing a copper material on the surface of the second plug as a bump by adopting an electrochemical copper plating process.
9. An integrated circuit antistatic adapter plate based on a diode is characterized by comprising a silicon substrate, TSV holes, an isolation groove, the diode, plugs, metal interconnection lines, salient points and a passivation layer; wherein the interposer is prepared by the method of any one of claims 1 to 8.
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