CN206022362U - The two-way transient voltage suppresser of integrated-type low pressure that groove is drawn - Google Patents
The two-way transient voltage suppresser of integrated-type low pressure that groove is drawn Download PDFInfo
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Abstract
The two-way transient voltage suppresser of integrated-type low pressure that the utility model groove is drawn, including the first conductivity type substrate；There is the epitaxial layer of the second conduction type on substrate；There is the first conductive type epitaxial layer on the second conductive type epitaxial layer；First isolated groove enters the first conductivity type substrate, and forms first area and second area；Diode Z1 is epitaxially formed by the first conductivity type implanted region, the second conduction type diffusion region and the first kind in first area, the first conduction type extension and the second conduction type are epitaxially formed diode D1；Diode Z2 is epitaxially formed by the first conductivity type implanted region, the second conduction type diffusion region and the first kind in second area, the first conduction type extension and the second conduction type are epitaxially formed diode D2；Second draws groove, enters the second conductive type epitaxial layer, interior the second conductivity type polysilicon of raising concentration；The diode Z1 and D2 is connected by the first metal wire IO1, the second metal wire IO2 connects the diode Z2 and D1.
Description
Technical field
The utility model is related to the two-way transient voltage suppresser of integrated-type low pressure of groove extraction, is the two-way instantaneous electricity of low pressure
The structure-improved of pressure suppressor, belongs to technical field of manufacturing semiconductors.
Background technology
Transient voltage suppresser（TVS）It is widely used on the integrated, to protect IC interior not by prominent
The infringement that the overvoltage that sends out is brought.The TVS device for being applied to mobile phone, automotive electronics and security protection every profession and trade at present is not required nothing more than and is had
Little junction capacity, and the big voltage signal of difference will also can be born between FPDP or between FPDP and ground, solve this
Two traditional ways of problem are the forward diodes for concatenating a low electric capacity on transient voltage suppresser, and use multiple chips
Envelope is closed, its result causes packaging cost high, and product area is big.
With the diminution and the reduction of operating voltage of integrated circuit technology size, the operating voltage of transient voltage suppresser
Decrease.At present to have reached 3.3V even lower for typical case's shut-off voltage of a lot of transient voltage suppressers, at the same time will
Seek little leakage current.
As notification number CN 103840013A disclose a low pressure transient voltage suppresser for being provided with potential barrier Zener diode.
The low pressure transient voltage suppresser (TVS) is to be located at the horizontal JFET in the N-type epitaxy layer on N+ substrates based on one, and which is buried by one
Enter formula p-type body regions to be formed with a surface p type island region domain.Doping level between two p-type body regions is optional with distance
Select, therefore to be built junction barrier completely depleted for the JFET raceway grooves, thus increases by a potential barrier.The device is less than gesture in anode voltage
Low-leakage current is presented when building voltage, and carries out electric current conduction when anode voltage exceedes barrier voltage.The structure of the device
In also have an intrinsic open base stage vertical NPN structure.In high current, electric current flow to vertical from the JFET raceway grooves conversion
NPN transistor, therefore provided clamp down on performance.The trigger voltage of TVS is identical with the barrier voltage of JFET, can pass through adjustment
The width of raceway groove and p-type body regions, length, doping values are adjusting.
Structure involved by above-mentioned utility model patent is a kind of transient voltage suppresser of two-way NPN formulas, this knot
Structure can not take into account low-work voltage and Low dark curient.
And for example notification number CN 101826716A disclose a low pressure transient voltage suppressing for being provided with potential barrier Zener diode
Device.The low pressure transient voltage suppresser (TVS) be based on one be located at N+ substrates on N-type epitaxy layer in horizontal JFET, its by
One flush type p-type body regions are formed with a surface p type island region domain.Doping level between two p-type body regions with distance is
Selectable, therefore to be built junction barrier completely depleted for the JFET raceway grooves, thus increases by a potential barrier.This device is low in anode voltage
Low-leakage current is presented when barrier voltage, and carries out electric current conduction when anode voltage exceedes barrier voltage.The device
Also there is in structure an intrinsic open base stage vertical NPN structure.In high current, electric current is flow to from the JFET raceway grooves conversion
Vertical NPN transistor, therefore provided clamp down on performance.The trigger voltage of TVS is identical with the barrier voltage of JFET, can pass through
The width of adjustment raceway groove and p-type body regions, length, doping values are adjusting.
The low pressure transient voltage suppresser structure of this improvement, has good performance under low pressure, and its technical process is simple,
Limited by technology, but this structure is difficult to make two-way full symmetric transient voltage suppresser.
In addition, also there is the two-way TVS device of low pressure in prior art be formed in parallel by two groups of unidirectional TVS, its packaging cost
High, area is big, and the problem that mesolow TVS electric leakages are big.
Content of the invention
Technical problem to be solved in the utility model is：There is provided a kind of integrated-type low pressure of groove extraction two-way instantaneous electricity
Pressure suppressor.The difficult problem that not only cost reduces and overcomes mesolow TVS electric leakages big.
The utility model the problems referred to above are solved by following proposal：A kind of two-way instantaneous electricity of integrated-type low pressure that groove is drawn
Pressure suppressor, the first conductivity type substrate, the conductive-type substrate epitaxial layer characterized in that, including：
One the first conductivity type substrate；
The epitaxial layer of one the second conduction type being formed on substrate；
One the first conductive type epitaxial layer being formed on the second conductive type epitaxial layer；
First isolated groove, the groove enter first conductivity type substrate, and shape from the first conductive type epitaxial layer
Into first area and second area；
The first conductivity type implanted region 131, the second conduction type diffusion region 141 and first is formed in the first area
The extension 121 of type forms diode Z1, the first conduction type extension 121 and the second conduction type extension 111 in first area
Form diode D1；
The first conductivity type implanted region, the second conduction type diffusion region and the first kind is formed in the second area
Diode Z2 is epitaxially formed, the first conduction type extension and the second conduction type are epitaxially formed diode D2 in second area；
Second draws filling the second conductivity type polysilicon of high concentration in groove, groove, and enters outside the second conduction type
Prolong layer, but do not enter the first conductivity type substrate；
Form the first metal wire IO1 and the second metal wire IO2, the first metal wire IO1 connect the diode Z1 and
D2, the second metal wire IO2 connect the diode Z2 and D1.
Transient voltage suppresser provided by the utility model has two-way full symmetric process structure, can be applicable to
The operating voltage of 1.8V-3.3V, and with less chip area and very low leakage current；PN junction is realized using deep groove structure
Isolation, and insert insulating materials silica in the trench, reduce the electric leakage of PN junction side, while being conducive to reducing chip
Area；The extension of the second conduction type is drawn to form surface electrode using deep trouth, and fill the polycrystalline of high concentration auto-dope
Silicon, compares traditional lead-out mode injected with impurity, and this structure does not need long-time high annealing, occupies less chip
Area, with less contact resistance, process stabilizing, reproducible.
Diode Z1 and diode Z2 in the utility model has identical process structure, is by the second conduction type
The PN junction being epitaxially formed of injection region, the injection region of the first conduction type and the first conduction type is constituted, the concentration ladder for being formed
Degree has negative resistance charactertistic, punch through voltage size to be adjusted by concentration after making knot break-through, and with relatively low leakage current.
Diode D1 and diode D2 in the utility model has identical process structure, by the outer of the first conduction type
Prolong the extension composition with the second conduction type, the extension concentration of wherein the first conduction type is low, and breakdown voltage is big, therefore junction capacity
Little.
In the utility model, Z1 is connected with D1, and Z2 is connected with D2, as D1 and D2 is formed by the PN junction of low concentration, its
Breakdown voltage is larger, and junction capacity is little, reduces branch road electric capacity after series connection, and therefore the structure is than general bi-directional voltage suppressor
Electric capacity is little.
On such scheme base, first conduction type be p-type, second conduction type be N-type, described first
Conductivity type substrate is P type substrate, has N-type epitaxy layer in P type substrate, has p-type epitaxial layer in N-type epitaxy layer, by first
Groove isolation construction, enters P type substrate from p-type epitaxial layer, and forms first area and second area；
P-type injection region, the second conductive-type N-type diffusion region is formed in the first area as N-type launch site, outside p-type
Prolong layer and form diode Z1, p-type epitaxial layer and the second conductive-type N-type are epitaxially formed diode D1 in first area；
P-type injection region, the second conductive-type N-type diffusion region is formed in the second area as N-type launch site, outside p-type
Prolong layer and form diode, p-type epitaxial layer and the second conductive-type N-type are epitaxially formed diode D2 in first area；
Filling high concentration the second conductive-type N-type polycrystalline silicon in second groove deriving structure, groove, and enter the second conductive-type
N-type epitaxy layer, but do not enter the first conductive-type P type substrate；
The metal for drawing groove top of the metal connection second area on the N-type launch site top of first area, forms the
One electrode IO1, the metal on the N-type launch site top of the metal connection second area for drawing groove top of first area, forms
Second electrode IO2.
Preferably, the resistance substrate rate of first conduction type is 0.01 Ω .cm-0.1 Ω .cm.
Preferably, the epilayer resistance rate of second conduction type is 0.01 Ω .cm-0.04 Ω .cm, and thickness is 3 m-
10 m, and form first area and second area.
On the basis of such scheme, it is preferred that the first conductive type epitaxial layer resistivity is 50 Ω .cm-150 Ω
.cm, thickness is 4 m-8 m.
First isolated groove enters described the through the first conductive type epitaxial layer and the second conductive type epitaxial layer
One conductivity type substrate, and form first area and second area in the substrate, the isolated groove width is 0.8 m-2 m,
Its depth be 10 m-21 m, filled media silica in described isolated groove.
Preferably, it is doped using ion implanting mode in described first area and second area, forms first and lead
The p-type base of electric type, its implantation dosage are 1e14/cm2-1e15/cm2.
It is doped using diffusion way in described first area and second area, forms the second conductive-type of high concentration
The N-type launch site of type.
Preferably, described second groove is drawn through the first conductive type epitaxial layer, enter outside second conduction type
Prolong layer, but do not penetrate the second conductive type epitaxial layer, described groove width is 0.8 m-2 m, its depth is 5 m-15 m, and
High concentration auto-dope polysilicon is filled in described groove.
The manufacturer of the two-way transient voltage suppresser of integrated-type low pressure that a kind of above-mentioned groove of the utility model is drawn
Method, in the steps below：
1）, the second conductive type epitaxial layer is formed in the first conductivity type substrate, substrate impurity is boron ion, electric
Resistance rate is 0.01 Ω .cm-0.1 Ω .cm, and the second conduction type epi dopant impurity is arsenic ion or phosphonium ion, and resistivity is
0.01 Ω .cm-0.04 Ω .cm, 3 m-10 m of epitaxial thickness；First conductive-type is grown on the second conductive type epitaxial layer thereafter
Type epitaxial layer, its impurity are boron ion, and resistivity is 50 Ω .cm-150 Ω .cm, and thickness is 4 m-8 m；
2）, the growth layer of silicon dioxide of the silicon chip surface after secondary epitaxy, using ion implantation technology, carries out first
The injection doping of conduction type, forms the base of Z1 and Z2, and its implanted dopant is boron ion, and implantation dosage is 1e14/cm2-
1e15/cm2；
3）, the silica of silicon chip surface is shelled entirely, using diffusion technique, the diffusing, doping of the second conduction type is carried out,
The launch site of Z1 and Z2 is formed, the resistivity for spreading source is 4 Ω .cm-10 Ω .cm；
4）, the first isolated groove is formed on epitaxial layer using photoetching and etching technics, groove width is 0.8 m-2 m,
Depth is 10 m-21 m, and the groove is through the second conductive type epitaxial layer and the first conductive type epitaxial layer entrance substrate, use
Substrate epitaxial material is divided into the firstth area by chemical vapor deposition method filled media silica in described isolated groove
Domain and second area；
5）, the second extraction groove structure is formed on epitaxial material using photoetching and etching technics, groove width is 0.8
M-2 m, its depth are 5 m-15 m, and the groove is through the first conductive type epitaxial layer, entrance the second conduction type extension
Layer, but the second conductive type epitaxial layer is not penetrated, high concentration is filled in described groove certainly using chemical vapor deposition method
DOPOS doped polycrystalline silicon, and carry out high annealing；
6）, using etching technics etches polycrystalline and hole, extraction groove and second is formed using chemical vapor deposition method and is led
The metal connection of electric type launch site, on the extraction groove of the metal connection second area on the N-type launch site top of first area
The metal in portion, forms first electrode IO1, and the metal for drawing groove top of first area connects the N-type launch site of second area
The metal on top, forms second electrode IO2.
Of the present utility model it is advantageous in that：The utility model is a kind of full symmetric to can be applicable to low pressure with two-way
Transient voltage suppresser, by realizing the isolation of PN junction using deep groove structure, reduce the electric leakage of PN junction side, while favorably
In the area for reducing chip；The extension of the second conduction type is drawn to form surface electrode using deep trouth, than traditional extraction side
The formula high annealing time is short, occupies less chip area, with less contact resistance, process stabilizing, reproducible；This reality
With the diode Z1 and diode Z2 in new be all by the injection region of the second conduction type, the injection region of the first conduction type and
The PN junction being epitaxially formed of the first conduction type is constituted, and the concentration gradient for being formed has negative resistance charactertistic, break-through electricity after making knot break-through
Pressure size is adjusted by concentration, and with relatively low leakage current；Diode D1 and D2 all by the first conduction type extension and
The extension composition of the second conduction type, the extension concentration of wherein the first conduction type are low, and breakdown voltage is big, and therefore junction capacity is little.
Description of the drawings
Fig. 1 is the circuit theory signal that a kind of groove of the utility model draws the two-way transient voltage suppresser of integrated-type low pressure
Figure；
Fig. 2 is the cross-section structure signal that a kind of groove of the utility model draws the two-way transient voltage suppresser of integrated-type low pressure
Figure；
Fig. 3 is the VA characteristic curve schematic diagram of the transient voltage suppresser according to the utility model process implementing example；
Fig. 4 to Fig. 8 is the manufacturer that a kind of groove of the utility model draws the two-way transient voltage suppresser of integrated-type low pressure
The process flow steps schematic diagram of method.
Specific embodiment
With reference to Fig. 1 and Fig. 2, a kind of two-way transient voltage suppresser of the integrated-type low pressure that groove is drawn：Including：First is conductive
Type（P-type）Substrate 101, the second conductive-type N-type epitaxy layer 111 are numbered the first conductive-type p-type epitaxial layer 121, and first is conductive
Class p-type injection region label 131, the second conductive-type N-type diffusion region 141, the groove structure 151 of extraction, wherein filling auto-dope are high
The polysilicon of concentration, isolation trench structure 161, wherein filled media silica, metal connecting layer 171, dielectric layer 172, its
In：
One first conductivity type substrate is P type substrate 101, has N-type epitaxy layer 111, in N-type epitaxy layer in P type substrate
There is p-type epitaxial layer 121 on 111, P type substrate is stretched into by the first isolated groove from p-type epitaxial layer 121, N-type epitaxy layer 111, make P
The epitaxial material of type substrate 101 forms first area and second area；
P-type injection region 131, the second conductive-type N-type diffusion region 141 is formed in the first area as N-type launch site, with
P-type epitaxial layer 121 forms diode Z1, and in first area, p-type epitaxial layer 121 and the second conductive-type N-type extension 111 form two poles
Pipe D1；
P-type injection region 131, the second conductive-type N-type diffusion region 141 is formed in the second area as N-type launch site, with
P-type epitaxial layer 121 forms diode Z2, and in first area, p-type epitaxial layer 121 and the second conductive-type N-type extension 111 form two poles
Pipe D2；
Second draws groove, is located in first area and second area, parallel with the first isolated groove, and in groove, filling is high
Concentration the second conductive-type N-type polycrystalline silicon, stretches into N-type epitaxy layer 111 from p-type epitaxial layer 121, but does not enter the first conductive-type p-type
Substrate；
The metal for drawing groove top of the metal connection second area on the N-type launch site top of first area, forms the
One electrode IO1, the metal on the N-type launch site top of the metal connection second area for drawing groove top of first area, forms
Second electrode IO2.
As shown in figure 1, in the utility model formed Z1, Z2 and D1, D2 annexation constitute a kind of full symmetric
Can be applicable to the transient voltage suppresser of low pressure.
The preparation method of the two-way transient voltage suppresser of integrated-type low pressure that above-mentioned groove is drawn refer to Fig. 4 to Fig. 8, walk
Suddenly it is：
1）, such as Fig. 4, the second conduction type N-type epitaxy layer 111 is formed in the first conduction type P type substrate 1, substrate is mixed
Impurity be boron ion, resistivity be 0.01 Ω .cm-0.1 Ω .cm, the second conduction type epi dopant impurity be arsenic ion or
Person's phosphonium ion, resistivity are 0.01 Ω .cm-0.04 Ω .cm, 3 m-10 m of epitaxial thickness, thereafter, in the second conduction type N-type
The first conduction type p-type epitaxial layer 121 is grown on epitaxial layer 111, and its impurity is boron ion, and resistivity is 50 Ω .cm-
150 Ω .cm, thickness are 4 m-8 m.
2）, with reference to Fig. 5, the silicon chip surface growth layer of silicon dioxide after secondary epitaxy, using ion implantation technology, enter
The injection doping of the first conduction type of row, forms p-type injection region 131 as the base of Z1 and Z2, and its implanted dopant is boron ion,
Implantation dosage is 1e14/cm2-1e15/cm2.
3）, such as Fig. 6, the silica of silicon chip surface is shelled entirely, using diffusion technique, the diffusion of the second conduction type is carried out
Doping, forms the second conductive-type N-type diffusion region 141 as the launch site of Z1 and Z2, and the resistivity for spreading source is 4 Ω .cm-10
Ω.cm.
4）, with reference to Fig. 7, the first isolated groove 161 is formed on epitaxial layer using photoetching and etching technics, groove width is
0.8 m-2 m, depth are 10 m-21 m, and the groove is through the second conductive type epitaxial layer 121 and the first conductive type epitaxial layer
111 enter P type substrates 101, using chemical vapor deposition method in described isolated groove 161 filled media silica,
Shown substrate epitaxial material is divided into first area and second area.
5）, with reference to Fig. 8, the second extraction groove 151 is formed on epitaxial layer using photoetching and etching technics, ditch groove width is drawn
Spend for 0.8 m-2 m, its depth is 5 m-15 m, the groove enters described second through the first conduction type p-type epitaxial layer 121
Conduction type N-type epitaxy layer 111, but the N-type epitaxy layer 111 is not penetrated, using chemical vapor deposition method in described groove
Middle filling high concentration auto-dope polysilicon, and carry out high annealing.
6）, using etching technics etches polycrystalline and hole, formed using chemical vapor deposition method and draw groove 151 and second
The metal 171 of conduction type N-type launch site connects, wherein, the metal connection second area on the N-type launch site top of first area
The metal for drawing groove top, form first electrode IO1, the metal connection second area for drawing groove top of first area
N-type launch site top metal, formed second electrode IO2, eventually form the utility model product as shown in Figure 2.
Transient voltage suppresser designed by the utility model is related to two kinds of groove structures, and both groove widths can be with
Unanimously, but depth must be different, the medium that is filled also must be different：The isolated groove for being formed, penetrates the first conduction type
（P-type）Epitaxial layer and the second conduction type（N-type）Epitaxial layer, and enter the first conduction type（P-type）Substrate zone, fill out inside which
Filling medium silica, has good buffer action, can reduce the leakage current of device, and compare PN junction isolation reducing chip
Size；The extraction groove for being formed, penetrates the first conduction type（P-type）Epitaxial layer, but do not penetrate the second conduction type（N-type）Outward
Prolong layer, the polycrystalline of its internal filling high concentration, effect is by the second conduction type（N-type）Epitaxial layer is drawn out to surface, so that with
One end of one transient voltage suppresser is connected, so as to achieve the transient voltage suppresser of bi-directional symmetrical on single.
Transient voltage suppresser designed by the utility model, has used the principle of enhancement mode break-over diode, by adjusting
Whole first conduction type（P-type）Injection region and the second conduction type（N-type）The concentration in diffusing, doping area and junction depth, obtain 3.3V very
To the breakdown voltage of 1.8V, the ESD protection of low-voltage circuit is may apply to, while punch breakdown device has puncturing than avalanche-type
The less leakage current of type device.
Transient voltage suppresser designed by the utility model, with reference to Fig. 1, Z1 is connected with D1, and Z2 is connected with D2, due to D1
It is to be formed by the PN junction of low concentration with D2, its breakdown voltage is larger, and junction capacity is little, after series connection, reduces branch road electric capacity, therefore should
Structure is less than the electric capacity of general bi-directional voltage suppressor.
Claims (8)
1. a kind of two-way transient voltage suppresser of groove is drawn integrated-type low pressure, the first conductivity type substrate, conductive-type lining
The epitaxial layer at bottom, it is characterised in that include：
One the first conductivity type substrate；
The epitaxial layer of one the second conduction type being formed on substrate；
One the first conductive type epitaxial layer being formed on the second conductive type epitaxial layer；
First isolated groove, the groove enter first conductivity type substrate from the first conductive type epitaxial layer, and form the
One region and second area；
The first conductivity type implanted region (131), the second conduction type diffusion region (141) and first is formed in the first area
The extension (121) of type forms diode Z1, the first conduction type extension (121) and the second conduction type extension in first area
(111) diode D1 is formed；
The extension of the first conductivity type implanted region, the second conduction type diffusion region and the first kind is formed in the second area
Diode Z2 is formed, the first conduction type extension and the second conduction type are epitaxially formed diode D2 in second area;
Second draws filling the second conductivity type polysilicon of high concentration in groove, groove, and enters the second conductive type epitaxial layer,
But do not enter the first conductivity type substrate；
The first metal wire IO1 and the second metal wire IO2 is formed, the first metal wire IO1 connects the diode Z1 and D2, institute
State the second metal wire IO2 and connect the diode Z2 and D1.
2. the two-way transient voltage suppresser of a kind of groove according to claim 1 is drawn integrated-type low pressure, its feature exist
In first conduction type is p-type, and second conduction type is N-type, and the first described conductivity type substrate is served as a contrast for p-type
Bottom (101), has N-type epitaxy layer (111) in P type substrate, has p-type epitaxial layer (121), by first in N-type epitaxy layer (111)
Groove isolation construction, enters P type substrate from p-type epitaxial layer (121), and forms first area and second area；
P-type injection region (131), the second conductive-type N-type diffusion region (141) is formed in the first area as N-type launch site, with
P-type epitaxial layer (121) forms diode Z1, p-type epitaxial layer (121) and the second conductive-type N-type extension (111) shape in first area
Into diode D1；
P-type injection region (131), the second conductive-type N-type diffusion region (141) is formed in the second area as N-type launch site, with
P-type epitaxial layer (121) forms diode Z2, p-type epitaxial layer (121) and the second conductive-type N-type extension (111) shape in first area
Into diode D2；
Filling high concentration the second conductive-type N-type polycrystalline silicon in second groove deriving structure, groove, and enter the second conductive-type N-type
Epitaxial layer, but do not enter the first conductive-type P type substrate；
The metal for drawing groove top of the metal connection second area on the N-type launch site top of first area, forms the first electricity
Pole IO1, the metal on the N-type launch site top of the metal connection second area for drawing groove top of first area, forms second
Electrode IO2.
3. the two-way transient voltage suppresser of a kind of groove according to claim 1 and 2 is drawn integrated-type low pressure, its feature
It is, the resistance substrate rate of first conduction type is 0.01 Ω .cm-0.1 Ω .cm.
4. the two-way transient voltage suppresser of a kind of groove according to claim 1 and 2 is drawn integrated-type low pressure, which is special
Levy and be, the epilayer resistance rate of second conduction type is 0.01 Ω .cm-0.04 Ω .cm, and thickness is 3 m-10 m.
5. the two-way transient voltage suppresser of a kind of groove according to claim 1 and 2 is drawn integrated-type low pressure, which is special
Levy and be, the first conductive type epitaxial layer resistivity is 50 Ω .cm-150 Ω .cm, and thickness is 4 m-8 m.
6. the two-way transient voltage suppresser of a kind of groove according to claim 1 and 2 is drawn integrated-type low pressure, which is special
Levy and be, it is conductive that the isolated groove enters described first through the first conductive type epitaxial layer and the second conductive type epitaxial layer
Type substrates, and form first area and second area in the substrate, the isolated groove width is 0.8 m-2 m, its depth
For 10 m-21 m, filled media silica in described isolated groove.
7. the two-way transient voltage suppresser of a kind of groove according to claim 6 is drawn integrated-type low pressure, its feature
It is, is doped using diffusion way in described first area and second area, forms the second conduction type of high concentration
N-type launch site.
8. the two-way transient voltage suppresser of a kind of groove according to claim 1 and 2 is drawn integrated-type low pressure, which is special
Levy and be, described second draws groove through the first conductive type epitaxial layer, enter second conductive type epitaxial layer, but not
The second conductive type epitaxial layer is penetrated, described groove width is 0.8 m-2 m, and its depth is 5 m-15 m, in described ditch
High concentration auto-dope polysilicon is filled in groove.
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| CN106129058A (en) * | 2016-08-27 | 2016-11-16 | 上海长园维安微电子有限公司 | Groove draws the two-way transient voltage suppresser of integrated-type low pressure and manufacture method thereof |
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| CN108054164A (en) * | 2017-12-12 | 2018-05-18 | 深圳迈辽技术转移中心有限公司 | Transient Voltage Suppressor and preparation method thereof |
| CN108054134A (en) * | 2017-12-15 | 2018-05-18 | 西安科锐盛创新科技有限公司 | TSV pinboards for system in package and preparation method thereof |
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2016
- 2016-08-27 CN CN201620950136.3U patent/CN206022362U/en not_active Withdrawn - After Issue
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| CN108109996B (en) * | 2017-12-15 | 2021-06-22 | 西安科锐盛创新科技有限公司 | Diode-based antistatic adapter plate for integrated circuit and preparation method thereof |
| CN108054134B (en) * | 2017-12-15 | 2021-07-20 | 西安科锐盛创新科技有限公司 | TSV adapter plate for system-in-package and preparation method thereof |
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