CN105789311B - Horizontal proliferation field effect transistor and its manufacturing method - Google Patents
Horizontal proliferation field effect transistor and its manufacturing method Download PDFInfo
- Publication number
- CN105789311B CN105789311B CN201610148112.0A CN201610148112A CN105789311B CN 105789311 B CN105789311 B CN 105789311B CN 201610148112 A CN201610148112 A CN 201610148112A CN 105789311 B CN105789311 B CN 105789311B
- Authority
- CN
- China
- Prior art keywords
- region
- buried layer
- channel region
- channel
- drift region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 230000005669 field effect Effects 0.000 title claims abstract description 60
- 230000035755 proliferation Effects 0.000 title claims abstract description 57
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 23
- 230000000694 effects Effects 0.000 claims abstract description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 64
- 229920005591 polysilicon Polymers 0.000 claims description 64
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 42
- 229910052760 oxygen Inorganic materials 0.000 claims description 42
- 239000001301 oxygen Substances 0.000 claims description 42
- 239000000758 substrate Substances 0.000 claims description 36
- 239000004065 semiconductor Substances 0.000 claims description 33
- 238000002347 injection Methods 0.000 claims description 14
- 239000007924 injection Substances 0.000 claims description 14
- 238000001259 photo etching Methods 0.000 claims description 14
- 230000005516 deep trap Effects 0.000 claims description 9
- 238000000034 method Methods 0.000 claims description 9
- 239000007943 implant Substances 0.000 claims description 6
- 238000000407 epitaxy Methods 0.000 claims description 4
- 238000005468 ion implantation Methods 0.000 claims description 4
- 238000002955 isolation Methods 0.000 claims description 3
- 239000000203 mixture Substances 0.000 claims description 3
- 230000005611 electricity Effects 0.000 claims description 2
- 238000000605 extraction Methods 0.000 claims description 2
- 238000009792 diffusion process Methods 0.000 claims 2
- 230000015556 catabolic process Effects 0.000 abstract description 13
- 239000010410 layer Substances 0.000 description 145
- 238000010586 diagram Methods 0.000 description 12
- 239000002184 metal Substances 0.000 description 9
- 239000011229 interlayer Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 102100035767 Adrenocortical dysplasia protein homolog Human genes 0.000 description 2
- 101100433963 Homo sapiens ACD gene Proteins 0.000 description 2
- 101100204059 Caenorhabditis elegans trap-2 gene Proteins 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/404—Multiple field plate structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Composite Materials (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a kind of horizontal proliferation field effect transistors, comprising: the buried layer of the second conduction type doping is formed in the drift region of the first conduction type doping, buried layer is divided into multiple buried layer sections with various concentration and different depth；Each two neighboring buried layer section mutual dislocation in the longitudinal direction, reduces the JFET effect between channel region and drift region, the current lead-through region of drift region when improving break-over of device；It is greater than the doping concentration of other buried layer sections near the doping concentration of the buried layer section of channel region, and the doping concentration of the buried layer section near channel region enables channel region side attachments drift region to be fully depleted in the initial stage of drain terminal voltage.The invention also discloses a kind of manufacturing methods of horizontal proliferation field effect transistor.The present invention can prevent low-voltage breakdown, improve breakdown voltage, can increase the conducting region of leakage current, reduce the conducting resistance of device.
Description
Technical field
The present invention relates to semiconductor integrated circuit manufacturing fields, more particularly to a kind of horizontal proliferation field effect transistor；
The invention further relates to a kind of manufacturing methods of horizontal proliferation field effect transistor.
Background technique
Super-pressure horizontal proliferation field effect transistor (LDMOS) is inserted into and drift region conduction type phase usually in drift region
Anti- buried layer, buried layer can help drift region to exhaust, and can properly increase drift region concentration in this way, it is also ensured that super-pressure
The breakdown voltage of LDMOS.
As shown in Figure 1, being the structural schematic diagram of existing horizontal proliferation field effect transistor；It is existing by taking N-type LDMOS as an example
LDMOS includes:
Drift region 102 is made of the deep N-well being formed in P-type semiconductor substrate such as silicon substrate 101.
It is formed with oxygen 103 on the surface of deep N-well 102, field oxygen 103 can be shallow trench field oxygen (STI) or local field oxygen
(LOCOS)。
Channel region 104, p-well forms in the deep N-well 102 by being formed in the semiconductor substrate 101.
It is formed in the polysilicon gate 106 of 101 top of semiconductor substrate, the polysilicon gate 106 and the semiconductor
The isolation of 101 surface of substrate has gate dielectric layer, and horizontally the polysilicon gate 106 extends to institute above the channel region 104
103 top of field oxygen for stating drift region 102, is used to form ditch by 104 surface of the channel region that the polysilicon gate 106 covers
Road；The first side of the polysilicon gate 106 is located at 104 top of channel region, second side is located on the drift region 102
Side.
N+ district's groups at source region 107 and drain region 108, the source region 108 be formed in the channel region 104 and and it is described more
The first side autoregistration of crystal silicon grid 106, the drain region 108 are formed in the drift region 102.
P+ district's groups at channel draw-out area 109, the channel draw-out area 109 is formed in the channel region 104 and is used for
The channel region 104 is drawn, the channel draw-out area 109 and the laterally contact of the source region 107.
Polysilicon field plate 106a is formed on the surface of the field oxygen 103 of 108 side of drain region.Drain region 108 and polysilicon field plate
106a passes through contact hole 111 and is connected to the drain electrode formed by front metal layer 112；Front metal layer 112 be also formed with grid,
Source electrode and underlayer electrode.Grid is contacted by contact hole 111 and polysilicon gate 106；Source electrode passes through contact hole 111 and source region 107
It is connected with channel draw-out area 109；Substrate extraction electrode is connected by contact hole 111 and the area P+ 110, and the area P+ 110 is formed in deep N
The surface of semiconductor substrate 101 outside trap 102.
The buried layer (PTOP) 105 of p-type doping is formed in drift region 102, buried layer 105 can help drift region 102 to consume
To the greatest extent, 105 concentration of drift region can be properly increased in this way, it is also ensured that the breakdown voltage of super-pressure LDMOS.
In existing structure shown in FIG. 1, due to the JFET effect of drift region 102 and the formation of channel region 104, LDMOS conducting
When, drain terminal electric current is difficult to reach source by the drift region 102 below of buried layer 105, and most of leakage currents are all walked above buried layer 105
Drift region, that is, Fig. 1 in region shown in dotted line frame 114 drift region, this reduces current channels, actually inhibit electricity
The raising of stream.
The buried layer 105 of existing drift region generallys use single high energy ion injection and completes the production, the transverse direction of buried layer 105
Impurity Distribution is uniform.Namely it is simultaneously formed positioned at the buried layer 105 of 104 bottom of channel region and the buried layer 105 in other regions
And doping concentration is identical, is be easy to cause in this way in drain terminal i.e. drain electrode end alive initial stage, channel region 104 and buried layer 105
Between drift region 102 be that the drift region 102 in region shown in dotted line frame 103 is not easy to be completely depleted, so that in drain terminal plus
The initial stage of voltage is easy for that the region is made to generate breakdown, and breakdown is as shown in label 103a, so existing structure is easy to form
Low-voltage breakdown, namely the initial stage more much lower than operating voltage as operating voltage ten/hit below
It wears.
It as shown in Figure 2 A, is the ionization by collision analogous diagram of existing device shown in Fig. 1；Interface corresponding to label 201 is half
Interface between conductor substrate 101 and deep N-well 102, ionization by collision maximum value appear in regional location corresponding to virtual coil 202,
Position consistency corresponding to dotted line frame 103 in this and Fig. 1.
It as shown in Figure 2 B, is the depletion region analogous diagram of existing device shown in Fig. 1；As can be seen that area corresponding to virtual coil 203
Drift region in domain is not fully depleted.
It as shown in Figure 3A, is the current density analogous diagram of existing device shown in Fig. 1；Electric current is concentrated mainly on buried layer 105
In the drift region of side in i.e. Fig. 3 in region shown in dotted line money 204, region corresponding to the dotted line frame 114 in this region and Fig. 1
Unanimously.It as shown in Figure 3B, is in Fig. 3 A along the current density plot of the lengthwise position of AA line；Electric current corresponding to dotted line frame 106
Density is maximum, which is exactly the depth bounds for being located at region corresponding to the dotted line frame 204 of Fig. 3 A.
Summary of the invention
Technical problem to be solved by the invention is to provide a kind of horizontal proliferation field effect transistors, can prevent low-voltage from hitting
It wears, improve breakdown voltage, can increase the conducting region of leakage current, reduce the conducting resistance of device.For this purpose, the present invention also provides one
The manufacturing method of kind horizontal proliferation field effect transistor.
In order to solve the above technical problems, horizontal proliferation field effect transistor provided by the invention includes:
The drift region of first conduction type doping, is formed in the second conductive type semiconductor substrate.
The channel region of second conduction type doping, is formed in the semiconductor substrate；The channel region and the drift
The contact or separated by a distance of area side.
Be formed with the buried layer of the second conduction type doping in the drift region, the buried layer be divided into various concentration and
Multiple buried layer sections of different depth.
The depth difference of each two neighboring buried layer section makes the channel region and described to mutual dislocation in the longitudinal direction
JFET effect between drift region reduces, the current lead-through region of drift region when improving break-over of device.
It is greater than the doping concentration of other buried layer sections of the buried layer near the doping concentration of the buried layer section of the channel region,
And the buried layer section that the doping concentration of the buried layer section near the channel region keeps the channel region side adjacent with the side
Between the drift region can be fully depleted in the initial stage of drain terminal voltage.
A further improvement is that the drift region is made of deep trap, each buried layer section is realized by ion implanting, is passed through
The depth for adjusting each buried layer section of energy adjustment of ion implanting, the dosage by adjusting ion implanting adjust each buried layer
The doping concentration of section.
A further improvement is that the drift region is made of epitaxial layer, the epitaxial layer of the drift region passes through multiple extension
Growth is formed, and each buried layer section carries out ion implanting in epitaxial surface after epitaxial growth corresponding with its depth and formed,
Dosage by adjusting ion implanting adjusts the doping concentration of each buried layer section.
A further improvement is that each two neighboring buried layer section buried structure that mutual dislocation forms in the longitudinal direction
Making drift region when break-over of device within the scope of entire depth is all current lead-through region.
A further improvement is that the doping concentration of other buried layer sections except the buried layer section of the channel region is identical
Or it is not identical.
A further improvement is that horizontal proliferation field effect transistor is N-type device, the first conduction type is N-type, and second leads
Electric type is p-type.
A further improvement is that horizontal proliferation field effect transistor is P-type device, the first conduction type is p-type, and second leads
Electric type is N-type.
A further improvement is that horizontal proliferation field effect transistor further include:
Be formed in the polysilicon gate of the semiconductor substrate, the polysilicon gate and the semiconductor substrate surface every
From there is gate dielectric layer, horizontally the polysilicon gate is extended to above the channel region above the drift region, described
The channel region surface of polysilicon gate covering is used to form channel；The first side of the polysilicon gate is located at the channel region
Top, second side are located above the drift region.
The source region of first conduction type heavy doping and drain region, the source region is formed in the channel region and and the polycrystalline
The first side autoregistration of Si-gate, the drain region are formed in the drift region.
A further improvement is that the horizontal proliferation field effect transistor further include: the ditch of the second conduction type heavy doping
Road draw-out area, the channel draw-out area are formed in the channel region and for drawing the channel region, and the channel is drawn
Area and the source region laterally contact.
A further improvement is that the horizontal proliferation field effect transistor further include: field oxygen is located at the channel region and institute
It states above the drift region between drain region, second side of the field oxygen and the drain region laterally contact, and the first of the field oxygen
Side and the channel region are at a distance；The polysilicon gate extends to above the field oxygen.
In order to solve the above technical problems, the manufacturing method of horizontal proliferation field effect transistor provided by the invention includes as follows
Step:
Step 1: forming the drift region of the first conduction type doping in the second conductive type semiconductor substrate；The drift
Area is moved to be formed using multiple epitaxy technique.
Step 2: forming the buried layer of the second conduction type doping in the drift region, the buried layer, which is divided into, has difference
Multiple buried layer sections of concentration and different depth；Each buried layer section is after epitaxial growth corresponding with its depth in epitaxial surface
It carries out adding ion implanting to be formed using photoetching, the dosage by adjusting ion implanting adjusts the doping concentration of each buried layer section.
The depth difference of each two neighboring buried layer section makes the channel region and described to mutual dislocation in the longitudinal direction
JFET effect between drift region reduces, the current lead-through region of drift region when improving break-over of device.
It is greater than the doping concentration of other buried layer sections of the buried layer near the doping concentration of the buried layer section of channel region, and most
Doping concentration close to the buried layer section of the channel region makes between the adjacent buried layer section in the channel region side and the side
The drift region can be fully depleted in the initial stage of drain terminal voltage.
Step 3: photoetching opens channel region injection region and carries out channel region injection forms second in the semiconductor substrate
The channel region of conduction type doping, the channel region and drift region side contact or separated by a distance.
A further improvement is that each two neighboring buried layer section buried structure that mutual dislocation forms in the longitudinal direction
Making drift region when break-over of device within the scope of entire depth is all current lead-through region.
A further improvement is that the doping concentration of other buried layer sections except the buried layer section of the channel region is identical
Or it is not identical.
A further improvement is that further comprising the steps of:
Step 4: forming field oxygen above the drift region.
Step 5: formation gate dielectric layer and polysilicon gate, the polysilicon gate are horizontally extended to from the channel region
Above the drift region, the channel region surface covered by the polysilicon gate is used to form channel, the polysilicon gate
First side is located above the channel region, second side is located above the field oxygen at the top of the drift region.
Step 6: the source and drain for carrying out the first conduction type heavy doping is injected to form source region and drain region, the source region is formed in
First side autoregistration in the channel region and with the polysilicon gate, the drain region is formed in the drift region, described
Second side of field oxygen and the drain region laterally contact.
Step 7: carrying out the second conduction type heavily-doped implant forms channel draw-out area, the channel draw-out area is formed in
In the channel region and for drawing the channel region, the channel draw-out area and the source region are laterally contacted.
In order to solve the above technical problems, the manufacturing method of horizontal proliferation field effect transistor provided by the invention includes as follows
Step:
Step 1: forming the drift region of the first conduction type doping in the second conductive type semiconductor substrate；The drift
Area is moved to be formed using deep trap technique.
Step 2: adding ion implantation technology to form burying for the second conduction type doping in the drift region using photoetching
Layer, the buried layer are divided into multiple buried layer sections with various concentration and different depth.
The depth difference of each two neighboring buried layer section makes the channel region and described to mutual dislocation in the longitudinal direction
JFET effect between drift region reduces, the current lead-through region of drift region when improving break-over of device.
It is greater than the doping concentration of other buried layer sections of the buried layer near the doping concentration of the buried layer section of the channel region,
And the buried layer section that the doping concentration of the buried layer section near the channel region keeps the channel region side adjacent with the side
Between the drift region can be fully depleted in the initial stage of drain terminal voltage.
By adjusting the depth of each buried layer section of energy adjustment of ion implanting, by the dosage tune for adjusting ion implanting
Save the doping concentration of each buried layer section.
Step 3: photoetching opens channel region injection region and carries out channel region injection forms second in the semiconductor substrate
The channel region of conduction type doping, the channel region and drift region side contact or separated by a distance.
A further improvement is that each two neighboring buried layer section buried structure that mutual dislocation forms in the longitudinal direction
Making drift region when break-over of device within the scope of entire depth is all current lead-through region.
A further improvement is that the doping concentration of other buried layer sections except the buried layer section of the channel region is identical
Or it is not identical.
A further improvement is that further comprising the steps of:
Step 4: forming field oxygen above the drift region.
Step 5: formation gate dielectric layer and polysilicon gate, the polysilicon gate are horizontally extended to from the channel region
Above the drift region, the channel region surface covered by the polysilicon gate is used to form channel, the polysilicon gate
First side is located above the channel region, second side is located above the field oxygen at the top of the drift region.
Step 6: the source and drain for carrying out the first conduction type heavy doping is injected to form source region and drain region, the source region is formed in
First side autoregistration in the channel region and with the polysilicon gate, the drain region is formed in the drift region, described
Second side of field oxygen and the drain region laterally contact.
Step 7: carrying out the second conduction type heavily-doped implant forms channel draw-out area, the channel draw-out area is formed in
In the channel region and for drawing the channel region, the channel draw-out area and the source region are laterally contacted.
The present invention is made by the way that the buried layer of drift region is divided into multiple buried layer sections with various concentration and different depth
Buried layer section, in the structure of longitudinal mutual sequence, can reduce the JFET effect between channel region and drift region in drift region, from
And when can improve break-over of device drift region current lead-through region, the optimal drift region being able to achieve within the scope of entire depth is all
Current lead-through region, this can reduce the conducting resistance of device.
The present invention is also configured by the doping concentration to the buried layer section near channel region, so that the buried layer section is mixed
Miscellaneous concentration it is maximum and meet enable the drift region between the adjacent buried layer section in channel region side and the side drain terminal voltage just
Stage beginning is fully depleted, and is thus avoided that and just punctures in the drain terminal voltage initial stage, i.e., the invention can avoid small
In the extremely low voltage breakdown of operating voltage, so breakdown voltage can be improved.
Detailed description of the invention
The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:
Fig. 1 is the structural schematic diagram of existing horizontal proliferation field effect transistor；
Fig. 2A is the ionization by collision analogous diagram of existing device shown in Fig. 1；
Fig. 2 B is the depletion region analogous diagram of existing device shown in Fig. 1；
Fig. 3 A is the current density analogous diagram of existing device shown in Fig. 1；
Fig. 3 B is in Fig. 3 A along the current density plot of the lengthwise position of AA line；
Fig. 4 is the structural schematic diagram of one horizontal proliferation field effect transistor of the embodiment of the present invention；
Fig. 5 is the structural schematic diagram of one horizontal proliferation field effect transistor of the embodiment of the present invention.
Specific embodiment
As shown in figure 4, being the structural schematic diagram of one horizontal proliferation field effect transistor of the embodiment of the present invention；With N-type device
For, one horizontal proliferation field effect transistor of the embodiment of the present invention includes:
The drift region 2 of n-type doping is formed in P-type semiconductor substrate such as silicon substrate 1；In the embodiment of the present invention one, institute
It states drift region 2 to be directly made of N-type epitaxy layer 2, N-type epitaxy layer 2 is formed in the surface of semiconductor substrate 1.
The channel region 4 of p-type doping, is formed in the drift region 2 of the semiconductor substrate 1.
It is formed with the buried layer i.e. PTOP of p-type doping in the drift region 2, the buried layer is divided into various concentration and not
With multiple buried layer sections of depth, buried layer section 5a corresponds to PTOP1 in Fig. 4, and buried layer section 5b corresponds to PTOP2, and buried layer section 5c is corresponding
Correspond to PTOP4 in PTOP3, buried layer section 5d.The embodiment of the present invention is a kind of, and the epitaxial layer of the drift region 2 passes through multiple extension
Growth is formed, and each buried layer section carries out ion implanting in epitaxial surface after epitaxial growth corresponding with its depth and formed,
Dosage by adjusting ion implanting adjusts the doping concentration of each buried layer section.Depth such as buried layer section 5c is most deep, buried layer section
5c can carry out photoetching when epitaxial layer is grown at position corresponding to buried layer section 5c and add ion implantation technology, and photoetching process can be with
The lateral position of buried layer section 5c is selected, as long as ion implanting carries out surface injection, does not need the injection of big energy.Generally,
It is formed from the buried layer section of depth using identical ion implanting, the doping concentration of the buried layer section of depth same in this way is all identical；?
The doping concentration of the buried layer section of same depth can also be different in other embodiments.The buried layer section of other each depth also uses identical
Method is formed.
The depth difference of each two neighboring buried layer section makes the channel region 4 and institute to mutual dislocation in the longitudinal direction
The JFET effect stated between drift region 2 reduces, the current lead-through region of the drift region 2 when improving break-over of device.This hair
Bright embodiment is a kind of, and each two neighboring buried layer section buried structure that mutual dislocation forms in the longitudinal direction makes break-over of device
When entire depth within the scope of the drift region 2 all be current lead-through region.Arrow 302 corresponds to conducting electric current in Fig. 4, can
Know, a kind of current lead-through region of the embodiment of the present invention can be distributed in the longitudinal region of entire drift region 2, and be no longer limited to
The top area of buried layer.
Near the channel region 4 buried layer section 5a doping concentration be greater than the buried layer other buried layer section 5b, 5c and
The doping concentration of the doping concentration of 5d, other buried layer sections except the buried layer section of the channel region 4 is identical or not phase
Together.And in the embodiment of the present invention one, make 4 side of channel region near the doping concentration of the buried layer section 5a of the channel region 4
The drift region 2 between the adjacent buried layer section 5b in the side is that the drift region 2 in region shown in dotted line frame 301 can leak
The initial stage of end voltage is fully depleted, and can be avoided just puncture in the initial stage of drain terminal voltage in this way, so this
Inventive embodiments one can be avoided low-voltage breakdown.
Horizontal proliferation field effect transistor further include:
It is formed in the polysilicon gate 6 of 1 top of semiconductor substrate, 1 table of the polysilicon gate 6 and the semiconductor substrate
Face isolation has gate dielectric layer such as gate oxide, and horizontally the polysilicon gate 6 extends to the drift above the channel region 4
2 top of area is moved, channel is used to form by 4 surface of the channel region that the polysilicon gate 6 covers；The of the polysilicon gate 6
One side is located at 4 top of channel region, second side is located at 2 top of drift region.
By N-type heavily doped region, that is, N+ district's groups at source region 7 and drain region 8, the source region 7 be formed in the channel region 4 simultaneously
With the first side autoregistration of the polysilicon gate 6, the drain region 8 is formed in the drift region 2.
Oxygen 3, above the drift region 2 between the channel region 4 and the drain region 8, the second of the field oxygen 3
Side and the laterally contact of the drain region 8, the first side of the field oxygen 3 and the channel region 4 are at a distance；The polysilicon gate
6 extend to 3 top of field oxygen.The field oxygen 3 is shallow trench field oxygen or local field oxygen.
By p-type heavily doped region, that is, area P+ channel draw-out area 9, the channel draw-out area 9 is formed in the channel region 4 simultaneously
For the channel region 4 to be drawn, the channel draw-out area 9 and the laterally contact of the source region 7.
Polysilicon field plate 6a is formed on the surface of the field oxygen 3 of 8 side of drain region.Drain region 8 and polysilicon field plate 6a, which pass through, to be connect
Contact hole 10 is connected to the drain electrode formed by front metal layer 11；Front metal layer 11 is also formed with grid and source electrode.Grid passes through
Contact hole 10 and polysilicon gate 6 contact；Source electrode is connected by contact hole 10 and source region 7 and channel draw-out area 9.
Doping type is carried out the exchange of N-type and p-type first is that be illustrated by taking N-type device as an example by the embodiment of the present invention,
P-type device can be obtained, P-type device is no longer described in detail here.
Compare shown in Fig. 1 and Fig. 4 it is found that the embodiment of the present invention one is by being divided into the buried layer of drift region 2 with Bu Tong dense
Multiple buried layer sections of degree and different depth, and make structure of the buried layer section in drift region 2 in longitudinal mutual sequence, ditch can be reduced
JFET effect between road area and drift region, the current lead-through region of drift region 2 when so as to improve break-over of device, optimal energy are real
Drift region 2 within the scope of present entire depth is all current lead-through region, this can reduce the conducting resistance of device.The present invention is real
It applies example one to be also configured by the doping concentration to the buried layer section 5a near channel region 4, so that the doping of buried layer section 5a
Concentration is maximum and meeting makes drift region 2 between 4 side of channel region and the adjacent buried layer section 5a in the side i.e. shown in dotted line frame 301
The drift region in region can be fully depleted in the initial stage of drain terminal voltage, be thus avoided that the drain terminal voltage initial stage just
Puncture, i.e., the embodiment of the present invention one is avoided that in the extremely low voltage breakdown for being less than operating voltage, so breakdown potential can be improved
Pressure.
As shown in figure 5, being the structural schematic diagram of two horizontal proliferation field effect transistor of the embodiment of the present invention；The present invention is implemented
In place of the difference of one horizontal proliferation field effect transistor of two horizontal proliferation field effect transistor of example and the embodiment of the present invention are as follows: this hair
The drift region 2a in bright embodiment two is made of N-type deep trap, and N-type deep trap 2a is realized by ion implanting；Each buried layer
Section realizes that the depth of each buried layer section of energy adjustment by adjusting ion implanting passes through adjusting ion by ion implanting
The dosage of injection adjusts the doping concentration of each buried layer section.The surface of semiconductor substrate 1 outside N-type deep trap 2a is formed with P+
Area 12, the area P+ 12 are connected to the underlayer electrode being made of front metal layer 11 by contact hole 10.
As shown in figure 4, the manufacturing method of one horizontal proliferation field effect transistor of the embodiment of the present invention includes the following steps:
Step 1: forming the drift region 2 of n-type doping in P-type semiconductor substrate 1；The drift region 2 uses multiple extension
Technique is formed.
Step 2: form the buried layer of p-type doping in the drift region 2, the buried layer is divided into various concentration and not
With multiple buried layer sections of depth；Each buried layer section is used after epitaxial growth corresponding with its depth in epitaxial surface
Photoetching adds ion implanting to be formed, and the dosage by adjusting ion implanting adjusts the doping concentration of each buried layer section.
The depth difference of each two neighboring buried layer section makes the channel region 4 and institute to mutual dislocation in the longitudinal direction
The JFET effect stated between drift region 2 reduces, the current lead-through region of the drift region 2 when improving break-over of device.
It is greater than the doping concentration of other buried layer sections of the buried layer near the doping concentration of the buried layer section of channel region 4, and
The buried layer section for keeping 4 side of channel region adjacent with the side near the doping concentration of the buried layer section of the channel region 4
Between the drift region 2 can be fully depleted in the initial stage of drain terminal voltage.
Step 3: photoetching opens 4 injection region of channel region and carries out channel region 4 and be infused in the semiconductor substrate 1 to form P
The channel region 4 of type doping, the channel region 4 and the contact or separated by a distance of 2 side of the drift region.
Step 4: forming field oxygen 3 above the drift region 2；
Step 5: forming gate dielectric layer such as gate oxide and polysilicon gate 6, the polysilicon gate 6 is horizontally from described
Channel region 4 extends to 2 top of drift region, is used to form ditch by 4 surface of the channel region that the polysilicon gate 6 covers
Road, the first side of the polysilicon gate 6 is located at 4 top of channel region, second side is located at the institute at the top of the drift region 2
State 3 top of oxygen.Polysilicon field plate is formed on the surface of the field oxygen 3 close to 8 side of drain region while forming polysilicon gate 6
6a。
Step 6: the source and drain for carrying out N-type heavy doping is injected to form source region 7 and drain region 8, the source region 7 is formed in the ditch
First side autoregistration in road area 4 and with the polysilicon gate 6, the drain region 8 are formed in the drift region 2, the field
Second side of oxygen 3 and the laterally contact of the drain region 8.
Step 7: carrying out p-type heavily-doped implant forms channel draw-out area 9, the channel draw-out area 9 is formed in the channel
In area 4 and for the channel region 4 to be drawn, the channel draw-out area 9 and the laterally contact of the source region 7.
Later, interlayer film, contact hole 10 and front metal layer 11 are formed.Contact hole 10 passes through interlayer film, to front metal
Layer 11 is patterned to form source electrode, grid and drain electrode.
As shown in figure 5, the manufacturing method of two horizontal proliferation field effect transistor of the embodiment of the present invention includes the following steps:
Step 1: forming the drift region 2 of n-type doping in P-type semiconductor substrate 1；The drift region 2 uses N-type deep trap
Technique is formed.
Step 2: add ion implantation technology to form the buried layer that p-type is adulterated in the drift region 2 using photoetching, it is described to bury
Layer is divided into multiple buried layer sections with various concentration and different depth.
The depth difference of each two neighboring buried layer section makes the channel region 4 and institute to mutual dislocation in the longitudinal direction
The JFET effect stated between drift region 2 reduces, the current lead-through region of the drift region 2 when improving break-over of device.
The doping for the other buried layer sections for being greater than the buried layer near the doping concentration of the buried layer section 5a of the channel region 4 is dense
Degree, and the doping concentration of the buried layer section near the channel region 4 make 4 side of channel region it is adjacent with the side described in bury
The drift region 2 between interval can be fully depleted in the initial stage of drain terminal voltage.
By adjusting the depth of each buried layer section of energy adjustment of ion implanting, by the dosage tune for adjusting ion implanting
Save the doping concentration of each buried layer section.
The buried structure of each two neighboring buried layer section mutual dislocation composition in the longitudinal direction is whole when making break-over of device
The drift region 2 in a depth bounds is all current lead-through region.
The doping concentration of other buried layer sections except the buried layer section of the channel region 4 is identical or not identical.
Step 3: photoetching opens 4 injection region of channel region and carries out channel region 4 and be infused in the semiconductor substrate 1 to form P
The channel region 4 of type doping, the channel region 4 and the contact or separated by a distance of 2 side of the drift region.
Step 4: forming field oxygen 3 above the drift region 2；
Step 5: forming gate dielectric layer such as gate oxide and polysilicon gate 6, the polysilicon gate 6 is horizontally from described
Channel region 4 extends to 2 top of drift region, is used to form ditch by 4 surface of the channel region that the polysilicon gate 6 covers
Road, the first side of the polysilicon gate 6 is located at 4 top of channel region, second side is located at the institute at the top of the drift region 2
State 3 top of oxygen.Polysilicon field plate is formed on the surface of the field oxygen 3 close to 8 side of drain region while forming polysilicon gate 6
6a。
Step 6: the source and drain for carrying out N-type heavy doping is injected to form source region 7 and drain region 8, the source region 7 is formed in the ditch
First side autoregistration in road area 4 and with the polysilicon gate 6, the drain region 8 are formed in the drift region 2, the field
Second side of oxygen 3 and the laterally contact of the drain region 8.
Step 7: progress p-type heavily-doped implant forms channel draw-out area 9 and the area P+ 12, the channel draw-out area 9 are formed in
In the channel region 4 and for the channel region 4 to be drawn, the channel draw-out area 9 and the laterally contact of the source region 7.The area P+
12 are formed in the surface of the semiconductor substrate 1 outside N-type deep trap 2.
Later, interlayer film, contact hole 10 and front metal layer 11 are formed.Contact hole 10 passes through interlayer film, to front metal
Layer 11 is patterned to form source electrode, grid, drain electrode and underlayer electrode.
The present invention has been described in detail through specific embodiments, but these are not constituted to limit of the invention
System.Without departing from the principles of the present invention, those skilled in the art can also make many modification and improvement, these are also answered
It is considered as protection scope of the present invention.
Claims (22)
1. a kind of horizontal proliferation field effect transistor characterized by comprising
The drift region of first conduction type doping, is formed in the second conductive type semiconductor substrate；
The channel region of second conduction type doping, is formed in the semiconductor substrate；The channel region and the drift region side
The face contact and drift region surrounds the channel region；
The buried layer of the second conduction type doping is formed in the drift region, the buried layer is divided into various concentration and difference
Multiple buried layer sections of depth；
The depth difference of each two neighboring buried layer section makes the channel region and the drift to mutual dislocation in the longitudinal direction
JFET effect between area reduces, the current lead-through region of drift region when improving break-over of device, has in the buried layer
There is depth to be greater than the buried layer section of the depth of the channel region, the current lead-through region is made to extend to depth greater than the channel region
The drift region in；
It is greater than the doping concentration of other buried layer sections of the buried layer near the doping concentration of the buried layer section of the channel region, and most
Doping concentration close to the buried layer section of the channel region makes between the adjacent buried layer section in the channel region side and the side
The drift region can be fully depleted in the initial stage of drain terminal voltage；Depth near the buried layer section of the channel region is big
In the depth of the channel region.
2. horizontal proliferation field effect transistor as described in claim 1, it is characterised in that: the drift region is made of deep trap,
Each buried layer section realizes that the depth of each buried layer section of energy adjustment by adjusting ion implanting is led to by ion implanting
The dosage for overregulating ion implanting adjusts the doping concentration of each buried layer section.
3. horizontal proliferation field effect transistor as described in claim 1, it is characterised in that: the drift region is by epitaxial layer group
At the epitaxial layer of the drift region is by being repeatedly epitaxially-formed, and each buried layer section is in extension corresponding with its depth
It carries out ion implanting in epitaxial surface after growth to be formed, the dosage by adjusting ion implanting adjusts the doping of each buried layer section
Concentration.
4. horizontal proliferation field effect transistor as described in claim 1, it is characterised in that: each two neighboring buried layer section exists
The buried structure that mutual dislocation forms on longitudinal direction makes drift region when break-over of device within the scope of entire depth all be electricity
Flow conducting region.
5. horizontal proliferation field effect transistor as described in claim 1, it is characterised in that: near the buried layer of the channel region
The doping concentration of other buried layer sections except section is identical or not identical.
6. the horizontal proliferation field effect transistor as described in any claim in claim 1 to 5, it is characterised in that: laterally
Diffusion field effect transistor is N-type device, and the first conduction type is N-type, and the second conduction type is p-type.
7. the horizontal proliferation field effect transistor as described in any claim in claim 1 to 5, it is characterised in that: laterally
Diffusion field effect transistor is P-type device, and the first conduction type is p-type, and the second conduction type is N-type.
8. the horizontal proliferation field effect transistor as described in any claim in claim 1 to 5, which is characterized in that laterally
Spread field effect transistor further include:
It is formed in the polysilicon gate of the semiconductor substrate, the polysilicon gate and semiconductor substrate surface isolation have
Gate dielectric layer, horizontally the polysilicon gate is extended to above the channel region above the drift region, by the polycrystalline
The channel region surface of Si-gate covering is used to form channel；The first side of the polysilicon gate is located on the channel region
Side, second side are located above the drift region；
The source region of first conduction type heavy doping and drain region, the source region is formed in the channel region and and the polysilicon gate
First side autoregistration, the drain region is formed in the drift region.
9. horizontal proliferation field effect transistor as claimed in claim 8, which is characterized in that the horizontal proliferation field effect transistor
Pipe further include:
The channel draw-out area of second conduction type heavy doping, the channel draw-out area are formed in the channel region and are used for institute
Channel region extraction is stated, the channel draw-out area and the source region laterally contact.
10. horizontal proliferation field effect transistor as claimed in claim 8, which is characterized in that the horizontal proliferation field-effect is brilliant
Body pipe further include:
Oxygen, above the drift region between the channel region and the drain region, second side of the field oxygen and described
Drain region laterally contacts, and the first side of the field oxygen and the channel region are at a distance；The polysilicon gate extends to described
Above the oxygen of field.
11. a kind of manufacturing method of horizontal proliferation field effect transistor, which comprises the steps of:
Step 1: forming the drift region of the first conduction type doping in the second conductive type semiconductor substrate；The drift region
It is formed using multiple epitaxy technique；
Step 2: forming the buried layer of the second conduction type doping in the drift region, the buried layer is divided into various concentration
With multiple buried layer sections of different depth；Each buried layer section carries out after epitaxial growth corresponding with its depth in epitaxial surface
It is formed using photoetching plus ion implanting, the dosage by adjusting ion implanting adjusts the doping concentration of each buried layer section；
The depth difference of each two neighboring buried layer section to mutual dislocation in the longitudinal direction, make channel region and the drift region it
Between JFET effect reduce, the current lead-through region of drift region when improving break-over of device；Have in the buried layer deep
Degree is greater than the buried layer section of the depth for the channel region being subsequently formed, and the current lead-through region is made to extend to depth greater than the channel
In the drift region in area；
Near channel region buried layer section doping concentration be greater than the buried layer other buried layer sections doping concentration, and near
The doping concentration of the buried layer section of the channel region makes the institute between the adjacent buried layer section in the channel region side and the side
Stating drift region can be fully depleted in the initial stage of drain terminal voltage；
Step 3: photoetching opens channel region injection region and carries out channel region injection forms the second conduction in the semiconductor substrate
The channel region of type doping, the channel region and the drift region side contact and the drift region surrounds the channel region,
It is greater than the depth of the channel region near the depth of the buried layer section of the channel region.
12. the manufacturing method of horizontal proliferation field effect transistor as claimed in claim 11, it is characterised in that: each two neighboring
It is described within the scope of entire depth when the buried structure of buried layer section mutual dislocation composition in the longitudinal direction makes break-over of device
Drift region is all current lead-through region.
13. the manufacturing method of horizontal proliferation field effect transistor as claimed in claim 11, it is characterised in that: near described
The doping concentration of other buried layer sections except the buried layer section of channel region is identical or not identical.
14. the manufacturing method of horizontal proliferation field effect transistor as claimed in claim 11, which is characterized in that further include step
It is rapid:
Step 4: forming field oxygen above the drift region；
Step 5: forming gate dielectric layer and polysilicon gate, the polysilicon gate horizontally extends to from the channel region described
Above drift region, the channel region surface covered by the polysilicon gate is used to form channel, and the first of the polysilicon gate
Side is located above the channel region, second side is located above the field oxygen at the top of the drift region；
Step 6: the source and drain for carrying out the first conduction type heavy doping is injected to form source region and drain region, the source region is formed in described
First side autoregistration in channel region and with the polysilicon gate, the drain region are formed in the drift region, the field oxygen
Second side and the drain region laterally contact；
Step 7: carrying out the second conduction type heavily-doped implant forms channel draw-out area, the channel draw-out area is formed in described
In channel region and for drawing the channel region, the channel draw-out area and the source region are laterally contacted.
15. the manufacturing method of the horizontal proliferation field effect transistor as described in any claim in claim 11 to 14,
Be characterized in that: horizontal proliferation field effect transistor is N-type device, and the first conduction type is N-type, and the second conduction type is p-type.
16. the manufacturing method of the horizontal proliferation field effect transistor as described in any claim in claim 11 to 14,
Be characterized in that: horizontal proliferation field effect transistor is P-type device, and the first conduction type is p-type, and the second conduction type is N-type.
17. a kind of manufacturing method of horizontal proliferation field effect transistor, which comprises the steps of:
Step 1: forming the drift region of the first conduction type doping in the second conductive type semiconductor substrate；The drift region
It is formed using deep trap technique；
Step 2: adding ion implantation technology to form the buried layer that the second conduction type adulterates, institute in the drift region using photoetching
It states buried layer and is divided into multiple buried layer sections with various concentration and different depth；
The depth difference of each two neighboring buried layer section to mutual dislocation in the longitudinal direction, make channel region and the drift region it
Between JFET effect reduce, the current lead-through region of drift region when improving break-over of device；Have in the buried layer deep
Degree is greater than the buried layer section of the depth for the channel region being subsequently formed, and the current lead-through region is made to extend to depth greater than the channel
In the drift region in area；
It is greater than the doping concentration of other buried layer sections of the buried layer near the doping concentration of the buried layer section of the channel region, and most
Doping concentration close to the buried layer section of the channel region makes between the adjacent buried layer section in the channel region side and the side
The drift region can be fully depleted in the initial stage of drain terminal voltage；
By adjusting the depth of each buried layer section of energy adjustment of ion implanting, the dosage by adjusting ion implanting adjusts each
The doping concentration of the buried layer section；
Step 3: photoetching opens channel region injection region and carries out channel region injection forms the second conduction in the semiconductor substrate
The channel region of type doping, the channel region and the drift region side contact and the drift region surrounds the channel region,
It is greater than the depth of the channel region near the depth of the buried layer section of the channel region.
18. the manufacturing method of horizontal proliferation field effect transistor as claimed in claim 17, it is characterised in that: each two neighboring
It is described within the scope of entire depth when the buried structure of buried layer section mutual dislocation composition in the longitudinal direction makes break-over of device
Drift region is all current lead-through region.
19. the manufacturing method of horizontal proliferation field effect transistor as claimed in claim 17, it is characterised in that: near described
The doping concentration of other buried layer sections except the buried layer section of channel region is identical or not identical.
20. the manufacturing method of horizontal proliferation field effect transistor as claimed in claim 17, which is characterized in that further include step
It is rapid:
Step 4: forming field oxygen above the drift region；
Step 5: forming gate dielectric layer and polysilicon gate, the polysilicon gate horizontally extends to from the channel region described
Above drift region, the channel region surface covered by the polysilicon gate is used to form channel, and the first of the polysilicon gate
Side is located above the channel region, second side is located above the field oxygen at the top of the drift region；
Step 6: the source and drain for carrying out the first conduction type heavy doping is injected to form source region and drain region, the source region is formed in described
First side autoregistration in channel region and with the polysilicon gate, the drain region are formed in the drift region, the field oxygen
Second side and the drain region laterally contact；
Step 7: carrying out the second conduction type heavily-doped implant forms channel draw-out area, the channel draw-out area is formed in described
In channel region and for drawing the channel region, the channel draw-out area and the source region are laterally contacted.
21. the manufacturing method of the horizontal proliferation field effect transistor as described in any claim in claim 17 to 20,
Be characterized in that: horizontal proliferation field effect transistor is N-type device, and the first conduction type is N-type, and the second conduction type is p-type.
22. the manufacturing method of the horizontal proliferation field effect transistor as described in any claim in claim 17 to 20,
Be characterized in that: horizontal proliferation field effect transistor is P-type device, and the first conduction type is p-type, and the second conduction type is N-type.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610148112.0A CN105789311B (en) | 2016-03-16 | 2016-03-16 | Horizontal proliferation field effect transistor and its manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610148112.0A CN105789311B (en) | 2016-03-16 | 2016-03-16 | Horizontal proliferation field effect transistor and its manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105789311A CN105789311A (en) | 2016-07-20 |
| CN105789311B true CN105789311B (en) | 2019-10-11 |
Family
ID=56393701
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610148112.0A Active CN105789311B (en) | 2016-03-16 | 2016-03-16 | Horizontal proliferation field effect transistor and its manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105789311B (en) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI628792B (en) * | 2017-09-21 | 2018-07-01 | 新唐科技股份有限公司 | Semiconductor substrate structures and semiconductor devices |
| CN108258051A (en) * | 2018-01-11 | 2018-07-06 | 上海华虹宏力半导体制造有限公司 | LDMOS device and its manufacturing method |
| EP3644374A1 (en) * | 2018-10-23 | 2020-04-29 | Infineon Technologies Dresden GmbH & Co . KG | Lateral superjunction transistor device and method for producing thereof |
| CN111293163B (en) * | 2018-12-06 | 2023-11-10 | 上海新微技术研发中心有限公司 | Laterally diffused metal oxide semiconductor field effect transistor |
| CN110112217A (en) * | 2019-04-15 | 2019-08-09 | 杭州电子科技大学 | Anti-single particle burns LDMOS device |
| CN112531026B (en) * | 2019-09-17 | 2022-06-21 | 无锡华润上华科技有限公司 | Lateral diffusion metal oxide semiconductor device and manufacturing method thereof |
| CN111524975A (en) * | 2020-04-17 | 2020-08-11 | 华虹半导体(无锡)有限公司 | Transverse diffusion high-voltage device and manufacturing method thereof |
| CN113611732A (en) * | 2021-07-02 | 2021-11-05 | 上海华虹宏力半导体制造有限公司 | JFET device |
| CN113594254B (en) * | 2021-07-29 | 2024-01-23 | 上海华虹宏力半导体制造有限公司 | LDMOS device structure for improving transconductance |
| CN113851521B (en) * | 2021-08-20 | 2023-08-18 | 上海华虹宏力半导体制造有限公司 | High-voltage field effect transistor structure for improving on-resistance characteristic and manufacturing method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102403350A (en) * | 2010-09-07 | 2012-04-04 | 上海华虹Nec电子有限公司 | LDMOS (laterally diffused metal oxide semiconductor) high-voltage device structure and preparation method |
| CN105206675A (en) * | 2015-08-31 | 2015-12-30 | 上海华虹宏力半导体制造有限公司 | Nldmos device and manufacturing method thereof |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6207994B1 (en) * | 1996-11-05 | 2001-03-27 | Power Integrations, Inc. | High-voltage transistor with multi-layer conduction region |
-
2016
- 2016-03-16 CN CN201610148112.0A patent/CN105789311B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102403350A (en) * | 2010-09-07 | 2012-04-04 | 上海华虹Nec电子有限公司 | LDMOS (laterally diffused metal oxide semiconductor) high-voltage device structure and preparation method |
| CN105206675A (en) * | 2015-08-31 | 2015-12-30 | 上海华虹宏力半导体制造有限公司 | Nldmos device and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105789311A (en) | 2016-07-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105789311B (en) | Horizontal proliferation field effect transistor and its manufacturing method | |
| CN106887452A (en) | Self-adjustable isolation biasing in semiconductor devices | |
| CN105226058A (en) | Dark diffusion region is utilized to prepare JFET and ldmos transistor in monolithic power integrated circuit | |
| CN103367445A (en) | LDMOS with accumulation enhancement implant | |
| CN105679820B (en) | JFET and its manufacturing method | |
| CN105810680B (en) | JFET and its manufacturing method | |
| CN106298935B (en) | LDMOS device and its manufacturing method | |
| CN102136493B (en) | High-voltage insulation type LDNMOS (laterally diffused metal oxide semiconductor) device and manufacture method thereof | |
| US11888022B2 (en) | SOI lateral homogenization field high voltage power semiconductor device, manufacturing method and application thereof | |
| CN106206320B (en) | The manufacturing method of LDMOS | |
| CN109935517A (en) | SGT device and its manufacturing method | |
| CN102136494A (en) | High-voltage isolating LDNMOS (Lateral Diffusion N-channel Metal Oxide Semiconductor) and manufacture method thereof | |
| CN105914231B (en) | Charge storage type IGBT and its manufacturing method | |
| CN105679831B (en) | Horizontal proliferation field-effect transistor and its manufacturing method | |
| CN106169503A (en) | There is semiconductor device and the manufacture method thereof of vertical float ring | |
| CN108666364A (en) | RFLDMOS devices and manufacturing method | |
| CN104659091A (en) | Ldmos device and manufacturing method thereof | |
| CN109888015A (en) | LDMOS device and preparation method thereof | |
| CN105047716B (en) | Radio frequency LDMOS device and its manufacturing method | |
| CN104241358B (en) | Radio frequency ldmos device and manufacturing method thereof | |
| CN110047930A (en) | VDMOS device | |
| CN109698239A (en) | NLDMOS device and its manufacturing method | |
| CN1331209C (en) | Semiconductor device channel termination | |
| CN104538441B (en) | Radio frequency LDMOS device and its manufacture method | |
| CN104282763B (en) | Radio frequency horizontal dual pervasion field effect transistor preparation method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |