CN108666364A - RFLDMOS devices and manufacturing method - Google Patents
RFLDMOS devices and manufacturing method Download PDFInfo
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- CN108666364A CN108666364A CN201810364760.9A CN201810364760A CN108666364A CN 108666364 A CN108666364 A CN 108666364A CN 201810364760 A CN201810364760 A CN 201810364760A CN 108666364 A CN108666364 A CN 108666364A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 39
- 229920005591 polysilicon Polymers 0.000 claims abstract description 39
- 238000002347 injection Methods 0.000 claims abstract description 17
- 239000007924 injection Substances 0.000 claims abstract description 17
- 230000005611 electricity Effects 0.000 claims abstract description 5
- 238000000034 method Methods 0.000 claims abstract description 5
- 229910052751 metal Inorganic materials 0.000 claims description 47
- 239000002184 metal Substances 0.000 claims description 47
- 229910021332 silicide Inorganic materials 0.000 claims description 34
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 34
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 21
- 229910052710 silicon Inorganic materials 0.000 claims description 21
- 239000010703 silicon Substances 0.000 claims description 21
- 238000002513 implantation Methods 0.000 claims description 16
- 239000000758 substrate Substances 0.000 claims description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 12
- 238000001259 photo etching Methods 0.000 claims description 12
- 150000002500 ions Chemical class 0.000 claims description 10
- 229920002120 photoresistant polymer Polymers 0.000 claims description 9
- 239000000377 silicon dioxide Substances 0.000 claims description 6
- WNUPENMBHHEARK-UHFFFAOYSA-N silicon tungsten Chemical group [Si].[W] WNUPENMBHHEARK-UHFFFAOYSA-N 0.000 claims description 6
- 238000005516 engineering process Methods 0.000 claims description 4
- 108091006146 Channels Proteins 0.000 claims description 3
- 108010075750 P-Type Calcium Channels Proteins 0.000 claims description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 3
- 229910052785 arsenic Inorganic materials 0.000 claims description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 3
- 238000000605 extraction Methods 0.000 claims description 3
- 229910052698 phosphorus Inorganic materials 0.000 claims description 3
- 239000011574 phosphorus Substances 0.000 claims description 3
- 230000005684 electric field Effects 0.000 abstract description 5
- 230000011218 segmentation Effects 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000010276 construction Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
Classifications
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- H01L29/7835—
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- H01L29/7816—
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
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- H01L29/0607—
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- H01L29/0847—
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- H01L29/404—
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- H01L29/66681—
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- H01L29/1045—
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- Toxicology (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a kind of RFLDMOS devices, its N-type is lightly doped drift region and is divided into upper layer and lower layer, it is below the polysilicon gate until encirclement drain region that drift region, which is lightly doped, in first N-type, it is to be lightly doped that the upright projection of drift region is Chong Die with the first N-type that drift region, which is lightly doped, by drain region side in second N-type, is the drop shadow spread that drift region is lightly doped without departing from the first N-type by polysilicon gate side；Two parts N-type is lightly doped drift region electricity and communicates；Faraday's ring is upper layer and lower layer, and is isolated with dielectric layer between two layers of faraday's ring.The present invention is by increasing by one layer of faraday's ring, reduce electric field strength of the gate edge close to drain terminal, it uses simultaneously and drift region segmentation injection is lightly doped twice, it can ensure while obtaining relatively high power density, do not increase electric field strength of the gate edge close to drain terminal again, that is, ensure that the reliability under high-performance.It is simple for process easy to implement the invention also discloses the manufacturing method of the RFLDMOS devices.
Description
Technical field
The present invention relates to semiconductor integrated circuit fields, more particularly to a kind of to be applied to what high-power RF signal amplified
RFLDMOS.The invention further relates to the manufacturing methods of the RFLDMOS devices.
Background technology
RFLDMOS (Radio Frequency Laterally Diffused Metal Oxide Semiconductor,
Rf-ldmos semiconductor) it is to be widely used in broadcasting and TV transmitting base station, mobile transmitting base station, radar etc.
The RF power device with high-gain, High Linear, high voltage, high-output power, operating voltage has two kinds of 28V and 50V,
The requirement of corresponding breakdown voltage is respectively 70V and 120V.
High-power RF device R FLDMOS for base station etc. includes such as lower structure：Source electrode, drain electrode, grid, raceway groove and base
Pole and Faraday shield ring, detailed construction are shown in Fig. 1.It is a N-type device.Device is located at the Grown in heavy doping
Epitaxial layer in, drain terminal there are one longer drift region to obtain required breakdown voltage, Faraday shield ring in drain terminal by adding
One layer of thin-medium and metallic plate composition.Higher pressure-resistant length (the heavily doped N-type drain terminal to polycrystalline by the low-doped drift region of N-type
The distance at silicon gate edge), and the metal Faraday cup of the adjusting field distribution as field plate codetermines.Raceway groove is by certainly
It is directed at the p-type ion implanting at grid source edge, and promotes to be formed by long-time high temperature, ultra-deep groove is used in combination to etch and insert
Void-free metal is connected on the substrate of p-type heavy doping, it is ensured that the source of device and raceway groove have good back metal to draw, phase
Connection for source and raceway groove that the diffusion technique in traditional structure is realized, can substantially reduce resistance and internal thermal resistance.
In RFLDMOS, if high performance, such as Idsat in order to obtain, Rdson, output power etc. is difficult to reach
To high reliability, such as HCI (hot carrier injection effect).A kind of new RFLDMOS structures described herein, this structure
Possess lower electric field strength close to drain terminal and drift region in gate edge, this is to be conducive to the HCI performances of device, while protecting again
High power density is held.
Invention content
Technical problem to be solved by the present invention lies in a kind of RFLDMOS devices are provided, the edge electricity of device grids is reduced
Field intensity improves reliability.
Another technical problem to be solved by this invention is to provide the manufacturing method of the RFLDMOS devices.
To solve the above problems, RFLDMOS devices of the present invention, including：
In P-type silicon substrate, has and p-type extension is lightly doped；
Yanzhong outside p-type is being lightly doped, there is N-type the drift region areas JiPXing Ti are lightly doped, drift region and p-type body is lightly doped in N-type
It is channel region between area；
The N-type is lightly doped in drift region, includes the drain region of the RFLDMOS devices, and drain region surface has metal silication
Object draws the drain electrode of the RFLDMOS devices；
In the areas PXing Ti include the source region of RFLDMOS devices, and the heavily doped P-type area that the areas PXing Ti are drawn；
Silicon face on heavily doped P-type area and source region also draws the two with metal silicide jointly forms the RFLDMOS
The source electrode of device；
The area surface of heavily doped P-type raceway groove bonding pad and RFLDMOS cover described in one layer of metal silicide extraction
The source electrode of RFLDMOS；
There is gate oxide on the silicon face in P-type channel area, polysilicon gate and metal silication are covered on gate oxide
Object；Polysilicon gate and gate oxide both ends have grid curb wall；
Drift is lightly doped in the N-type of metal silicide on polysilicon gate, the side wall by leaking side and close polysilicon gate
It moves in area and wraps up dielectric layer, metal faraday's ring is covered on dielectric layer；
The back side of the P-type silicon substrate also has back metal to form underlayer electrode；
The N-type is lightly doped drift region and is divided into first and second two parts, and it is from more that drift region, which is lightly doped, in the first N-type
Until surrounding drain region below polysilicon gate, it is that drift region is lightly doped with the first N-type that drift region, which is lightly doped, by drain region side in the second N-type
Upright projection overlapping, be the drop shadow spread that drift region is lightly doped without departing from the first N-type by polysilicon gate side；It is two-part
N-type is lightly doped drift region electricity and communicates；
Faraday's ring is upper layer and lower layer, and is isolated with dielectric layer between two layers of faraday's ring.
Further, drift region is lightly doped apart from 0.4~1 μm of polysilicon gate in second N-type.
To solve the above problems, the manufacturing method of RFLDMOS devices of the present invention, including following processing step：
1st step, the growing P-type extension in P type substrate；Gate oxide is grown with boiler tube above it, then to deposit N-type heavily doped
Miscellaneous polysilicon, or deposit the N-type ion implanting that undoped polysilicon carries out high dose again；Pass through photoetching plus etching work
Etching polysilicon is formed the gate structure of RFLDMOS devices by skill；
2nd step carries out the injection that drift region is lightly doped in the first N-type under the definition of photoresist, forms the first N-type and gently mixes
Miscellaneous drift region；
3rd step carries out the injection that drift region is lightly doped in the second N-type under the definition of photoresist, forms the second N-type and gently mixes
Miscellaneous drift region；
4th step, photoetching open the areas PXing Ti and inject window, carry out p-type ion implanting, form the areas PXing Ti；Again with photoresist
The injection window in source region and drain region is opened, the source region of RFLDMOS devices and the injection in drain region are carried out；Shape is injected in the areas PXing Ti
At heavily doped P-type area；
5th step, by metal silicide technology, in the top of polysilicon gate, source region, drain region and heavily doped P-type area
Upper formation metal silicide；
6th step deposits one layer of dielectric layer and one layer of metal silicide in entire silicon face；Pass through photoetching and etching work
Skill etches metal silicide to form first layer faraday's ring；
7th step, then deposit one layer of dielectric layer and second layer metal silicide in entire silicon face；Pass through photoetching and quarter
Etching technique etches second layer metal silicide to form second layer faraday's ring；
8th step deposits medium before contact hole, etches contact hole, forms contact.
Further, in the 1st step, P type substrate is heavy doping, and resistivity is 0.005~0.05ohm*cm；It is lightly doped
The doping concentration of p-type extension is 1014~1016cm-3；Polysilicon doping ion is phosphorus or arsenic, and concentration is more than 1020cm-3。
Further, in the 2nd step, the Implantation Energy that drift region is lightly doped in the first N-type is 100~200keV, injection
Dosage is 1E12~3E12cm-3。
Further, in the 3rd step, the Implantation Energy that drift region is lightly doped in the second N-type is 200~300keV, injection
Dosage is 0.5E12~2E12cm-2, drift region is lightly doped apart from 0.4~1 μm of polysilicon gate in the second N-type.
Further, in the 4th step, the implantation dosage in source region and drain region is 1E15~5E15cm-2, heavily doped P-type area
Implantation dosage is 1E15~5E15cm-2。
Further, in the 6th step, the dielectric layer of deposit is silica, and thickness isThe metal
Silicide is tungsten silicon.
Further, in the 7th step, the dielectric layer deposited again is silica, and thickness isDescribed
Metal silicide is tungsten silicon, forms second layer faraday's ring.
RFLDMOS devices of the present invention reduce gate edge close to drain terminal by increasing by one layer of faraday's ring
Electric field strength, while being injected using drift region segmentation is lightly doped twice, it is ensured that while obtaining relatively high power density, again
Do not increase electric field strength of the gate edge close to drain terminal, that is, ensure that the reliability under high-performance.It is of the present invention
The manufacturing method of RFLDMOS devices, it is simple for process.
Description of the drawings
Fig. 1 is the structural schematic diagram of traditional RFLDMOS devices.
Fig. 2 is the structural schematic diagram of RFLDMOS devices of the present invention.
Fig. 3~8 are RFLDMOS device fabrications step schematic diagrams of the present invention.
Fig. 9 is manufacturing process flow schematic diagram of the present invention.
Reference sign
1 is P type substrate, and 2 be p-type extension, and 3 be that the first N-type is lightly doped drift region, and 4 be the areas PXing Ti, and 5 be faraday's ring, 6
It is gate oxide, 7 be grid, and 8 be that drift region is lightly doped in the second N-type.
Specific implementation mode
The structures of RFLDMOS devices of the present invention as shown in figure 8, comprising：
In P-type silicon substrate, has and p-type extension is lightly doped.
Yanzhong outside p-type is being lightly doped, there is N-type the drift region areas JiPXing Ti are lightly doped, drift region and p-type body is lightly doped in N-type
It is channel region between area.
The N-type is lightly doped in drift region, includes the drain region of the RFLDMOS devices, and drain region surface has metal silication
Object draws the drain electrode of the RFLDMOS devices.
In the areas PXing Ti include the source region of RFLDMOS devices, and the heavily doped P-type area that the areas PXing Ti are drawn；
Silicon face on heavily doped P-type area and source region also draws the two with metal silicide jointly forms the RFLDMOS
The source electrode of device.
The area surface of heavily doped P-type raceway groove bonding pad and RFLDMOS cover described in one layer of metal silicide extraction
The source electrode of RFLDMOS.
There is gate oxide on the silicon face in P-type channel area, polysilicon gate and metal silication are covered on gate oxide
Object；Polysilicon gate and gate oxide both ends have grid curb wall.
Drift is lightly doped in the N-type of metal silicide on polysilicon gate, the side wall by leaking side and close polysilicon gate
It moves in area and wraps up dielectric layer, metal faraday's ring is covered on dielectric layer.
The back side of the P-type silicon substrate also has back metal to form underlayer electrode.
The N-type is lightly doped drift region and is divided into first and second part, and it is from polycrystalline that drift region, which is lightly doped, in the first N-type
Until surrounding drain region below silicon gate, it is that drift region is lightly doped with the first N-type that drift region, which is lightly doped, by drain region side in the second N-type
Upright projection is overlapped, and is the drop shadow spread that drift region is lightly doped without departing from the first N-type by polysilicon gate side；Two parts N-type
Drift region electricity is lightly doped to communicate.
Faraday's ring is upper layer and lower layer, and is isolated with dielectric layer between two layers of faraday's ring.
Drift region is lightly doped apart from 0.4~1 μm of polysilicon gate in second N-type.
The manufacturing method of RFLDMOS devices of the present invention, totally seven steps with reference to corresponding to 2~Fig. 8 of figure, packet
Contain：
1st step, the growing P-type extension in P type substrate, as shown in Figure 2.P type substrate is heavy doping, resistivity 0.005
~0.05ohm*cm；The doping concentration that p-type extension is lightly doped is 1014~1016cm-3.Above it gate oxidation is grown with boiler tube
Layer, then the polysilicon of N-type heavy doping is deposited, or deposit the N-type ion implanting that undoped polysilicon carries out high dose again；It is logical
It crosses photoetching and adds etching technics, etching polysilicon is formed to the gate structure of RFLDMOS devices；Polysilicon doping ion be phosphorus or
Arsenic, concentration are more than 1020cm-3。
2nd step carries out the injection that drift region is lightly doped in the first N-type under the definition of photoresist, forms the first N-type and gently mixes
Miscellaneous drift region；The Implantation Energy that drift region is lightly doped in first N-type is 100~200keV, implantation dosage 1E12~
3E12cm-3。
3rd step carries out the injection that drift region is lightly doped in the second N-type under the definition of photoresist, forms the second N-type and gently mixes
Miscellaneous drift region；The Implantation Energy that drift region is lightly doped in second N-type is 200~300keV, implantation dosage 0.5E12~2E12cm-2,
Drift region is lightly doped apart from 0.4~1 μm of polysilicon gate in second N-type.
4th step, photoetching open the areas PXing Ti and inject window, carry out p-type ion implanting, form the areas PXing Ti；Again with photoresist
The injection window in source region and drain region is opened, the source region of RFLDMOS devices and the injection in drain region are carried out；Shape is injected in the areas PXing Ti
At heavily doped P-type area；The implantation dosage in source region and drain region is 1E15~5E15cm-2, the implantation dosage in heavily doped P-type area is 1E15~
5E15cm-2。
5th step, by metal silicide technology, in the top of polysilicon gate, source region, drain region and heavily doped P-type area
Upper formation metal silicide.
6th step, the dielectric layer that one layer of dielectric layer deposition is deposited in entire silicon face is silica, and thickness isOne layer of metal silicide is re-formed, the metal silicide is tungsten silicon；It, will by photoetching and etching technics
Metal silicide etches to form first layer faraday's ring.
7th step, then one layer of dielectric layer is deposited in entire silicon face, dielectric layer is silica, and thickness isWith
And second layer metal silicide, such as tungsten silicon；By photoetching and etching technics, etch second layer metal silicide to form second
Layer faraday's ring.
8th step deposits medium before contact hole, etches contact hole, forms contact, and resulting devices are completed, as shown in Figure 8.
It these are only the preferred embodiment of the present invention, be not intended to limit the present invention.Those skilled in the art is come
It says, the invention may be variously modified and varied.All within the spirits and principles of the present invention, any modification made by is equal
Replace, improve etc., it should all be included in the protection scope of the present invention.
Claims (9)
1. a kind of RFLDMOS devices, including：
In P-type silicon substrate, has and p-type extension is lightly doped；
Yanzhong outside p-type is being lightly doped, there is N-type to be lightly doped the drift region areas JiPXing Ti, N-type be lightly doped drift region and the areas PXing Ti it
Between be channel region；
The N-type is lightly doped in drift region, includes the drain region of the RFLDMOS devices, and drain region surface is drawn with metal silicide
Go out the drain electrode of the RFLDMOS devices；
In the areas PXing Ti include the source region of RFLDMOS devices, and the heavily doped P-type area that the areas PXing Ti are drawn；In weight
Silicon face on doped p-type area and source region also draws the two with metal silicide jointly forms the RFLDMOS devices
Source electrode；
The area surface of heavily doped P-type raceway groove bonding pad and RFLDMOS cover described in one layer of metal silicide extraction
The source electrode of RFLDMOS；
There is gate oxide on the silicon face in P-type channel area, polysilicon gate and metal silicide are covered on gate oxide；It is more
Polysilicon gate and gate oxide both ends have grid curb wall；
Drift region is lightly doped in the N-type of metal silicide on polysilicon gate, the side wall by leaking side and close polysilicon gate
On wrap up dielectric layer, metal faraday's ring is covered on dielectric layer；
The back side of the P-type silicon substrate also has back metal to form underlayer electrode；
It is characterized in that：
The N-type is lightly doped drift region and is divided into first and second two parts, and it is from polysilicon that drift region, which is lightly doped, in the first N-type
Until surrounding drain region below grid, it is that hanging down for drift region is lightly doped with the first N-type that drift region, which is lightly doped, by drain region side in the second N-type
Shadow overlapping is delivered directly, is the drop shadow spread that drift region is lightly doped without departing from the first N-type by polysilicon gate side；Two parts N-type is light
Doped drift region electricity communicates；
Faraday's ring is upper layer and lower layer, and is isolated with dielectric layer between two layers of faraday's ring.
2. RFLDMOS devices as described in claim 1, it is characterised in that：Drift region is lightly doped apart from polycrystalline in second N-type
0.4~1 μm of silicon gate.
3. a kind of manufacturing method of manufacture RFLDMOS devices as described in claim 1, it is characterised in that：Including following technique
Step：
1st step, the growing P-type extension in P type substrate；Gate oxide is grown with boiler tube above it, then deposits N-type heavy doping
Polysilicon, or deposit the N-type ion implanting that undoped polysilicon carries out high dose again；It, will by photoetching plus etching technics
Etching polysilicon forms the gate structure of RFLDMOS devices；2nd step carries out the first N-type and is lightly doped under the definition of photoresist
The injection of drift region forms the first N-type and drift region is lightly doped；
3rd step carries out the injection that drift region is lightly doped in the second N-type under the definition of photoresist, forms the second N-type and drift is lightly doped
Move area；
4th step, photoetching open the areas PXing Ti and inject window, carry out p-type ion implanting, form the areas PXing Ti；It opens with photoresist again
The injection window in source region and drain region carries out the source region of RFLDMOS devices and the injection in drain region；Injection forms weight in the areas PXing Ti
Doped p-type area；
5th step, by metal silicide technology, the shape in the top of polysilicon gate, source region, drain region and heavily doped P-type area
At metal silicide；
6th step deposits one layer of dielectric layer and one layer of metal silicide in entire silicon face；It, will by photoetching and etching technics
Metal silicide etches to form first layer faraday's ring；
7th step, then deposit one layer of dielectric layer and second layer metal silicide in entire silicon face；Pass through photoetching and etching work
Skill etches second layer metal silicide to form second layer faraday's ring；
8th step deposits medium before contact hole, etches contact hole, forms contact.
4. the manufacturing method of RFLDMOS devices as claimed in claim 3, it is characterised in that：In 1st step, P type substrate is
Heavy doping, resistivity are 0.005~0.05ohm*cm；The doping concentration that p-type extension is lightly doped is 1014~1016cm-3；Polysilicon
Doped ions are phosphorus or arsenic, and concentration is more than 1020cm-3。
5. the manufacturing method of RFLDMOS devices as claimed in claim 3, it is characterised in that：In 2nd step, the first N-type is light
The Implantation Energy of doped drift region is 100~200keV, implantation dosage 1E12~3E12cm-3。
6. the manufacturing method of RFLDMOS devices as claimed in claim 3, it is characterised in that：In 3rd step, the second N-type is light
The Implantation Energy of doped drift region is 200~300keV, implantation dosage 0.5E12~2E12cm-2, drift is lightly doped in the second N-type
0.4~1 μm from polysilicon gate of offset.
7. the manufacturing method of RFLDMOS devices as claimed in claim 3, it is characterised in that：In 4th step, source region and leakage
The implantation dosage in area is 1E15~5E15cm-2, the implantation dosage in heavily doped P-type area is 1E15~5E15cm-2。
8. the manufacturing method of RFLDMOS devices as claimed in claim 3, it is characterised in that：In 6th step, Jie of deposit
Matter layer is silica, and thickness isThe metal silicide is tungsten silicon.
9. the manufacturing method of RFLDMOS devices as claimed in claim 3, it is characterised in that：In 7th step, deposit again
Dielectric layer be silica, thickness isThe metal silicide is tungsten silicon, forms second layer faraday's ring.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109712893A (en) * | 2019-01-28 | 2019-05-03 | 上海华虹宏力半导体制造有限公司 | The process of optimised devices hot carrier in jection performance in RFLDMOS |
| CN111370312A (en) * | 2020-03-24 | 2020-07-03 | 上海华虹宏力半导体制造有限公司 | Manufacturing method of RFLDMOS device |
| CN112117332A (en) * | 2020-11-02 | 2020-12-22 | 上海华虹宏力半导体制造有限公司 | LDMOS device and technological method |
| CN116364553A (en) * | 2023-06-02 | 2023-06-30 | 华南理工大学 | Method for manufacturing semiconductor device and semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109712893A (en) * | 2019-01-28 | 2019-05-03 | 上海华虹宏力半导体制造有限公司 | The process of optimised devices hot carrier in jection performance in RFLDMOS |
| CN111370312A (en) * | 2020-03-24 | 2020-07-03 | 上海华虹宏力半导体制造有限公司 | Manufacturing method of RFLDMOS device |
| CN111370312B (en) * | 2020-03-24 | 2023-05-02 | 上海华虹宏力半导体制造有限公司 | Manufacturing method of RFLDMOS device |
| CN112117332A (en) * | 2020-11-02 | 2020-12-22 | 上海华虹宏力半导体制造有限公司 | LDMOS device and technological method |
| CN112117332B (en) * | 2020-11-02 | 2023-08-22 | 上海华虹宏力半导体制造有限公司 | LDMOS device and process method |
| CN116364553A (en) * | 2023-06-02 | 2023-06-30 | 华南理工大学 | Method for manufacturing semiconductor device and semiconductor device |
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