CN111370312A - Manufacturing method of RFLDMOS device - Google Patents
Manufacturing method of RFLDMOS device Download PDFInfo
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- CN111370312A CN111370312A CN202010210606.3A CN202010210606A CN111370312A CN 111370312 A CN111370312 A CN 111370312A CN 202010210606 A CN202010210606 A CN 202010210606A CN 111370312 A CN111370312 A CN 111370312A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 93
- 229920005591 polysilicon Polymers 0.000 claims abstract description 89
- 239000000758 substrate Substances 0.000 claims abstract description 51
- 238000000034 method Methods 0.000 claims abstract description 50
- 210000000746 body region Anatomy 0.000 claims abstract description 41
- 238000005530 etching Methods 0.000 claims abstract description 21
- 239000010410 layer Substances 0.000 claims description 32
- 229920002120 photoresistant polymer Polymers 0.000 claims description 24
- 238000005468 ion implantation Methods 0.000 claims description 17
- 238000001259 photo etching Methods 0.000 claims description 10
- 239000011229 interlayer Substances 0.000 claims description 6
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 238000000206 photolithography Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 238000009826 distribution Methods 0.000 description 3
- 238000000151 deposition Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000009987 spinning Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
Abstract
The application discloses a manufacturing method of an RFLDMOS device, and relates to the field of semiconductor manufacturing. The method includes forming a polysilicon layer on a substrate; etching the polysilicon layer according to the pattern defined by the first mask to form a polysilicon gate and auxiliary gates, wherein the auxiliary gates are arranged between two adjacent polysilicon gates with the spacing larger than a preset distance; etching and removing the auxiliary gate according to the pattern defined by the second mask; forming a drift region and a body region in a substrate; forming a drain region in the drift region and a source region in the body region; the problem that the shape stability of the side wall of the grid electrode of the RFLDMOS device is not high is solved; the method achieves the effects of improving the stability of the grid side wall morphology of the RFLDMOS device, ensuring the channel concentration and improving the stability of the threshold voltage.
Description
Technical Field
The application relates to the field of semiconductor manufacturing, in particular to a manufacturing method of an RFLDMOS device.
Background
An RFLDMOS (Radio Frequency Lateral Double-diffused MOSFET) has the advantages of high operating Frequency, high withstand voltage, high output power, high gain, high linearity and the like, and is widely applied to mobile transmitting base stations, broadcast television transmitting base stations, broadband Frequency modulation transmitters, airborne transponders, radar systems and the like.
The threshold voltage is one of the main parameters of the RFLDMOS device and represents the minimum gate-source voltage when the surface of the channel region is inverted and a certain current flows. In order to obtain the best operation performance of the device, the threshold voltage of the actual product needs to be stabilized within the designed voltage range.
The shape of the grid has important influence on the threshold voltage, and in the manufacturing process of the RFLDMOS device, the polysilicon gate is formed by etching the polysilicon, and if the shape of the etched grid is unstable, the threshold voltage of the device can be influenced, so that the performance of the device is influenced.
Disclosure of Invention
In order to solve the problems in the related art, the application provides a manufacturing method of an RFLDMOS device. The technical scheme is as follows:
in one aspect, an embodiment of the present application provides a method for manufacturing an RFLDMOS device, where the method includes:
forming a polysilicon layer on a substrate;
etching the polysilicon layer according to the pattern defined by the first mask to form a polysilicon gate and auxiliary gates, wherein the auxiliary gates are arranged between two adjacent polysilicon gates with the spacing larger than a preset distance;
etching and removing the auxiliary gate according to the pattern defined by the second mask;
forming a drift region and a body region in a substrate;
a drain region is formed in the drift region, and a source region is formed in the body region.
Optionally, the plurality of auxiliary gates are uniformly arranged between two adjacent polysilicon gates having a distance larger than a predetermined distance.
Optionally, the removing the auxiliary gate by etching according to the pattern defined by the second mask includes:
carrying out a photoetching process by using a second mask plate, and covering the polysilicon gate by photoresist;
and removing the auxiliary gate by an etching process.
Optionally, before forming the polysilicon layer on the substrate, the method further includes:
a gate oxide layer is formed on a substrate.
Optionally, forming a drift region in the substrate includes:
defining a drift region pattern through a photoetching process;
and performing ion implantation according to the drift region pattern to form a drift region in the substrate.
Optionally, forming a body region in the substrate includes:
defining a body region pattern through a photoetching process, wherein one side of the polysilicon gate outside the body region pattern is not covered by a photoresist;
and carrying out body region ion implantation through a self-alignment process, and carrying out high-temperature well pushing to form a body region in the substrate.
Optionally, forming a drain region in the drift region and forming a source region in the body region includes:
defining a drain region pattern above the drift region through a photoetching process, and forming a drain region in the drift region through ion implantation;
a source region pattern is defined above the body region by a photolithography process, and a source region is formed in the body region by an ion implantation process.
Optionally, after forming the drain region in the drift region and forming the source region in the body region, the method further includes:
forming an interlayer dielectric layer on a substrate;
forming a through hole in the interlayer dielectric layer;
and leading out the source region, the drain region and the polysilicon gate through the through hole to form a source electrode, a drain electrode and a grid electrode.
The technical scheme at least comprises the following advantages:
forming a polysilicon layer on a substrate, etching the polysilicon layer according to a pattern defined by a first mask to form a polysilicon gate and auxiliary gates, wherein the auxiliary gates are arranged between two adjacent polysilicon gates with the distance larger than a preset distance; etching and removing the auxiliary gate according to the pattern defined by the second mask, forming a drift region and a body region in the substrate, forming a drain region in the drift region, and forming a source region in the body region; the problem that the shape stability of the side wall of the grid electrode of the RFLDMOS device is not high is solved; the gate sidewall morphology stability of the RFLDMOS device is improved, the channel concentration is guaranteed, and therefore the threshold voltage stability is improved.
Drawings
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a method for manufacturing an RFLDMOS device according to an embodiment of the present disclosure;
fig. 2 is a partial cross-sectional view of an RFLDMOS device provided in an embodiment of the present application during a manufacturing process;
fig. 3 is a schematic diagram illustrating a positional relationship between an auxiliary gate and a polysilicon gate in an RFLDMOS device manufacturing process according to an embodiment of the present disclosure;
fig. 4 is a partial cross-sectional view of an RFLDMOS device provided in an embodiment of the present application during a manufacturing process;
fig. 5 is a schematic diagram illustrating a positional relationship among an auxiliary gate, a polysilicon gate, and a photoresist in an RFLDMOS device manufacturing process according to an embodiment of the present disclosure;
fig. 6 is a partial cross-sectional view of an RFLDMOS device provided in an embodiment of the present application during a manufacturing process;
fig. 7 is a schematic diagram of a polysilicon gate in an RFLDMOS device manufacturing process according to an embodiment of the present disclosure;
fig. 8 is a cross-sectional view of an RFLDMOS device provided in an embodiment of the present application during a manufacturing process.
Detailed Description
The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.
When the RFLDMOS device is manufactured, a polysilicon layer is deposited and then etched to form a polysilicon gate, then the polysilicon is used as a mask for self-alignment to carry out ion implantation, and proper high-temperature well pushing is carried out to form a channel.
Because a plurality of RFLDMOS devices can be manufactured on the same substrate, due to the existence of a drift region and a body region of the LDOMOS device, the situation that the distance between two adjacent polysilicon gates is large can occur in a polysilicon gate pattern defined according to a mask, and the polysilicon gates can be regarded as isolated distribution under the situation. Due to the inherent characteristics of the etching process, after the polysilicon layer is etched according to the polysilicon gate pattern, the sidewall morphology of the polysilicon gate which is in isolated distribution is unstable, the doping concentration of the substrate below the sidewall of the polysilicon gate can be influenced, the channel concentration is influenced, and the threshold voltage of the RFLDMOS device is further influenced.
Please refer to fig. 1, which shows a flowchart of a method for fabricating an RFLDMOS device according to an embodiment of the present application. As shown in fig. 1, the method for fabricating the RFLDMOS device at least includes the following steps:
in step 101, a polysilicon layer is formed on a substrate.
Providing a substrate, and depositing polycrystalline silicon on the substrate to form a polycrystalline silicon layer.
In step 102, the polysilicon layer is etched according to the pattern defined by the first mask to form polysilicon gates and auxiliary gates, and a plurality of auxiliary gates are arranged between two adjacent polysilicon gates with the distance larger than a predetermined distance.
The first mask comprises a polysilicon gate pattern and an auxiliary gate pattern.
And spin-coating photoresist on the polysilicon layer, exposing by using a first mask plate, and transferring the polysilicon pattern and the auxiliary gate pattern on the first mask plate into the photoresist on the surface of the substrate through development.
And etching the polysilicon layer according to the polysilicon pattern and the auxiliary gate pattern by an etching process to obtain a plurality of polysilicon gates and a plurality of auxiliary gates.
The number of the polysilicon gates and the number of the auxiliary gates are determined according to actual conditions.
In the formed polysilicon gates, there are cases where the distance between two adjacent polysilicon gates is smaller than a predetermined distance, and the distance between two adjacent polysilicon gates is larger than the predetermined distance. A plurality of auxiliary gates are arranged between two adjacent polysilicon gates with the distance larger than a preset distance.
The predetermined distance is predetermined according to actual conditions.
The number of the auxiliary gates arranged between two adjacent polysilicon gates with a distance larger than a predetermined distance is determined according to actual conditions, and is not limited in the embodiment of the present application.
As shown in fig. 2, a plurality of polysilicon gates 22 and a plurality of auxiliary gates 23 are formed on a substrate 21, and the plurality of auxiliary gates 23 are arranged between two adjacent polysilicon gates 22 having a distance greater than a predetermined distance.
Fig. 3 is a schematic diagram schematically illustrating a position relationship between an auxiliary gate and a polysilicon gate in an RFLDMOS device manufacturing process.
The auxiliary gate is added between the two adjacent polysilicon gates with the distance larger than the preset distance, so that the polysilicon gates distributed in an isolating mode are changed into density distribution, and the stability of the sidewall appearance of the etched polysilicon gates is improved.
In step 103, the auxiliary gate is etched and removed according to the pattern defined by the second mask.
And removing all the auxiliary gates on the substrate and reserving the polysilicon gate.
A photoresist is spun on the substrate, and is exposed by using a second mask, and after development, the polysilicon gate 22 is covered by the photoresist 24, and the auxiliary gate 23 is not covered by the photoresist, as shown in fig. 4.
Fig. 5 exemplarily shows a schematic diagram of a position relationship of the auxiliary gate, the polysilicon gate and the photoresist in the RFLDMOS device manufacturing process, in fig. 5, the auxiliary gate 23 is not covered by the photoresist, and the polysilicon gate 22 is covered by the photoresist 24.
As shown in fig. 6 and 7, after the auxiliary gate is removed, the polysilicon gate 22 remains on the surface of the substrate 21.
And after the auxiliary gate is etched and removed, removing the photoresist on the surface of the substrate.
In step 104, a drift region and a body region are formed within the substrate.
A drift region and a body region are sequentially formed in the substrate by an ion implantation process.
Because the appearance of the side wall of the polysilicon gate is more stable, the concentration of the channel is more stable after self-aligned ion implantation is carried out by taking the polysilicon gate as a mask, and the stability of the threshold voltage of the RFLDMOS device is improved.
In step 105, a drain region is formed in the drift region and a source region is formed in the body region.
And forming a drain region in the drift region and a source region in the body region by an ion implantation process.
In summary, in the RFLDMOS device manufacturing method provided by the embodiment of the present application, a polysilicon layer is formed on a substrate, and the polysilicon layer is etched according to a pattern defined by a first mask to form a polysilicon gate and auxiliary gates, where a plurality of auxiliary gates are arranged between two adjacent polysilicon gates having a distance greater than a predetermined distance; etching and removing the auxiliary gate according to the pattern defined by the second mask, forming a drift region and a body region in the substrate, forming a drain region in the drift region, and forming a source region in the body region; the problem that the shape stability of the side wall of the grid electrode of the RFLDMOS device is not high is solved; the gate sidewall morphology stability of the RFLDMOS device is improved, the channel concentration is guaranteed, and therefore the threshold voltage stability is improved.
Another embodiment of the present application provides a method for manufacturing an RFLDMOS device, which may include the following steps:
in step 201, a gate oxide layer is formed on a substrate.
In step 202, a polysilicon layer is formed on a substrate.
And depositing polycrystalline silicon above the gate oxide layer on the surface of the substrate to form a polycrystalline silicon layer.
In step 203, the polysilicon layer is etched according to the pattern defined by the first mask, and a plurality of auxiliary gates are uniformly arranged between two adjacent polysilicon gates with the distance larger than a predetermined distance.
This step is explained in step 102 above and will not be described here.
A plurality of auxiliary gates are arranged at equal intervals between two adjacent polysilicon gates having an interval greater than a predetermined distance.
In step 204, a photolithography process is performed using a second reticle, and the polysilicon gate is covered with a photoresist.
And (3) coating photoresist on the surface of the substrate in a spinning mode, exposing by using a second mask, and after developing, completely covering the polysilicon gate by the photoresist and not covering the auxiliary gate by the photoresist.
In step 205, the auxiliary gate is removed by an etching process.
And removing the auxiliary gate on the surface of the substrate by an etching process, removing the photoresist, and leaving the polysilicon gate of the RFLDMOS device on the surface of the substrate.
In step 206, a drift region pattern is defined by a photolithography process.
And spin-coating photoresist on the surface of the substrate, exposing through a mask plate, and transferring the drift region pattern into the photoresist on the surface of the substrate after developing.
In step 207, an ion implantation is performed according to the drift region pattern to form a drift region within the substrate.
And after the drift region is formed, removing the photoresist on the surface of the substrate.
In step 208, a body region pattern is defined by a photolithography process, and one side of the polysilicon gate outside the body region pattern is not covered by the photoresist.
In step 209, a body region is formed in the substrate by performing a self-aligned process, followed by a high temperature drive-in.
As shown in fig. 8, in the region defined by the photoresist 81 and forming the body region, a self-aligned process is performed with the polysilicon gate 22 as a mask to perform ion implantation, and high-temperature well driving is performed to form the body region 82 in the substrate and form a channel; and controlling the channel length L according to the reaction condition for controlling the high-temperature drive well.
In step 210, a drain region pattern is defined over the drift region by a photolithography process, and a drain region is formed in the drift region by ion implantation.
In step 211, a source region pattern is defined over the body region by a photolithography process, and a source region is formed in the body region by an ion implantation process.
The execution sequence of step 210 and step 211 may be determined according to actual situations, and is not limited in this embodiment of the application.
In step 212, an interlevel dielectric layer is formed on the substrate.
In step 213, a via is formed in the interlevel dielectric layer.
And forming through holes in the interlayer dielectric layer by photoetching and etching processes, wherein the formed through holes are aligned to the source region, the drain region and the polysilicon gate.
In step 214, the source region, the drain region and the polysilicon gate are led out through the through holes to form a source electrode, a drain electrode and a grid electrode.
And filling the through holes with metal, forming metal electrodes above the interlayer dielectric layer, leading out the source region through the through holes to form a source electrode, leading out the drain region to form a drain electrode, and leading out the polysilicon gate to form a gate.
In the embodiment of the application, as the auxiliary gate is added, the appearance of the side wall of the polysilicon gate after etching is more stable, and when the polysilicon gate is used as a mask for body region ion implantation, the doping concentration of the substrate below the side wall of the polysilicon gate is more stable, so that the stability of the threshold voltage of a device is improved.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.
Claims (8)
1. A manufacturing method of an RFLDMOS device is characterized by comprising the following steps:
forming a polysilicon layer on a substrate;
etching the polysilicon layer according to the pattern defined by the first mask to form a polysilicon gate and auxiliary gates, wherein the auxiliary gates are arranged between two adjacent polysilicon gates with the distance larger than a preset distance;
etching and removing the auxiliary gate according to the pattern defined by the second mask;
forming a drift region and a body region in the substrate;
and forming a drain region in the drift region and forming a source region in the body region.
2. The method of claim 1, wherein a plurality of the auxiliary gates are uniformly arranged between two adjacent polysilicon gates having a spacing greater than a predetermined distance.
3. The method of claim 1, wherein the etching away the auxiliary gate according to the pattern defined by the second mask comprises:
carrying out a photoetching process by using the second mask, wherein the polysilicon gate is covered by photoresist;
and removing the auxiliary gate by an etching process.
4. The method of claim 1 or 2, wherein prior to forming a polysilicon layer on a substrate, the method further comprises:
and forming a gate oxide layer on the substrate.
5. The method of claim 1 or 2, wherein forming a drift region within a substrate comprises:
defining a drift region pattern through a photoetching process;
and carrying out ion implantation according to the drift region pattern, and forming a drift region in the substrate.
6. The method of claim 1 or 2, wherein forming a body region within the substrate comprises:
defining a body region pattern through a photoetching process, wherein one side of the polysilicon gate outside the body region pattern is not covered by a photoresist;
and carrying out body region ion implantation through a self-alignment process, and carrying out high-temperature drive-in to form a body region in the substrate.
7. The method of claim 1 or 2, wherein forming a drain region in the drift region and a source region in the body region comprises:
defining a drain region pattern above the drift region through a photoetching process, and forming a drain region in the drift region through ion implantation;
and defining a source region pattern above the body region through a photoetching process, and forming a source region in the body region through an ion implantation process.
8. The method of claim 1 or 2, wherein after forming a drain region in the drift region and a source region in the body region, the method further comprises:
forming an interlayer dielectric layer on the substrate;
forming a through hole in the interlayer dielectric layer;
and leading out the source region, the drain region and the polysilicon gate through the through hole to form a source electrode, a drain electrode and a grid electrode.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020076867A1 (en) * | 2000-11-24 | 2002-06-20 | Lee Sang Ick | Method of forming a metal gate in a semiconductor device |
| CN102543738A (en) * | 2010-12-20 | 2012-07-04 | 上海华虹Nec电子有限公司 | High-voltage LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and manufacture method for same |
| CN103035717A (en) * | 2012-07-27 | 2013-04-10 | 上海华虹Nec电子有限公司 | Laterally diffused metal oxide semiconductor (LDMOS) component of step-shaped drifting area and manufacturing method thereof |
| CN108666364A (en) * | 2018-04-23 | 2018-10-16 | 上海华虹宏力半导体制造有限公司 | RFLDMOS devices and manufacturing method |
| JP2019046874A (en) * | 2017-08-30 | 2019-03-22 | ルネサスエレクトロニクス株式会社 | Semiconductor device manufacturing method |
-
2020
- 2020-03-24 CN CN202010210606.3A patent/CN111370312B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020076867A1 (en) * | 2000-11-24 | 2002-06-20 | Lee Sang Ick | Method of forming a metal gate in a semiconductor device |
| CN102543738A (en) * | 2010-12-20 | 2012-07-04 | 上海华虹Nec电子有限公司 | High-voltage LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and manufacture method for same |
| CN103035717A (en) * | 2012-07-27 | 2013-04-10 | 上海华虹Nec电子有限公司 | Laterally diffused metal oxide semiconductor (LDMOS) component of step-shaped drifting area and manufacturing method thereof |
| JP2019046874A (en) * | 2017-08-30 | 2019-03-22 | ルネサスエレクトロニクス株式会社 | Semiconductor device manufacturing method |
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