CN112164647B - Method for etching groove - Google Patents
Method for etching groove Download PDFInfo
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- CN112164647B CN112164647B CN202011028815.2A CN202011028815A CN112164647B CN 112164647 B CN112164647 B CN 112164647B CN 202011028815 A CN202011028815 A CN 202011028815A CN 112164647 B CN112164647 B CN 112164647B
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- trench
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- 238000005530 etching Methods 0.000 title claims abstract description 48
- 238000000034 method Methods 0.000 title claims abstract description 35
- 239000000758 substrate Substances 0.000 claims abstract description 65
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 19
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 10
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 9
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 claims description 6
- 238000001039 wet etching Methods 0.000 claims description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 238000001312 dry etching Methods 0.000 claims description 3
- 239000007789 gas Substances 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 2
- 230000000694 effects Effects 0.000 abstract description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 3
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Drying Of Semiconductors (AREA)
Abstract
The application discloses a method for etching a groove, which relates to the field of semiconductor manufacturing and comprises the steps of forming a hard mask layer on a substrate, forming a layer of photoresist on the surface of the hard mask layer, forming a groove opening pattern in the photoresist, wherein the characteristic dimension of the groove opening pattern is smaller than the target characteristic dimension of a groove opening, etching according to the groove opening pattern, forming a groove opening pattern on the hard mask layer, forming a groove with a preset depth on the top of the substrate, increasing the characteristic dimension of the groove opening pattern in the hard mask layer, enabling the characteristic dimension of the groove opening pattern in the hard mask layer to be equal to the target characteristic dimension, etching the substrate according to the increased groove opening pattern, and forming a groove in the substrate; the problem that the top of the side wall of the trench is easy to have a side digging phenomenon after the trench is etched at present is solved; the effect of avoiding the side digging phenomenon at the top of the side wall of the groove and optimizing the groove forming process is achieved.
Description
Technical Field
The application relates to the field of semiconductor manufacturing, in particular to a method for etching a groove.
Background
The trench of the conventional MOS device is formed on the surface of the substrate, and when the MOS device is conducted, source and drain current flows through the trench in a direction parallel to the gate oxide. With the continuous improvement of the requirements on the breakdown voltage and the integration level of the device, the structure of the MOS device is changed, and a power MOSFET appears.
The MOSFET of the groove gate structure changes the channel from horizontal to vertical, eliminates the influence of a plane parasitic JFET, reduces the cell size, increases the current gain and reduces the on-resistance. In fabricating a trench gate MOSFET device, a trench needs to be formed in a substrate. The step of manufacturing the groove comprises the following steps: a hard mask is formed on the surface of the substrate, a groove pattern is defined, and then the substrate is etched to form a groove.
However, during the etching process, due to the high selectivity of silicon to the hard mask, the sidewall of the trench top is prone to undercut (11) phenomenon, as shown in fig. 1, which easily affects the performance of the device.
Disclosure of Invention
In order to solve the problems in the related art, the present application provides a method for trench etching. The technical scheme is as follows:
in one aspect, an embodiment of the present application provides a method for trench etching, where the method includes:
forming a hard mask layer on a substrate;
forming a layer of photoresist on the surface of the hard mask layer;
forming a groove opening pattern in the photoresist layer, wherein the characteristic dimension of the groove opening pattern is smaller than the target characteristic dimension of the groove opening;
etching according to the groove opening pattern, forming a groove opening pattern on the hard mask layer, and forming a groove with a preset depth on the top of the substrate;
increasing the characteristic size of a groove opening pattern in the hard mask layer, and enabling the characteristic size of the groove opening pattern in the hard mask layer to be equal to the target characteristic size of the groove opening;
and etching the substrate according to the enlarged groove opening pattern to form a groove in the substrate.
Optionally, the increasing the feature size of the trench opening pattern in the hard mask layer to make the feature size of the trench opening pattern in the hard mask layer equal to the target feature size of the trench opening includes:
and removing part of silicon oxide on the outer side of the groove opening pattern by a wet etching process, so that the characteristic dimension of the groove opening pattern in the silicon oxide layer is equal to the target characteristic dimension of the groove opening.
Optionally, hydrofluoric acid is used in the wet etching process.
Optionally, the hard mask layer is a silicon oxide layer.
Optionally, the predetermined depth of the groove formed on the top of the substrate is 200A to 800A.
Optionally, the method further includes:
and removing the residual photoresist on the surface of the substrate.
Optionally, the etching the substrate according to the enlarged trench opening pattern to form a trench in the substrate includes:
and etching by using hexafluoromethane and oxygen by taking the hard mask layer containing the enlarged groove opening pattern as a mask to form a groove in the substrate.
Optionally, the etching according to the trench opening pattern to form a trench opening pattern in the hard mask layer, and forming a groove with a predetermined depth on the top of the substrate includes:
performing dry etching according to the groove opening pattern, forming a groove opening pattern on the hard mask layer, and forming a groove with a preset depth on the top of the substrate;
wherein, the gas used for etching is tetrafluoromethane and/or trifluoromethane.
The technical scheme at least comprises the following advantages:
forming a hard mask layer on a substrate, forming a layer of photoresist on the surface of the hard mask layer, forming a groove opening pattern in the photoresist, wherein the characteristic dimension of the groove opening pattern is smaller than the target characteristic dimension of a groove opening, etching according to the groove opening pattern, forming the groove opening pattern on the hard mask layer, forming a groove with a preset depth at the top of the substrate, increasing the characteristic dimension of the groove opening pattern in the hard mask layer, enabling the characteristic dimension of the groove opening pattern in the hard mask layer to be equal to the target characteristic dimension of the groove opening, etching the substrate according to the increased groove opening pattern, and forming a groove in the substrate; the problem that the top of the side wall of the groove is easy to have a side digging phenomenon after the groove is etched at present is solved; the effect of avoiding the side digging phenomenon at the top of the side wall of the groove and optimizing the groove forming process is achieved.
Drawings
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a SEM cross-sectional view of a conventional trench;
FIG. 2 is a flowchart of a trench etching method according to an embodiment of the present disclosure;
FIG. 3 is a schematic diagram illustrating an embodiment of a trench etching method according to an embodiment of the present disclosure;
FIG. 4 is a schematic diagram illustrating an embodiment of a trench etching method according to an embodiment of the present disclosure;
FIG. 5 is a schematic diagram illustrating an embodiment of a trench etching method according to an embodiment of the present disclosure;
fig. 6 is a schematic implementation diagram of a trench etching method according to an embodiment of the present application.
Detailed Description
The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it should be noted that, unless otherwise explicitly stated or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, a fixed connection, a detachable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.
Referring to fig. 2, a flowchart of a trench etching method provided in an embodiment of the present application is shown, where the method at least includes the following steps:
And 102, forming a layer of photoresist on the surface of the hard mask layer.
And exposing the photoresist layer by using a mask plate comprising the groove opening pattern, and forming the groove opening pattern on the photoresist layer after developing.
A trench opening refers to a trench opening on a substrate.
As shown in fig. 3, a hard mask layer 32 is formed on the surface of the substrate 31, a photoresist layer 33 is formed on the hard mask layer 31, and a trench opening pattern 34 is formed in the photoresist layer 33.
The target feature size of the trench opening is predetermined and determined as the case may be.
And 104, etching according to the groove opening pattern, forming the groove opening pattern on the hard mask layer, and forming a groove with a preset depth on the top of the substrate.
And etching the hard mask layer, continuously etching part of the substrate downwards after the etching of the hard mask layer is finished, and stopping etching when a groove with a preset depth is formed at the top of the substrate.
The depth of the substrate top groove is related to the depth of the undercut phenomenon in the existing product, and the depth of the substrate top groove is determined in advance according to actual conditions.
At this time, the opening size of the recess formed on top of the substrate is smaller than the target feature size of the trench.
After etching, hard mask layer 32 is patterned with trench openings, and the top of the substrate is also patterned with a recess, as shown in fig. 4.
And 105, increasing the characteristic size of the groove opening pattern in the hard mask layer, and enabling the characteristic size of the groove opening pattern in the hard mask layer to be equal to the target characteristic size of the groove opening.
Because the feature size of the trench opening pattern in the hard mask layer in step 104 is smaller than the target feature size of the trench, if the trench opening pattern in the hard mask layer is not enlarged, the opening of the subsequently formed trench will not meet the predetermined requirement, and therefore, a portion of the hard mask layer on both sides of the trench opening pattern in the hard mask layer is removed, so that the feature size of the trench opening pattern in the hard mask layer is equal to the target feature size of the trench opening.
Because the opening pattern of the groove in the hard mask layer is increased, the hard mask is reduced, the opening size of the groove at the top of the substrate is not changed, and a part of the substrate is exposed below the opening pattern of the groove.
As shown in fig. 5, the feature size of the trench opening pattern 34 in the hard mask layer 32 increases, and the hard mask 32 on both sides of the trench opening pattern becomes smaller as compared with fig. 4, and a portion of the substrate under the hard mask 32 is exposed.
And 106, etching the substrate according to the enlarged groove opening pattern to form a groove in the substrate.
Etching the substrate 31 by using an etching process to form a trench 35 in the substrate 31, as shown in fig. 6; the opening size of the trench 35 is the same as the size of the enlarged trench opening pattern, that is, the opening size of the trench 35 is the target feature size, and the sidewall of the trench 35 has no undercut (side undercut).
To sum up, in the trench etching method provided in the embodiment of the present application, a hard mask layer is formed on a substrate, a layer of photoresist is formed on the surface of the hard mask layer, a trench opening pattern is formed in the photoresist, the characteristic dimension of the trench opening pattern is smaller than the target characteristic dimension of the trench opening, etching is performed according to the trench opening pattern, the hard mask layer forms the trench opening pattern, a groove with a predetermined depth is formed at the top of the substrate, the characteristic dimension of the trench opening pattern in the hard mask layer is increased, the characteristic dimension of the trench opening pattern in the hard mask layer is made equal to the target characteristic dimension of the trench opening, the substrate is etched according to the increased trench opening pattern, and a trench is formed in the substrate; because partial substrate material is reserved on the top of the trench in the substrate before normal trench etching is carried out, the reserved substrate material on the top of the trench can be removed by side digging when the normal trench etching is carried out, so that the size of an opening of the formed trench reaches a target characteristic size, and the problem that the side digging phenomenon is easy to occur on the top of the side wall of the trench after the current trench etching is solved; the effect of avoiding the side digging phenomenon at the top of the side wall of the groove and optimizing the groove forming process is achieved.
In an alternative embodiment based on the embodiment shown in fig. 2, the hard mask layer is a silicon oxide layer.
and removing part of the silicon oxide outside the groove opening pattern by a wet etching process, so that the characteristic dimension of the groove opening pattern in the silicon oxide layer is equal to the target characteristic dimension of the groove opening.
Optionally, the chemical solution used in the wet etching process is hydrofluoric acid (HF), and the hydrofluoric acid is used to remove a portion of silicon oxide outside the trench opening pattern.
In an alternative embodiment based on the embodiment shown in fig. 2, the predetermined depth of the recess formed in the top of the substrate is 200A-800A. For example, the predetermined depth of the groove formed on the top of the substrate is 500A.
In an alternative embodiment based on the embodiment shown in fig. 2, before step 105, the method further comprises: and removing the residual photoresist on the surface of the substrate.
In an alternative embodiment based on the embodiment shown in fig. 2, the step 106, that is, the step of "etching the substrate according to the enlarged trench opening pattern to form the trench in the substrate", may be implemented as follows:
and etching by using hexafluoromethane and oxygen by taking the hard mask layer containing the enlarged groove opening pattern as a mask to form a groove in the substrate.
In an alternative embodiment based on the embodiment shown in fig. 2, the step 104, that is, the step "etching according to the trench opening pattern, forming the trench opening pattern on the hard mask layer, and forming the recess with a predetermined depth on the top of the substrate", may be implemented as follows:
performing dry etching according to the groove opening pattern, forming a groove opening pattern on the hard mask layer, and forming a groove with a preset depth on the top of the substrate; wherein, the gas used for etching is tetrafluoromethane and/or trifluoromethane.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.
Claims (6)
1. A method for etching a trench, the method comprising:
forming a hard mask layer on a substrate;
forming a layer of photoresist on the surface of the hard mask layer;
forming a trench opening pattern in the photoresist layer, wherein the characteristic dimension of the trench opening pattern is smaller than the target characteristic dimension of the trench opening;
etching according to the groove opening pattern, forming a groove opening pattern on the hard mask layer, and forming a groove with a preset depth on the top of the substrate;
increasing the characteristic size of a groove opening pattern in the hard mask layer, and enabling the characteristic size of the groove opening pattern in the hard mask layer to be equal to the target characteristic size of the groove opening;
etching the substrate according to the enlarged groove opening pattern to form a groove in the substrate; wherein the predetermined depth of the recess is less than the depth of the trench, the predetermined depth of the recess being 200A-800A.
2. The method of claim 1, wherein the hard mask layer is a silicon oxide layer, and the increasing a feature size of a trench opening pattern in the hard mask layer to make the feature size of the trench opening pattern in the hard mask layer equal to a target feature size of the trench opening comprises:
and removing part of the silicon oxide layer outside the groove opening pattern by a wet etching process, so that the characteristic dimension of the groove opening pattern in the silicon oxide layer is equal to the target characteristic dimension of the groove opening.
3. The method of claim 2, wherein the chemical solution used in the wet etching process is hydrofluoric acid.
4. The method of claim 1, further comprising:
and removing the residual photoresist on the surface of the substrate.
5. The method of claim 1, wherein etching the substrate according to the enlarged trench opening pattern to form a trench in the substrate comprises:
and etching by using hexafluoromethane and oxygen by taking the hard mask layer containing the enlarged groove opening pattern as a mask to form a groove in the substrate.
6. The method of claim 1, wherein the etching according to the trench opening pattern, forming a trench opening pattern in the hard mask layer, and forming a recess with a predetermined depth on top of the substrate comprises:
performing dry etching according to the groove opening pattern, forming a groove opening pattern on the hard mask layer, and forming a groove with a preset depth on the top of the substrate;
wherein, the gas used for etching is tetrafluoromethane and/or trifluoromethane.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202011028815.2A CN112164647B (en) | 2020-09-25 | 2020-09-25 | Method for etching groove |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011028815.2A CN112164647B (en) | 2020-09-25 | 2020-09-25 | Method for etching groove |
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| CN112164647B true CN112164647B (en) | 2022-12-27 |
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| CN114171605B (en) * | 2021-12-03 | 2024-08-30 | 杭州赛晶电子有限公司 | Manufacturing method of P-type impurity diffusion junction shielding grid silicon diode |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105493255A (en) * | 2013-08-27 | 2016-04-13 | 东京毅力科创株式会社 | Method for laterally trimming a hardmask |
| CN106783727A (en) * | 2015-11-23 | 2017-05-31 | 中芯国际集成电路制造(上海)有限公司 | The forming method of interconnection structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105493255A (en) * | 2013-08-27 | 2016-04-13 | 东京毅力科创株式会社 | Method for laterally trimming a hardmask |
| CN106783727A (en) * | 2015-11-23 | 2017-05-31 | 中芯国际集成电路制造(上海)有限公司 | The forming method of interconnection structure |
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