CN111370312B - Manufacturing method of RFLDMOS device - Google Patents
Manufacturing method of RFLDMOS device Download PDFInfo
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- CN111370312B CN111370312B CN202010210606.3A CN202010210606A CN111370312B CN 111370312 B CN111370312 B CN 111370312B CN 202010210606 A CN202010210606 A CN 202010210606A CN 111370312 B CN111370312 B CN 111370312B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 25
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 93
- 229920005591 polysilicon Polymers 0.000 claims abstract description 93
- 239000000758 substrate Substances 0.000 claims abstract description 51
- 238000000034 method Methods 0.000 claims abstract description 49
- 210000000746 body region Anatomy 0.000 claims abstract description 40
- 238000005530 etching Methods 0.000 claims abstract description 22
- 239000010410 layer Substances 0.000 claims description 32
- 229920002120 photoresistant polymer Polymers 0.000 claims description 24
- 238000005468 ion implantation Methods 0.000 claims description 18
- 239000011229 interlayer Substances 0.000 claims description 8
- 238000001259 photo etching Methods 0.000 claims description 7
- 238000000206 photolithography Methods 0.000 claims description 7
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 5
- 238000009826 distribution Methods 0.000 description 4
- 238000002955 isolation Methods 0.000 description 3
- 239000002184 metal Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 1
- 238000009987 spinning Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
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- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The application discloses a manufacturing method of an RFLDMOS device, and relates to the field of semiconductor manufacturing. The method includes forming a polysilicon layer on a substrate; etching the polysilicon layer according to the pattern defined by the first mask plate to form a polysilicon gate and auxiliary gates, wherein a plurality of auxiliary gates are arranged between two adjacent polysilicon gates with a distance larger than a preset distance; etching to remove the auxiliary gate according to the pattern defined by the second mask; forming a drift region and a body region in a substrate; forming a drain region in the drift region and a source region in the body region; the problem of low stability of the morphology of the grid side wall of the RFLDMOS device is solved; the stability of the side wall morphology of the grid electrode of the RFLDMOS device is improved, the channel concentration is guaranteed, and the threshold voltage stability is improved.
Description
Technical Field
The application relates to the field of semiconductor manufacturing, in particular to a manufacturing method of an RFLDMOS device.
Background
RFLDMOS (Radio Frequency Lateral Double-diffused MOSFET) has the advantages of high working frequency, high voltage resistance, high output power, high gain, high linearity and the like, and is widely applied to mobile transmitting base stations, broadcast television transmitting base stations, broadband frequency modulation transmitters, airborne transponders, radar systems and the like.
The threshold voltage is one of the main parameters of the RFLDMOS device, and represents the minimum gate-source voltage when the channel region surface reaches inversion and has a certain current flowing. In order for the device to achieve optimal performance, the threshold voltage of the actual product needs to be stable within the designed voltage range.
The gate morphology has an important influence on the threshold voltage, and in the manufacturing process of the RFLDMOS device, polysilicon gate is formed by etching polysilicon, and if the etched gate morphology is unstable, the threshold voltage of the device is influenced, so that the performance of the device is influenced.
Disclosure of Invention
In order to solve the problems in the related art, the application provides a manufacturing method of an RFLDMOS device. The technical scheme is as follows:
in one aspect, an embodiment of the present application provides a method for manufacturing an RFLDMOS device, where the method includes:
forming a polysilicon layer on a substrate;
etching the polysilicon layer according to the pattern defined by the first mask plate to form a polysilicon gate and auxiliary gates, wherein a plurality of auxiliary gates are arranged between two adjacent polysilicon gates with a distance larger than a preset distance;
etching to remove the auxiliary gate according to the pattern defined by the second mask;
forming a drift region and a body region in a substrate;
a drain region is formed in the drift region, and a source region is formed in the body region.
Optionally, the plurality of auxiliary gates are uniformly arranged between two adjacent polysilicon gates having a pitch greater than a predetermined distance.
Optionally, removing the auxiliary gate according to the pattern defined by the second mask includes:
carrying out a photoetching process by utilizing a second mask, wherein the polysilicon gate is covered by photoresist;
and removing the auxiliary gate through an etching process.
Optionally, before forming the polysilicon layer on the substrate, the method further comprises:
a gate oxide layer is formed on a substrate.
Optionally, forming a drift region in the substrate includes:
defining a drift region pattern by a photolithography process;
ion implantation is performed according to the drift region pattern to form a drift region within the substrate.
Optionally, forming a body region in the substrate includes:
defining a body region pattern through a photoetching process, wherein one side of a polysilicon gate outside the body region pattern is not covered by a photoresist;
and performing body region ion implantation through a self-alignment process, and performing high-temperature push-well to form a body region in the substrate.
Optionally, forming a drain region in the drift region and a source region in the body region, including:
defining a drain region pattern above the drift region through a photoetching process, and forming a drain region in the drift region through ion implantation;
a source region pattern is defined over the body region by a photolithography process, and a source region is formed in the body region by an ion implantation process.
Optionally, forming a drain region in the drift region, and after forming a source region in the body region, the method further comprises:
forming an interlayer dielectric layer on a substrate;
forming a through hole in the interlayer dielectric layer;
and leading out the source region, the drain region and the polysilicon gate through the through holes to form a source electrode, a drain electrode and a grid electrode.
The technical scheme of the application at least comprises the following advantages:
forming a polysilicon layer on a substrate, etching the polysilicon layer according to a pattern defined by a first mask plate to form a polysilicon gate and auxiliary gates, wherein a plurality of auxiliary gates are arranged between two adjacent polysilicon gates with a distance larger than a preset distance; etching and removing the auxiliary gate according to the pattern defined by the second mask, forming a drift region and a body region in the substrate, forming a drain region in the drift region, and forming a source region in the body region; the problem of low stability of the morphology of the grid side wall of the RFLDMOS device is solved; the stability of the side wall morphology of the grid electrode of the RFLDMOS device is improved, and the channel concentration is guaranteed, so that the threshold voltage stability is improved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of a method for manufacturing an RFLDMOS device according to an embodiment of the present application;
fig. 2 is a partial cross-sectional view of an RFLDMOS device provided in an embodiment of the present application during fabrication;
fig. 3 is a schematic diagram of a positional relationship between an auxiliary gate and a polysilicon gate in a manufacturing process of the RFLDMOS device provided in the embodiment of the application;
fig. 4 is a partial cross-sectional view of an RFLDMOS device provided in an embodiment of the present application during fabrication;
fig. 5 is a schematic diagram of a positional relationship among an auxiliary gate, a polysilicon gate, and a photoresist in a manufacturing process of the RFLDMOS device provided in the embodiment of the application;
fig. 6 is a partial cross-sectional view of an RFLDMOS device provided in an embodiment of the present application during fabrication;
fig. 7 is a schematic diagram of a polysilicon gate in the manufacturing process of the RFLDMOS device provided in the embodiment of the application;
fig. 8 is a cross-sectional view of an RFLDMOS device provided in an embodiment of the application during fabrication.
Detailed Description
The following description of the embodiments of the present application will be made apparent and complete in conjunction with the accompanying drawings, in which embodiments described are some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.
In the description of the present application, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of description of the present application and to simplify the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; the two components can be directly connected or indirectly connected through an intermediate medium, or can be communicated inside the two components, or can be connected wirelessly or in a wired way. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art in a specific context.
In addition, the technical features described below in the different embodiments of the present application may be combined with each other as long as they do not collide with each other.
When the RFLDMOS device is manufactured, a polysilicon layer is deposited, then a polysilicon gate is formed by etching, then ion implantation is carried out by taking the polysilicon as a mask in a self-alignment mode, and a proper high-temperature push-well is carried out to form a channel.
Because a plurality of RFLDMOS devices can be manufactured on the same substrate, due to the drift region and the body region of the LDMOS devices, the situation that the distance between two adjacent polysilicon gates is large can occur in the polysilicon gate pattern defined by the mask, and the polysilicon gates can be regarded as isolation distribution under the situation. Due to the inherent characteristics of the etching process, after the polysilicon layer is etched according to the polysilicon gate pattern, the sidewall morphology of the polysilicon gate in isolation distribution is unstable, the doping concentration of the substrate below the sidewall of the polysilicon gate can be influenced, the channel concentration is influenced, and the threshold voltage of the RFLDMOS device is further influenced.
Referring to fig. 1, a flowchart of a method for manufacturing an RFLDMOS device according to an embodiment of the present application is shown. As shown in fig. 1, the manufacturing method of the RFLDMOS device at least includes the following steps:
in step 101, a polysilicon layer is formed on a substrate.
A substrate is provided, and polysilicon is deposited on the substrate to form a polysilicon layer.
In step 102, the polysilicon layer is etched according to the pattern defined by the first mask plate to form a polysilicon gate and auxiliary gates, and a plurality of auxiliary gates are arranged between two adjacent polysilicon gates with a distance greater than a predetermined distance.
The first mask plate comprises a polysilicon gate pattern and an auxiliary gate pattern.
And spin-coating photoresist above the polysilicon layer, exposing by using a first mask, and transferring the polysilicon pattern and the auxiliary gate pattern on the first mask to the photoresist on the surface of the substrate through development.
And etching the polysilicon layer according to the polysilicon pattern and the auxiliary gate pattern by an etching process to obtain a plurality of polysilicon gates and a plurality of auxiliary gates.
The number of the polysilicon gates and the number of the auxiliary gates are determined according to practical situations.
Among the formed polysilicon gates, there are cases where the distance between two adjacent polysilicon gates is smaller than a predetermined distance, and the distance between two adjacent polysilicon gates is larger than a predetermined distance. A plurality of auxiliary gates are arranged between two adjacent polysilicon gates with a distance greater than a predetermined distance.
The predetermined distance is predetermined according to the actual situation.
The number of the auxiliary gates arranged between two adjacent polysilicon gates with a pitch greater than a predetermined distance is determined according to practical situations, which is not limited in the embodiment of the present application.
As shown in fig. 2, a plurality of polysilicon gates 22 and a plurality of auxiliary gates 23 are formed on a substrate 21, and a plurality of auxiliary gates 23 are arranged between two adjacent polysilicon gates 22 having a pitch greater than a predetermined distance.
Fig. 3 schematically illustrates a positional relationship between an auxiliary gate and a polysilicon gate in the RFLDMOS device manufacturing process.
By adding an auxiliary gate between two adjacent polysilicon gates with the distance larger than the preset distance, the polysilicon gates in isolation distribution are changed into density distribution, and the stability of the polysilicon gate sidewall morphology after etching is improved.
In step 103, the auxiliary gate is etched and removed according to the pattern defined by the second mask.
And completely removing the auxiliary gate on the substrate and reserving the polysilicon gate.
Photoresist is spun on the substrate, exposure is performed by using a second mask, and after development, the polysilicon gate 22 is covered by the photoresist 24, and the auxiliary gate 23 is not covered by the photoresist, as shown in fig. 4.
Fig. 5 is a schematic diagram schematically showing the positional relationship of the auxiliary gate, the polysilicon gate and the photoresist in the RFLDMOS device manufacturing process, in which the auxiliary gate 23 is not covered by the photoresist and the polysilicon gate 22 is covered by the photoresist 24 in fig. 5.
As shown in fig. 6 and 7, after the auxiliary gate is removed, the polysilicon gate 22 remains on the surface of the substrate 21.
And removing the photoresist on the surface of the substrate after the auxiliary gate is etched and removed.
In step 104, a drift region and a body region are formed within the substrate.
A drift region and a body region are sequentially formed in the substrate by an ion implantation process.
Because the appearance of the side wall of the polysilicon gate is more stable, after self-aligned ion implantation is carried out by taking the polysilicon gate as a mask, the channel concentration is more stable, and the stability of the threshold voltage of the RFLDMOS device is improved.
In step 105, a drain region is formed in the drift region and a source region is formed in the body region.
And forming a drain region in the drift region and a source region in the body region by an ion implantation process.
In summary, in the method for manufacturing the RFLDMOS device provided in the embodiment of the present application, a polysilicon layer is formed on a substrate, and the polysilicon layer is etched according to a pattern defined by a first mask, so as to form a polysilicon gate and an auxiliary gate, where a plurality of auxiliary gates are arranged between two adjacent polysilicon gates with a distance greater than a predetermined distance; etching and removing the auxiliary gate according to the pattern defined by the second mask, forming a drift region and a body region in the substrate, forming a drain region in the drift region, and forming a source region in the body region; the problem of low stability of the morphology of the grid side wall of the RFLDMOS device is solved; the stability of the side wall morphology of the grid electrode of the RFLDMOS device is improved, and the channel concentration is guaranteed, so that the threshold voltage stability is improved.
Another embodiment of the present application provides a method for manufacturing an RFLDMOS device, where the method for manufacturing an RFLDMOS device may include the following steps:
in step 201, a gate oxide layer is formed on a substrate.
In step 202, a polysilicon layer is formed on a substrate.
And depositing polysilicon above the gate oxide layer on the surface of the substrate to form a polysilicon layer.
In step 203, the polysilicon layer is etched according to the pattern defined by the first reticle, and the plurality of auxiliary gates are uniformly arranged between two adjacent polysilicon gates having a pitch greater than a predetermined distance.
This step is described in step 102, and will not be described here again.
The auxiliary gates are arranged at equal intervals between two adjacent polysilicon gates with a distance larger than a predetermined distance.
In step 204, a photolithography process is performed using a second reticle, the polysilicon gate being covered with photoresist.
Photoresist is coated on the surface of the substrate in a spinning mode, exposure is conducted through a second mask, after development, all the polysilicon gate is covered by the photoresist, and the auxiliary gate is not covered by the photoresist.
In step 205, the auxiliary gate is removed by an etching process.
And removing the auxiliary gate on the surface of the substrate through an etching process, and removing the photoresist, so that the polysilicon gate of the RFLDMOS device is left on the surface of the substrate.
In step 206, a drift region pattern is defined by a photolithographic process.
Spin-coating photoresist on the surface of the substrate, exposing through a mask plate, and transferring the developed drift region pattern into the photoresist on the surface of the substrate.
In step 207, ion implantation is performed according to the drift region pattern, forming a drift region within the substrate.
After forming the drift region, photoresist on the surface of the substrate is removed.
In step 208, a body pattern is defined by a photolithography process, with one side of the polysilicon gate outside the body pattern not covered by photoresist.
In step 209, body region ion implantation is performed by a self-aligned process, and a high temperature push well is performed to form a body region within the substrate.
As shown in fig. 8, in the region where the body region is formed defined by the photoresist 81, a self-aligned process is performed by using the polysilicon gate 22 as a mask to perform ion implantation, and a high-temperature push-well is performed to form a body region 82 in the substrate and form a channel; and controlling the channel length L according to the reaction conditions of the high-temperature push well.
In step 210, a drain region pattern is defined over the drift region by a photolithographic process, and a drain region is formed within the drift region by ion implantation.
In step 211, a source region pattern is defined over the body region by a photolithography process, and a source region is formed in the body region by an ion implantation process.
The execution sequence of step 210 and step 211 may be determined according to practical situations, which is not limited in the embodiments of the present application.
In step 212, an interlayer dielectric layer is formed on the substrate.
In step 213, a via is formed in the interlayer dielectric layer.
And forming a through hole in the interlayer dielectric layer through photoetching and etching processes, wherein the formed through hole is aligned to the source region, the drain region and the polysilicon gate.
In step 214, the source region, the drain region, and the polysilicon gate are led out through the through holes to form a source, a drain, and a gate.
Filling the through hole with metal, forming a metal electrode above the interlayer dielectric layer, leading out the source region through the through hole to form a source electrode, leading out the drain region to form a drain electrode, and leading out the polysilicon gate to form a gate electrode.
In the embodiment of the application, due to the fact that the auxiliary gate is added, the shape of the side wall of the polysilicon gate after etching is more stable, and when the polysilicon gate is used as a mask for body region ion implantation, the doping concentration of the substrate below the side wall of the polysilicon gate is also more stable, so that the stability of the threshold voltage of the device is improved.
It is apparent that the above examples are given by way of illustration only and are not limiting of the embodiments. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. While nevertheless, obvious variations or modifications may be made to the embodiments described herein without departing from the scope of the invention.
Claims (8)
1. The manufacturing method of the RFLDMOS device is characterized by comprising the following steps:
forming a polysilicon layer on a substrate;
etching the polysilicon layer according to the pattern defined by the first mask plate to form a polysilicon gate and auxiliary gates, wherein a plurality of auxiliary gates are arranged between two adjacent polysilicon gates with a distance larger than a preset distance;
etching and removing the auxiliary gate according to the pattern defined by the second mask;
forming a drift region and a body region in the substrate;
and forming a drain region in the drift region and forming a source region in the body region.
2. The method of claim 1 wherein a plurality of said auxiliary gates are uniformly arranged between two adjacent polysilicon gates having a pitch greater than a predetermined distance.
3. The method of claim 1, wherein the etching the auxiliary gate according to the pattern defined by the second reticle comprises:
carrying out a photoetching process by utilizing the second mask, wherein the polysilicon gate is covered by photoresist;
and removing the auxiliary gate through an etching process.
4. The method of claim 1 or 2, wherein prior to forming the polysilicon layer on the substrate, the method further comprises:
a gate oxide layer is formed on the substrate.
5. The method of claim 1 or 2, wherein forming a drift region within the substrate comprises:
defining a drift region pattern by a photolithography process;
and performing ion implantation according to the drift region pattern to form a drift region in the substrate.
6. The method of claim 1 or 2, wherein forming a body region within the substrate comprises:
defining a body region pattern through a photoetching process, wherein one side of a polysilicon gate outside the body region pattern is not covered by a photoresist;
and performing body region ion implantation through a self-alignment process, performing high-temperature push-well, and forming a body region in the substrate.
7. The method of claim 1 or 2, wherein forming a drain region within the drift region and a source region within the body region comprises:
defining a drain region pattern above the drift region through a photoetching process, and forming a drain region in the drift region through ion implantation;
a source region pattern is defined over the body region by a photolithography process, and a source region is formed within the body region by an ion implantation process.
8. The method of claim 1 or 2, wherein the forming a drain region within the drift region, after forming a source region within the body region, further comprises:
forming an interlayer dielectric layer on the substrate;
forming a through hole in the interlayer dielectric layer;
and leading out the source region, the drain region and the polysilicon gate through the through holes to form a source electrode, a drain electrode and a grid electrode.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102543738A (en) * | 2010-12-20 | 2012-07-04 | 上海华虹Nec电子有限公司 | High-voltage LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and manufacture method for same |
| CN103035717A (en) * | 2012-07-27 | 2013-04-10 | 上海华虹Nec电子有限公司 | Laterally diffused metal oxide semiconductor (LDMOS) component of step-shaped drifting area and manufacturing method thereof |
| CN108666364A (en) * | 2018-04-23 | 2018-10-16 | 上海华虹宏力半导体制造有限公司 | RFLDMOS devices and manufacturing method |
| JP2019046874A (en) * | 2017-08-30 | 2019-03-22 | ルネサスエレクトロニクス株式会社 | Semiconductor device manufacturing method |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100353539B1 (en) * | 2000-11-24 | 2002-09-27 | 주식회사 하이닉스반도체 | Method for manufacturing gate in semiconductor device |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102543738A (en) * | 2010-12-20 | 2012-07-04 | 上海华虹Nec电子有限公司 | High-voltage LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and manufacture method for same |
| CN103035717A (en) * | 2012-07-27 | 2013-04-10 | 上海华虹Nec电子有限公司 | Laterally diffused metal oxide semiconductor (LDMOS) component of step-shaped drifting area and manufacturing method thereof |
| JP2019046874A (en) * | 2017-08-30 | 2019-03-22 | ルネサスエレクトロニクス株式会社 | Semiconductor device manufacturing method |
| CN108666364A (en) * | 2018-04-23 | 2018-10-16 | 上海华虹宏力半导体制造有限公司 | RFLDMOS devices and manufacturing method |
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