CN114188404A - Source end process method of LDMOS device - Google Patents

Source end process method of LDMOS device Download PDF

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Publication number
CN114188404A
CN114188404A CN202111440107.4A CN202111440107A CN114188404A CN 114188404 A CN114188404 A CN 114188404A CN 202111440107 A CN202111440107 A CN 202111440107A CN 114188404 A CN114188404 A CN 114188404A
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China
Prior art keywords
window
source
photoresist
implantation
ldmos device
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CN202111440107.4A
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Chinese (zh)
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王星杰
杨新杰
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Priority to CN202111440107.4A priority Critical patent/CN114188404A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0856—Source regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The invention discloses a source end process method of an LDMOS device, which comprises the steps of coating photoresist on the surface of a substrate or an epitaxy, opening the photoresist at the source end of the LDMOS device to form an injection window of the source end, carrying out first-time ion injection on the source end, and forming a source region in the substrate or the epitaxy; then, partially removing the photoresist of the source region to form a new source end injection window, and redefining the source region and the channel; etching the polysilicon layer in the window under the definition of the reformed source region window, removing the polysilicon layer in the window and exposing the silicon oxide layer below the polysilicon layer; and carrying out second doping ion implantation in the source region window. After high-energy injection, the LDMOS channel is redefined by dry etching a small amount of photoresist and polysilicon etching again so as to reduce the influence of the high-energy injection on the LDMOS channel.

Description

Source end process method of LDMOS device
Technical Field
The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a source end process method of an LDMOS device integrated in a BCD process.
Background
DMOS (Double-diffused MOS) has the characteristics of high voltage resistance, high current driving capability, extremely low power consumption and the likeThe method is widely applied to power management chips at present. In an LDMOS (Lateral Double-diffused MOSFET) device, on-resistance is an important index. In the BCD (Bipolar-CMOS-DMOS) process, LDMOS is integrated with CMOS in the same chip, but has high breakdown voltage BV (Breakdown Voltage) and low characteristic on-resistance RSPThe contradiction/compromise exists between the Specific on-Resistance, and the requirements of the application of the switch tube cannot be met. The high-voltage LDMOS has the characteristics of high voltage and high current of discrete devices, also absorbs the advantage of high-density intelligent logic control of a low-voltage integrated circuit, realizes the functions which can be completed by a plurality of chips originally by a single chip, greatly reduces the area, reduces the cost, improves the energy efficiency, and accords with the development direction of miniaturization, intellectualization and low energy consumption of modern power electronic devices. Breakdown voltage and on-resistance are key parameters for measuring the high-voltage LDMOS device. Therefore, R should be reduced as much as possible to obtain the same breakdown voltageSPTo improve the competitiveness of the product.
In the existing LDMOS structure, as shown in fig. 1, taking the most common NLDMOS device as an example, 101 in the figure is a P-type substrate or a P-type epitaxy, 103 is a gate dielectric layer, 104 is a polysilicon gate, 105 is a drift region and RESURF layer implantation, 107 is a P-type body region implantation, 108 is a gate sidewall, 109 is a heavily doped N-type region (source region, drain region), and 110 is a heavily doped P-type region.
After the BCD process enters a 0.18um node, in order to reduce the source-drain on-resistance Rdson sp of the LDMOS, a shorter channel is formed through the source end engineering of the LDMOS so as to achieve the purpose of further reducing the Rdson sp. Meanwhile, the requirements of longitudinal voltage resistance and a safe working area are comprehensively considered, multi-step high-energy injection is used, in order to play a blocking role, photoresist with the thickness of more than 1um is used, the appearance of the photoresist is not good at the moment, the side appearance of the photoresist is inclined and not vertical, as shown in fig. 2, a doping source for high-energy injection penetrates through the inclined photoresist blocking area to enter a channel of the LDMOS, and the threshold voltage Vt and the Rdson of the LDMOS are influenced.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a source end process method of an LDMOS device, which has more excellent threshold voltage performance and characteristic on-resistance performance.
In order to solve the problems, the source end process method of the LDMOS device, provided by the invention, comprises the steps of coating photoresist on the surface of a substrate or an epitaxy, opening the photoresist at the source end of the LDMOS device to form an injection window of the source end, carrying out first-time ion injection on the source end, and forming a source region in the substrate or the epitaxy;
then, photoresist stripping is carried out on the source region photoresist again to form a new source end injection window, and a source region and a channel are redefined;
etching the polysilicon layer in the window under the definition of the reformed source region window, removing the polysilicon layer in the window and exposing the silicon oxide layer below the polysilicon layer;
and carrying out second low-energy doping ion implantation in the source region window.
The further improvement is that in the step one, the thickness of the coated photoresist is not less than 1um, the photoresist is opened after photoetching to form a window, and the side wall of the photoresist in the window is in an inclined state.
In a further improvement, in the first step, the first ion implantation is high-energy ion implantation; the implantation is formed by one-step implantation or multi-step implantation.
In the first step, after the first ion implantation, high-energy ions pass through the photoresist sidewall in the inclined window, and besides forming the source region in the substrate or epitaxy, a doped source implantation region is additionally formed at the edge of the source region, and the implantation depth is smaller than that of the source region.
The further improvement is that the photoresist in the source region is partially removed, and the photoresist in the window region is etched by adopting dry etching, so that the window region is further enlarged.
The further improvement is that after the window area is enlarged, the doping source injection area with 50-100% area is also in the range of opening the window.
The further improvement is that the second low-energy doping ion implantation is completed by one implantation or multiple step implantations.
In a further improvement, the first high-energy implantation has an implantation energy of 50 Kev-2500 Kev.
In a further improvement, the second low energy implantation has an implantation energy of 1Kev to 500 Kev.
After high-energy injection, the LDMOS channel is redefined by dry etching a small amount of photoresist and polysilicon etching again so as to reduce the influence of the high-energy injection on the LDMOS channel.
Drawings
Fig. 1 is a cross-sectional view of a conventional LDMOS device.
Fig. 2 is a schematic diagram of the present invention first performing high-energy ion implantation.
Fig. 3 is a schematic diagram of a modified etching of a source photoresist according to the present invention.
Fig. 4 is a schematic diagram of etching a polysilicon layer in a source photoresist window according to the present invention.
Fig. 5 is a schematic diagram of the present invention for low energy ion implantation at the source end.
FIG. 6 is a process flow diagram of the present invention.
Description of the reference numerals
101 is a substrate or epitaxy, 103 is an oxide layer, 104 is a polysilicon layer, and 502 is photoresist.
Detailed Description
The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
The invention relates to a source terminal process method of an LDMOS device, which aims at solving the problem that high-energy ions penetrate through an inclined photoresist side wall to form an additional doped injection region in a substrate when the ions of a source terminal are injected to generate adverse influence on a device channel. Due to the high-energy ion implantation, the implantation energy is 50 Kev-2500 Kev, the thickness of the coated photoresist is not less than 1um, the photoresist is opened after photoetching to form a window, and the side wall of the photoresist in the window is in an inclined state. Therefore, in the inclined state, the high-energy ions can penetrate through the photoresist with the relatively thin thickness at the lower part, so that in addition to forming the source region, an additional doping source implantation region can be formed at a shallower position in the substrate, wherein the implantation depth is smaller than that of the source region.
And then, carrying out dry etching on the photoresist of the source region to remove a small amount of photoresist, further enlarging a source end injection window, forming a new source end injection window, exposing most or all of the doped source injection regions within the range of opening the window, wherein the area of the doped source injection regions is generally 50-100%, and redefining the source region and the channel.
And etching the polysilicon layer in the window under the definition of the reformed source region window, removing the polysilicon layer in the window and exposing the silicon oxide layer below the polysilicon layer.
And performing secondary low-energy doping ion implantation in the source region window, wherein the implantation energy is 1 Kev-500 Kev, and the low-energy ion implantation can be completed by one-time implantation or multiple step implantation.
By the process method, after high-energy injection, the photoresist is subjected to a small amount of modified etching, the injection range of the source region is redefined, and the influence of a high-energy injection doping source entering the photoresist blocking region on the LDMOS channel is avoided.
The above are merely preferred embodiments of the present invention, and are not intended to limit the present invention. Various modifications and alterations to this invention will become apparent to those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (9)

1. A source end process method of an LDMOS device is characterized in that:
coating photoresist on the surface of the substrate or the epitaxy, opening the photoresist at the source end of the LDMOS device to form an injection window of the source end, performing first ion injection on the source end, and forming a source region in the substrate or the epitaxy;
then etching the source region photoresist to form a new source end injection window, and redefining a source region and a channel;
etching the polysilicon layer in the window under the definition of the reformed source region window, removing the polysilicon layer in the window and exposing the silicon oxide layer below the polysilicon layer;
and carrying out second doping ion implantation in the source region window.
2. The source terminal process method of the LDMOS device set forth in claim 1, wherein: in the first step, the thickness of the coated photoresist is not less than 1um, the photoresist is opened to form a window after photoetching, and the side wall of the photoresist in the window is in an inclined state.
3. The source terminal process method of the LDMOS device set forth in claim 1, wherein: in the first step, the first ion implantation is high-energy ion implantation; the implantation is formed by one-step implantation or multi-step implantation.
4. The source terminal process method of the LDMOS device set forth in claim 1, wherein: in the first step, after the first ion implantation, high-energy ions pass through the side wall of the photoresist in the inclined window, and besides forming a source region in the substrate or the extension, a doping source implantation region is additionally formed and is formed at the edge of the source region, and the implantation depth is smaller than that of the source region.
5. The source terminal process method of the LDMOS device set forth in claim 1, wherein: and etching the photoresist of the source region again, and etching the photoresist of the window region by adopting dry etching to further enlarge the window region.
6. The source terminal process method of the LDMOS device of claim 4 or 5, wherein: after the window area is enlarged, the doping source injection area with 50-100% area is also in the range of opening the window.
7. The source terminal process method of the LDMOS device set forth in claim 1, wherein: the second low-energy doping ion implantation is completed by one implantation or multiple step implantations.
8. The source terminal process method of the LDMOS device set forth in claim 1, wherein: the first high-energy injection has the injection energy of 50 Kev-2500 Kev.
9. The source terminal process method of the LDMOS device set forth in claim 1, wherein: and the second low-energy implantation with implantation energy of 1 Kev-500 Kev.
CN202111440107.4A 2021-11-30 2021-11-30 Source end process method of LDMOS device Pending CN114188404A (en)

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CN202111440107.4A CN114188404A (en) 2021-11-30 2021-11-30 Source end process method of LDMOS device

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Application Number Priority Date Filing Date Title
CN202111440107.4A CN114188404A (en) 2021-11-30 2021-11-30 Source end process method of LDMOS device

Publications (1)

Publication Number Publication Date
CN114188404A true CN114188404A (en) 2022-03-15

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