CN111430243B - Method for manufacturing semiconductor device and semiconductor device - Google Patents
Method for manufacturing semiconductor device and semiconductor device Download PDFInfo
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- CN111430243B CN111430243B CN202010391060.6A CN202010391060A CN111430243B CN 111430243 B CN111430243 B CN 111430243B CN 202010391060 A CN202010391060 A CN 202010391060A CN 111430243 B CN111430243 B CN 111430243B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 56
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 31
- 238000000034 method Methods 0.000 title claims abstract description 31
- 150000002500 ions Chemical class 0.000 claims abstract description 56
- 238000001259 photo etching Methods 0.000 claims abstract description 22
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 19
- 229920005591 polysilicon Polymers 0.000 claims abstract description 19
- 238000005530 etching Methods 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 238000002347 injection Methods 0.000 claims abstract description 10
- 239000007924 injection Substances 0.000 claims abstract description 10
- 238000000151 deposition Methods 0.000 claims abstract description 4
- 238000002513 implantation Methods 0.000 claims description 43
- 238000001459 lithography Methods 0.000 description 11
- 238000000206 photolithography Methods 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- -1 phosphorus ions Chemical class 0.000 description 5
- 229910044991 metal oxide Inorganic materials 0.000 description 3
- 150000004706 metal oxides Chemical class 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 210000000746 body region Anatomy 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000003252 repetitive effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- High Energy & Nuclear Physics (AREA)
- Manufacturing & Machinery (AREA)
- Toxicology (AREA)
- Health & Medical Sciences (AREA)
- Ceramic Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a manufacturing method of a semiconductor device and the semiconductor device, comprising the following steps: providing a semiconductor substrate; forming a deep well on a semiconductor substrate, defining an active region and depositing polysilicon; providing a first photoetching plate, etching the polysilicon through the first photoetching plate to form a first injection window, injecting first conductive type ions to form a first conductive type well, and injecting high-concentration first conductive type ions into the first conductive type well; providing a second photoetching plate, etching the polysilicon through the second photoetching plate to form a second injection window, injecting second conductive type ions to form a second conductive type well, and injecting high-concentration first conductive type ions into the second conductive type well; providing a third photoetching plate, etching to form a contact hole, and injecting high-concentration second conductivity type ions into the second conductivity type well through the contact hole; and filling the contact hole to form the semiconductor device. The process for manufacturing the semiconductor device reduces the cost.
Description
Technical Field
The present invention relates to the field of semiconductor manufacturing, and in particular, to a method for manufacturing a semiconductor device and a semiconductor device.
Background
The BCD (bipolarcmos-DMOS) process is an integrated process technology that enables bipolarcmos and DMOS devices to be integrated simultaneously on a single chip.
The lateral diffusion metal oxide semiconductor (Laterally Diffused Metal Oxide Semiconductor, LDMOS) device, which is used as a high-voltage lateral semiconductor device in the BCD process, is a lightly doped MOS device, has good thermal stability and frequency stability, high gain and durability, low feedback capacitance and resistance, is generally used as a driving device of a subsequent module, and is the most critical part in the BCD process design.
As shown in fig. 1, fig. 1 illustrates a conventional BCD process for manufacturing an LDMOS device, as shown in fig. 1, comprising the steps of:
forming a Deep N Well (DNW) to form a drift region of the LDMOS device;
defining an Active Area (AA);
forming a device poly Gate (GT) to form a gate;
forming an N Well (NW) and a P Well (PW) to form a low-voltage well region of the device;
forming an N+ injection region (SN) and a P+ injection region (SP) to form a source drain region;
contact holes (CT) are formed.
As can be seen from the above, the BCD conventional process for manufacturing the LDMOS device requires at least 8 layers of lithography, and the BCD process generally measures the process cost by the number of lithography layers, so that it is advantageous to control the process cost and improve the efficiency by reducing the number of lithography layers.
Disclosure of Invention
In view of the foregoing, an aspect of the present invention proposes a method of manufacturing a semiconductor device, including:
providing a semiconductor substrate;
forming a deep well, defining an active region and depositing polysilicon on the semiconductor substrate;
providing a first photoetching plate, and etching the polysilicon through the first photoetching plate to form a first injection window;
implanting first conductive type ions through the first implantation window to form a first conductive type well, and implanting high-concentration first conductive type ions in the first conductive type well to form a drain region;
providing a second photoetching plate, and etching the polysilicon through the second photoetching plate to form a second injection window;
implanting the second conductive type ions through the second implantation window to form a second conductive type well, and implanting high-concentration first conductive type ions in the second conductive type well to form a source region;
providing a third photoetching plate for etching the source region and the drain region to form a contact hole, and injecting high-concentration second conductivity type ions into the second conductivity type well through the contact hole;
and filling the contact hole to form the semiconductor device.
In an embodiment, the first conductive type ions are implanted through the first implantation window, or/and the second conductive type ions are implanted through the second implantation window, and the implantation angle is 15-65 degrees.
In one embodiment, the first conductivity type ions are implanted through the first implantation window, or/and the second conductivity type ions are implanted through the second implantation window, and the implantation energy is 60 KeV-800 KeV.
In an embodiment, the amount of the implantation dose of the high concentration second conductivity type ions into the second conductivity type well is an order of magnitude smaller than the amount of the implantation dose of the high concentration first conductivity type ions into the second conductivity type well.
In one embodiment, the high concentration first conductivity type ions are implanted in the first conductivity type well, or/and the high concentration first conductivity type ions are implanted in the second conductivity type well, and the implantation dosage is 5E 15-5E 16.
In one embodiment, the high concentration of the second conductivity type ions is implanted in the second conductivity type well at a dose of 5E14 to 5E15.
In an embodiment, the deep well is a deep N-well, the first conductivity type well is an N-well, and the second conductivity type well is a P-well.
In one embodiment, the first reticle is an N-well reticle and the second reticle is a P-well reticle.
In one embodiment, the third reticle is a contact hole reticle.
Another aspect of the invention provides a semiconductor device manufactured using any of the manufacturing methods described above.
Compared with the traditional BCD process, the manufacturing method of the semiconductor device and the semiconductor device provided by the invention have the advantages that the number of photoetching plates is reduced, and the process and manufacturing cost are reduced, so that the development cost of the semiconductor device is reduced.
Drawings
Fig. 1 illustrates a conventional BCD process for fabricating an LDMOS device;
FIG. 2 is a flow chart of a method for fabricating a semiconductor device according to an embodiment of the invention; and
fig. 3 to 12 are schematic structural views showing a method of manufacturing the semiconductor device shown in fig. 2.
Detailed Description
The present invention will be described in detail below with reference to specific embodiments shown in the drawings. These embodiments are not intended to limit the invention and structural, methodological, or functional modifications of these embodiments that may be made by one of ordinary skill in the art are included within the scope of the invention.
Example embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments can be embodied in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus a repetitive description thereof will be omitted.
The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the invention. It will be appreciated, however, by one skilled in the art that the inventive aspects may be practiced without one or more of the specific details, or with other methods, components, materials, etc. In some instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring the invention.
In one embodiment of the present invention, a method for manufacturing a semiconductor device is provided, including:
providing a semiconductor substrate;
forming a deep well on a semiconductor substrate, defining an active region and depositing polysilicon;
providing a first photoetching plate, and etching the polysilicon through the first photoetching plate to form a first injection window;
implanting first conductive type ions through the first implantation window to form a first conductive type well, and implanting high-concentration first conductive type ions in the first conductive type well to form a drain region;
providing a second photoetching plate, and etching the polysilicon through the second photoetching plate to form a second injection window;
implanting second conductive type ions through the second implantation window to form a second conductive type well, and implanting high-concentration first conductive type ions in the second conductive type well to form a source region;
providing a third photoetching plate for etching the source region and the drain region to form a contact hole, and injecting high-concentration second conductive type ions into the second conductive type well;
and filling the contact hole to form the semiconductor device.
The method of manufacturing a semiconductor device according to the present invention will be described in detail below using an N-type laterally diffused metal oxide semiconductor (NLDMOS) as an example, and one of ordinary skill in the art can derive corresponding methods of manufacturing other semiconductor devices in accordance with the teachings of the present invention.
Referring to fig. 2-11, fig. 2 is a flow chart illustrating a method for manufacturing a semiconductor device according to an embodiment of the invention, and fig. 3-12 are structural diagrams related to the method for manufacturing a semiconductor device shown in fig. 2.
First, in step 201, a semiconductor substrate 11, which in this embodiment may be a P-type substrate (PSUB), is provided.
Then, in step 202, a deep well 12 is formed on the semiconductor substrate 11, an active region is defined, and polysilicon 13 is deposited, as shown in fig. 3.
Specifically, on the semiconductor substrate 11, deep wells 12 are formed by photolithography using a deep well mask (DW mask), and corresponding active regions are defined by photolithography using an active region mask (AA mask), and then polysilicon 13 is deposited.
In this embodiment, the deep well reticle may be a deep N-well reticle (DNW mask).
Thereafter, in step 203, a first reticle 21 is provided, and the polysilicon 13 is etched through the first reticle 21 to form a first implantation window A1 (as shown in fig. 5).
Specifically, in this embodiment, the first photolithography plate is an N-well photolithography plate (NW mask), a Photoresist (Photoresist) 31 is coated on the polysilicon 13, and then the Photoresist 31 is exposed and developed to form a pattern of the first photolithography plate 21, as shown in fig. 4, and the polysilicon 13 is etched to form a first implantation window A1.
Then, in step 204, first conductivity type ions are implanted through the first implantation window A1 to form the first conductivity type well 14, and high concentration first conductivity type ions are implanted in the first conductivity type well 14 to form the drain region 15.
In this embodiment, the first conductivity type is N-type, and N-type ions, such as phosphorus ions, are implanted through the first implantation window A1, and the implantation angle is a large angle implantation, such as 15 ° to 65 °, and the implantation energy is in the range of 60KeV to 800KeV, so as to form an N Well (NW), as shown in fig. 5. And implanting ions of the first conductivity type at a high concentration, i.e., implanting n+ ions (SN), in a dose range of 5E15 to 5E16, as shown in fig. 6, to form a drain region 15.
Next, in step 205, a second reticle 22 is provided, and the polysilicon 13 is etched through the second reticle 22, and a second implantation window A2 is formed.
Specifically, in this embodiment, the second mask 22 is a P-well mask (PW mask), and a photoresist 32 is coated on the polysilicon 13 to protect the drain region, and etching is performed to form a second implantation window A2, as shown in fig. 7.
Then, in step 206, second conductivity type ions are implanted through the second implantation window A2 to form the second conductivity type well 16, and high concentration first conductivity type ions are implanted in the second conductivity type well 16 to form the source region 17.
In this embodiment, the second conductivity type is P-type, the P-type ions, such as boron ions, are implanted through the second implantation window A2, and the implantation angle may be a large angle implantation, such as 15 ° to 65 °, and the implantation energy may be in the range of 60KeV to 800KeV, so as to form a P-well (PW), as shown in fig. 8. High concentrations of ions of the first conductivity type may also be implanted at a large angle along the sidewalls of photoresist 32 at a dose in the range of 5E15 to 5E16, i.e., N + ions (SN), to form source regions 17, as shown in fig. 9.
Thereafter, in step 207, a third photolithography tool 23 is provided to etch the source region 17, the drain region 15 to form a contact hole CT, and to implant high concentration of second conductive type ions in the second conductive type well 16.
In this embodiment, the third mask 23 is a contact hole mask (CT mask), and is coated with a photoresist 33, etched to form a contact hole CT, as shown in fig. 10, and high-concentration second conductivity type ions, i.e., p+ ions (SP), are implanted into the P-well through the contact hole CT, as shown in fig. 11.
The amount of the implantation dose of the high concentration second conductivity type ions into the second conductivity type well 16 is smaller than the amount of the implantation dose of the high concentration first conductivity type ions into the second conductivity type well 16, that is, the amount of the implantation dose of the p+ ions into the P well is smaller than the amount of the implantation dose of the n+ ions, and in this embodiment, the amount of the implantation dose of the p+ ions is 5E14 to 5E15. Since the p+ dose is an order of magnitude smaller than the n+ dose, the region in the P-well where both n+ and p+ are implanted still appears as an n+ region.
Finally, in step 208, the contact holes are filled, i.e., the electrical connection structures are added, thereby forming the final semiconductor device.
As shown in fig. 12, in the present embodiment, the semiconductor device is formed including a source region 17, a drain region 15, a polycrystalline gate 19, and a body region (SP) 18.
As can be seen from the above, in this embodiment, only 5 layers of lithography are needed to manufacture the NLDMOS device, that is, only the deep well lithography, the active region lithography, the N-well lithography, the P-well lithography, and the contact hole lithography are needed, and compared with the conventional BCD process, the total number of lithography is 5, 3 lithography blocks are reduced, and the process and manufacturing cost are reduced, thereby reducing the development cost of the semiconductor device.
In the above manufacturing process, NLDMOS is taken as an example, but the same applies to PLDMOS, that is, in this case, the first conductivity type may be P-type, the second conductivity type may be N-type, and the related process may be adaptively adjusted.
In another embodiment of the present invention, a semiconductor device is fabricated using the fabrication method described above, and as shown in fig. 12, the semiconductor device includes a source region 17, a drain region 15, a poly gate 19, and a body region (SP) 18.
Compared with the traditional BCD process, the manufacturing method of the semiconductor device and the semiconductor device provided by the invention have the advantages that the number of photoetching plates is reduced, and the process and manufacturing cost are reduced, so that the development cost of the semiconductor device is reduced.
It will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.
Claims (10)
1. A method of manufacturing a semiconductor device, comprising:
providing a semiconductor substrate;
forming a deep well, defining an active region and depositing polysilicon on the semiconductor substrate;
providing a first photoetching plate, and etching the polysilicon through the first photoetching plate to form a first injection window;
implanting first conductive type ions through the first implantation window to form a first conductive type well, and implanting high-concentration first conductive type ions in the first conductive type well to form a drain region;
providing a second photoetching plate, and etching the polysilicon through the second photoetching plate to form a second injection window;
implanting second conductive type ions through the second implantation window to form a second conductive type well, and implanting high-concentration first conductive type ions into the second conductive type well to form a source region;
providing a third photoetching plate for etching the source region and the drain region to form a contact hole, and injecting high-concentration second conductivity type ions into the second conductivity type well through the contact hole;
and filling the contact hole to form the semiconductor device.
2. The method according to claim 1, wherein the first conductivity type ions are implanted through a first implantation window, or/and the second conductivity type ions are implanted through a second implantation window, the implantation angle being 15 ° to 65 °.
3. The method according to claim 1, wherein ions of the first conductivity type are implanted through a first implantation window, or/and ions of the second conductivity type are implanted through a second implantation window, and the implantation energy is 60KeV to 800KeV.
4. The method of manufacturing a semiconductor device according to claim 1, wherein an implantation dose of high-concentration second conductivity type ions is an order of magnitude smaller than an implantation dose of high-concentration first conductivity type ions in the second conductivity type well.
5. The method according to claim 4, wherein the high concentration of the first conductivity type ions is implanted in the first conductivity type well, or/and the high concentration of the first conductivity type ions is implanted in the second conductivity type well, the implantation dose being 5E15 to 5E16.
6. The method of manufacturing a semiconductor device according to claim 4, wherein high concentration of second conductivity type ions is implanted in the second conductivity type well at a dose of 5E14 to 5E15.
7. The method of manufacturing a semiconductor device according to claim 1, wherein the deep well is a deep N-well, the first conductivity type well is an N-well, and the second conductivity type well is a P-well.
8. The method of manufacturing a semiconductor device according to claim 7, wherein the first reticle is an N-well reticle and the second reticle is a P-well reticle.
9. The method of manufacturing a semiconductor device according to claim 1, wherein the third reticle is a contact hole reticle.
10. A semiconductor device manufactured by the manufacturing method according to any one of claims 1 to 9.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102738215A (en) * | 2011-08-18 | 2012-10-17 | 成都芯源系统有限公司 | Lateral double-diffused metal oxide semiconductor field effect transistor and manufacturing method thereof |
| CN107634001A (en) * | 2016-11-18 | 2018-01-26 | 成都芯源系统有限公司 | Manufacturing method of L DMOS device |
| CN107742645A (en) * | 2016-09-28 | 2018-02-27 | 成都芯源系统有限公司 | Method for manufacturing L DMOS device with self-aligned body region |
| CN110610860A (en) * | 2018-06-14 | 2019-12-24 | 美格纳半导体有限公司 | Semiconductor device and method for manufacturing semiconductor device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2010225736A (en) * | 2009-03-23 | 2010-10-07 | Oki Semiconductor Co Ltd | Semiconductor device and method of manufacturing the semiconductor device |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102738215A (en) * | 2011-08-18 | 2012-10-17 | 成都芯源系统有限公司 | Lateral double-diffused metal oxide semiconductor field effect transistor and manufacturing method thereof |
| CN107742645A (en) * | 2016-09-28 | 2018-02-27 | 成都芯源系统有限公司 | Method for manufacturing L DMOS device with self-aligned body region |
| CN107634001A (en) * | 2016-11-18 | 2018-01-26 | 成都芯源系统有限公司 | Manufacturing method of L DMOS device |
| CN110610860A (en) * | 2018-06-14 | 2019-12-24 | 美格纳半导体有限公司 | Semiconductor device and method for manufacturing semiconductor device |
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Address after: Room 901-23, 9 / F, west 4 building, Xigang development center, 298 Zhenhua Road, Sandun Town, Xihu District, Hangzhou City, Zhejiang Province Applicant after: Jiehuate Microelectronics Co.,Ltd. Address before: Room 901-23, 9 / F, west 4 building, Xigang development center, 298 Zhenhua Road, Sandun Town, Xihu District, Hangzhou City, Zhejiang Province Applicant before: JOULWATT TECHNOLOGY Inc.,Ltd. |
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