CN111430243A - Method for manufacturing semiconductor device and semiconductor device - Google Patents

Method for manufacturing semiconductor device and semiconductor device Download PDF

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CN111430243A
CN111430243A CN202010391060.6A CN202010391060A CN111430243A CN 111430243 A CN111430243 A CN 111430243A CN 202010391060 A CN202010391060 A CN 202010391060A CN 111430243 A CN111430243 A CN 111430243A
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conductivity type
semiconductor device
well
manufacturing
conductive type
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CN111430243B (en
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陈斌
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Joulwatt Technology Hangzhou Co Ltd
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Joulwatt Technology Hangzhou Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Manufacturing & Machinery (AREA)
  • Toxicology (AREA)
  • Health & Medical Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The invention discloses a manufacturing method of a semiconductor device and the semiconductor device, comprising: providing a semiconductor substrate; forming a deep well on a semiconductor substrate, defining an active region and depositing polycrystalline silicon; providing a first photoetching plate, etching the polycrystalline silicon through the first photoetching plate to form a first injection window, injecting first conductive type ions to form a first conductive type trap, and injecting high-concentration first conductive type ions into the first conductive type trap; providing a second photoetching plate, etching the polycrystalline silicon through the second photoetching plate to form a second injection window, injecting second conductive type ions to form a second conductive type trap, and injecting high-concentration first conductive type ions into the second conductive type trap; providing a third photoetching plate, etching to form a contact hole, and injecting high-concentration second conductive type ions into the second conductive type trap through the contact hole; and filling the contact hole to form the semiconductor device. The process for manufacturing the semiconductor device reduces the cost.

Description

Method for manufacturing semiconductor device and semiconductor device
Technical Field
The present invention relates to the field of semiconductor manufacturing, and in particular, to a method for manufacturing a semiconductor device and a semiconductor device.
Background
The BCD (Bipolar-CMOS-DMOS) process is an integrated process technology that enables the simultaneous integration of Bipolar, CMOS and DMOS devices on a single chip.
A laterally Diffused Metal oxide semiconductor (L ideal Diffused Metal oxide semiconductor device, &lTtT transition = L' &gTt L &lTt/T &gTt DMOS) device is used as a high-voltage lateral semiconductor device in a BCD process, is a lightly doped MOS device, has good thermal stability and frequency stability, high gain and durability and low feedback capacitance and resistance, is generally used as a driving device of a subsequent module and is the most critical part in the BCD process design.
Fig. 1 shows a conventional BCD process for manufacturing L DMOS device, as shown in fig. 1, including the following steps:
forming a Deep N Well (DNW) to form a drift region of an L DMOS device;
defining an Active Area (AA);
forming a device poly Gate (GT) to form a gate;
forming an N Well (NW) and a P Well (PW) to form a low-voltage well region of the device;
forming an N + injection region (SN) and a P + injection region (SP) to form a source drain region;
contact holes (CT) are formed.
As can be seen from the above, the conventional BCD process for manufacturing L DMOS devices requires at least 8 levels of lithography, and the BCD process usually measures the process cost by the number of lithography levels, so that it is advantageous to reduce the number of lithography levels to control the process cost and improve the efficiency.
Disclosure of Invention
In view of the above, an aspect of the present invention provides a method of manufacturing a semiconductor device, including:
providing a semiconductor substrate;
forming a deep well on the semiconductor substrate, defining an active region and depositing polycrystalline silicon;
providing a first photoetching plate, and etching the polycrystalline silicon through the first photoetching plate to form a first injection window;
implanting first conductivity type ions through the first implantation window to form a first conductivity type well, and implanting high concentration first conductivity type ions in the first conductivity type well to form a drain region;
providing a second photoetching plate, and etching the polycrystalline silicon through the second photoetching plate to form a second injection window;
implanting the second conductive type ions through the second implantation window to form a second conductive type well, and implanting high-concentration first conductive type ions in the second conductive type well to form a source region;
providing a third photoetching plate for etching the source region and the drain region to form a contact hole, and injecting high-concentration second conductive type ions into the second conductive type trap through the contact hole;
and filling the contact hole to form the semiconductor device.
In one embodiment, the first conductivity type ions are implanted through the first implantation window, or/and the second conductivity type ions are implanted through the second implantation window, and the implantation angle is 15-65 °.
In one embodiment, the first conductive type ions are implanted through the first implantation window, or/and the second conductive type ions are implanted through the second implantation window, and the implantation energy is 60KeV to 800 KeV.
In one embodiment, an implantation dose of implanting high concentration of second conductivity type ions in the second conductivity type well is smaller than an implantation dose of implanting high concentration of first conductivity type ions in the second conductivity type well.
In one embodiment, high concentration first conductive type ions are implanted into the first conductive type trap, or/and high concentration first conductive type ions are implanted into the second conductive type trap, wherein the implantation dosage is 5E 15-5E 16.
In one embodiment, high concentration second conductive type ions are implanted into the second conductive type trap at a dose of 5E 14-5E 15.
In an embodiment, the deep well is a deep N-well, the first conductive type well is an N-well, and the second conductive type well is a P-well.
In one embodiment, the first reticle is an N-well reticle and the second reticle is a P-well reticle.
In one embodiment, the third reticle is a contact hole reticle.
Another aspect of the present invention provides a semiconductor device manufactured by the manufacturing method described in any one of the above.
Compared with the traditional BCD process, the manufacturing method of the semiconductor device and the semiconductor device provided by the invention have the advantages that the number of the photoetching plates is reduced, and the process and manufacturing cost are reduced, so that the development cost of the semiconductor device is reduced.
Drawings
Fig. 1 illustrates a conventional BCD process for making L DMOS devices;
FIG. 2 is a schematic flow chart illustrating a method of fabricating a semiconductor device according to an embodiment of the present invention; and
fig. 3-12 are schematic structural diagrams illustrating the method of manufacturing the semiconductor device shown in fig. 2.
Detailed Description
The present invention will be described in detail below with reference to specific embodiments shown in the drawings. These embodiments are not intended to limit the present invention, and structural, methodological, or functional changes made by those skilled in the art according to these embodiments are included in the scope of the present invention.
Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus their repetitive description will be omitted.
The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to provide a thorough understanding of embodiments of the invention. One skilled in the relevant art will recognize, however, that the invention may be practiced without one or more of the specific details, or with other methods, components, materials, and so forth. In some instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring the invention.
In one embodiment of the present invention, a method for manufacturing a semiconductor device includes:
providing a semiconductor substrate;
forming a deep well on a semiconductor substrate, defining an active region and depositing polycrystalline silicon;
providing a first photoetching plate, and etching the polycrystalline silicon through the first photoetching plate to form a first injection window;
implanting first conductivity type ions through the first implantation window to form a first conductivity type well, and implanting high concentration first conductivity type ions in the first conductivity type well to form a drain region;
providing a second photoetching plate, and etching the polycrystalline silicon through the second photoetching plate to form a second injection window;
implanting second conductivity type ions through the second implantation window to form a second conductivity type well, and implanting high-concentration first conductivity type ions into the second conductivity type well to form a source region;
providing a third photoetching plate for etching the source region and the drain region to form a contact hole and injecting high-concentration second conductive type ions into the second conductive type well;
and filling the contact hole to form the semiconductor device.
The following will describe the method for manufacturing a semiconductor device in detail by taking an N-type laterally diffused metal oxide semiconductor (N L DMOS) as an example, and those skilled in the art can obtain other corresponding methods for manufacturing a semiconductor device according to the teachings of the present invention.
Referring to fig. 2-11, fig. 2 is a flow chart illustrating a method for manufacturing a semiconductor device according to an embodiment of the invention, and fig. 3-12 are structural diagrams illustrating the method for manufacturing the semiconductor device shown in fig. 2.
First, in step 201, a semiconductor substrate 11, which may be a P-type substrate (PSUB) in this embodiment, is provided.
Then, in step 202, a deep well 12 is formed on the semiconductor substrate 11, an active region is defined, and polysilicon 13 is deposited, as shown in fig. 3.
Specifically, on the semiconductor substrate 11, a deep well 12 is formed by performing photolithography using a deep well reticle (DW mask), and an active area reticle (AA mask) is used to perform photolithography, define a corresponding active area, and then deposit polysilicon 13.
In this embodiment, the deep well reticle may be a deep N-well reticle (DNW mask).
Thereafter, in step 203, a first reticle 21 is provided, and the polysilicon 13 is etched through the first reticle 21 to form a first implantation window a1 (as shown in fig. 5).
Specifically, in this embodiment, the first reticle is an N-well reticle (NW mask), a Photoresist (Photoresist)31 is coated on the polysilicon 13, the Photoresist 31 is exposed and developed to form a pattern of the first reticle 21, as shown in fig. 4, and the polysilicon 13 is etched to form the first implantation window a 1.
Then, in step 204, first conductivity type ions are implanted through first implantation window a1 to form first conductivity type well 14, and high concentration first conductivity type ions are implanted in first conductivity type well 14 to form drain region 15.
In the present embodiment, the first conductive type is set to N-type, N-type ions, such as phosphorus ions, are implanted through the first implantation window a1 at a large angle, such as 15 ° to 65 °, and at an implantation energy ranging from 60KeV to 800KeV, thereby forming an N-well (NW), as shown in fig. 5. And implanting high concentration first conductivity type ions, i.e., implanting N + ions (SN), with an implantation dose in the range of 5E 15-5E 16, as shown in FIG. 6, to form the drain region 15.
Next, in step 205, a second reticle 22 is provided, the polysilicon 13 is etched through the second reticle 22, and a second implantation window a2 is formed.
Specifically, in the present embodiment, the second reticle 22 is a P-well reticle (PW mask), and the photoresist 32 is coated on the polysilicon 13 to protect the drain region, and etching is performed to form the second implantation window a2, as shown in fig. 7.
Then, in step 206, second conductivity type ions are implanted through second implantation window a2 to form second conductivity type well 16, and high concentration first conductivity type ions are implanted in second conductivity type well 16 to form source region 17.
In the present embodiment, the second conductive type is P-type, P-type ions, such as boron ions, are implanted through the second implantation window a2, and the implantation angle may also be a large angle, such as 15 ° to 65 °, and the implantation energy range is 60KeV to 800KeV, so as to form a P-well (PW), as shown in fig. 8. High concentrations of first conductivity type ions can also be implanted at large angles along the sidewalls of the photoresist 32, with an implant dose in the range of 5E 15-5E 16, i.e., N + ions (SN) are implanted to form the source region 17, as shown in FIG. 9.
Thereafter, in step 207, a third reticle 23 is provided for etching the source region 17 and the drain region 15 to form a contact hole CT, and implanting high concentration second conductive type ions into the second conductive type well 16.
In this embodiment, the third reticle 23 is a contact hole reticle (CT mask), a photoresist 33 is coated and etched to form a contact hole CT, as shown in fig. 10, and a high concentration of second conductive type ions, i.e., P + ions (SP), are implanted into the P-well through the contact hole CT, as shown in fig. 11.
It should be noted that the implantation dose of the high concentration second conductivity type ions in the second conductivity type well 16 is smaller than the implantation dose of the high concentration first conductivity type ions in the second conductivity type well 16, that is, the implantation dose of the P + ions in the P well is smaller than the implantation dose of the N + ions, and in this embodiment, the implantation dose of the P + ions is 5E 14-5E 15. Since the P + dose is one order of magnitude less than the N + dose, the region in the P-well where both N + and P + are implanted still behaves as an N + region.
Finally, in step 208, the contact holes are filled, i.e., electrical connection structures are added, thereby forming the final semiconductor device.
As shown in fig. 12, in the present embodiment, a semiconductor device is formed including a source region 17, a drain region 15, a poly gate 19, and a body region (SP) 18.
As can be seen from the above, in this embodiment, only 5 layers of photolithography are required for manufacturing the N L DMOS device, that is, only 5 photolithography masks are required, that is, only the deep well photolithography mask, the active region photolithography mask, the N well photolithography mask, the P well photolithography mask, and the contact hole photolithography mask are required, which reduces 3 photolithography masks and reduces the process and manufacturing cost compared to the conventional BCD process, thereby reducing the development cost of the semiconductor device.
In the above manufacturing process, N L DMOS is taken as an example, but the same is also applicable to P L DMOS, that is, in this case, the first conductivity type may be P-type, the second conductivity type may be N-type, and the related process may be adaptively adjusted.
In another embodiment of the present invention, a semiconductor device manufactured by the above manufacturing method, as shown in fig. 12, includes a source region 17, a drain region 15, a poly gate 19 and a body region (SP) 18.
Compared with the traditional BCD process, the manufacturing method of the semiconductor device and the semiconductor device provided by the invention have the advantages that the number of the photoetching plates is reduced, and the process and manufacturing cost are reduced, so that the development cost of the semiconductor device is reduced.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims (10)

1. A method of manufacturing a semiconductor device, comprising:
providing a semiconductor substrate;
forming a deep well on the semiconductor substrate, defining an active region and depositing polycrystalline silicon;
providing a first photoetching plate, and etching the polycrystalline silicon through the first photoetching plate to form a first injection window;
implanting first conductivity type ions through the first implantation window to form a first conductivity type well, and implanting high concentration first conductivity type ions in the first conductivity type well to form a drain region;
providing a second photoetching plate, and etching the polycrystalline silicon through the second photoetching plate to form a second injection window;
implanting the second conductive type ions through the second implantation window to form a second conductive type well, and implanting high-concentration first conductive type ions in the second conductive type well to form a source region;
providing a third photoetching plate for etching the source region and the drain region to form a contact hole, and injecting high-concentration second conductive type ions into the second conductive type trap through the contact hole;
and filling the contact hole to form the semiconductor device.
2. The method for manufacturing a semiconductor device according to claim 1, wherein the first conductivity type ions are implanted through the first implantation window, or/and the second conductivity type ions are implanted through the second implantation window, and an angle of implantation is 15 ° to 65 °.
3. The method for manufacturing a semiconductor device according to claim 1, wherein the first conductivity type ions are implanted through the first implantation window, or/and the second conductivity type ions are implanted through the second implantation window, and the implantation energy is 60KeV to 800 KeV.
4. The manufacturing method of a semiconductor device according to claim 1, wherein an implantation dose of implanting high-concentration second conductivity type ions in the second conductivity type well is smaller than an implantation dose of implanting high-concentration first conductivity type ions in the second conductivity type well.
5. The method for manufacturing a semiconductor device according to claim 4, wherein a high concentration of first conductivity type ions is implanted in the first conductivity type well, or/and a high concentration of first conductivity type ions is implanted in the second conductivity type well at an implant dose of 5E15 to 5E 16.
6. The method for manufacturing a semiconductor device according to claim 4, wherein a high concentration of second conductivity type ions is implanted into the second conductivity type well at a dose of 5E14 to 5E 15.
7. The manufacturing method of a semiconductor device according to claim 1, wherein the deep well is a deep N-well, the first conductive type well is an N-well, and the second conductive type well is a P-well.
8. A method for manufacturing a semiconductor device according to claim 7, wherein the first reticle is an N-well reticle and the second reticle is a P-well reticle.
9. A method for manufacturing a semiconductor device according to claim 1, wherein the third reticle is a contact hole reticle.
10. A semiconductor device manufactured by the manufacturing method according to any one of claims 1 to 9.
CN202010391060.6A 2020-05-11 2020-05-11 Method for manufacturing semiconductor device and semiconductor device Active CN111430243B (en)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100237413A1 (en) * 2009-03-23 2010-09-23 Oki Semiconductor Co., Ltd. Semiconductor device and method for manufacturing semiconductor device
CN102738215A (en) * 2011-08-18 2012-10-17 成都芯源系统有限公司 Lateral double-diffused metal oxide semiconductor field effect transistor and manufacturing method thereof
CN107634001A (en) * 2016-11-18 2018-01-26 成都芯源系统有限公司 Manufacturing method of L DMOS device
CN107742645A (en) * 2016-09-28 2018-02-27 成都芯源系统有限公司 Method for manufacturing L DMOS device with self-aligned body region
CN110610860A (en) * 2018-06-14 2019-12-24 美格纳半导体有限公司 Semiconductor device and method for manufacturing semiconductor device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100237413A1 (en) * 2009-03-23 2010-09-23 Oki Semiconductor Co., Ltd. Semiconductor device and method for manufacturing semiconductor device
CN102738215A (en) * 2011-08-18 2012-10-17 成都芯源系统有限公司 Lateral double-diffused metal oxide semiconductor field effect transistor and manufacturing method thereof
CN107742645A (en) * 2016-09-28 2018-02-27 成都芯源系统有限公司 Method for manufacturing L DMOS device with self-aligned body region
CN107634001A (en) * 2016-11-18 2018-01-26 成都芯源系统有限公司 Manufacturing method of L DMOS device
CN110610860A (en) * 2018-06-14 2019-12-24 美格纳半导体有限公司 Semiconductor device and method for manufacturing semiconductor device

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