CN208861995U - A kind of LDMOS device structure - Google Patents
A kind of LDMOS device structure Download PDFInfo
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- CN208861995U CN208861995U CN201821139718.9U CN201821139718U CN208861995U CN 208861995 U CN208861995 U CN 208861995U CN 201821139718 U CN201821139718 U CN 201821139718U CN 208861995 U CN208861995 U CN 208861995U
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Abstract
A kind of LDMOS device structure, comprising: the substrate of the first conduction type forms the epitaxial layer of the first conduction type on substrate；Form the drift region of the second conduction type in the epitaxial layer；The well region of first conduction type extends in substrate from the surface of epitaxial layer；The channel region of first conduction type, is formed in drift region and between drift region and well region；The source region of second conduction type is located in well region and channel region；And second conduction type drain region, be located at drift region in, the grid above channel region is formed with gate insulating layer therebetween；Wherein, it is also formed with groove near surface from epitaxial layer, covers to trench portions drift region and channel region, the trench fill region that trench fill has oxide to constitute.
Description
Technical field
The utility model relates to technical field of semiconductors.More particularly, to a kind of LDMOS device structure.
Background technique
Cross bimoment (Lateral Double Diffused
It MOSFET is) that a kind of market demand is big, the wide radio-frequency power amplifier part of development prospect.In Radio-Frequency Wireless Communication field, base
It stands and long range transmitter almost all uses silicon substrate LDMOS high-capacity transistor；In addition, LDMOS is also widely used for radio frequency
Amplifier, as the communications field HF, VHF and UHF, pulse radar, industry, science and medical applications, aviation electronics and WiMAXTM are logical
The fields such as letter system.
With the reduction of LDMOS device size, the reduction of the gate oxide thickness, junction depth, channel length of device, device is in high pressure
Under environment, high electric field region will necessarily be generated, electric field strength increases in MOSFET channel, under the action of this strong electrical field of carrier
Very high energy will be obtained, these high energy carriers are known as " hot carrier ".Hot carrier hits lattice atoms, and collide electricity
From phenomenon, secondary electron hole pair is generated, wherein partial holes become substrate current, and part carrier can cross Si/SiO2
Potential barrier forms grid current, in Si/SiO2Place, which generates, generates trap in interfacial state and grid oxygen, so that device leads to device performance,
As the degeneration of threshold voltage, mutual conductance and linear zone/saturation region electric current even results in device to influence the service life of device
Part failure.
Accordingly, it is desirable to provide a kind of generation that can prevent hot carrier's effect, optimization drift region field distribution are to mention
The LDMOS device of high device lifetime, so as to be preferably applied in radio circuit and need to carry out high voltage control
In circuit.
Utility model content
The purpose of this utility model is to provide generation, optimization drift region electric fields that one kind can prevent hot carrier's effect
Distribution is to improve the LDMOS device structure of device lifetime.
In order to achieve the above objectives, the utility model adopts the following technical solutions:
A kind of LDMOS device structure, comprising: the substrate of the first conduction type forms the first conduction type on substrate
Epitaxial layer；Form the drift region of the second conduction type in the epitaxial layer；The well region of first conduction type, from the table of epitaxial layer
Face extends in substrate；The channel region of first conduction type, is formed in drift region and between drift region and well region；Second
The source region of conduction type is located in well region and channel region；And second conduction type drain region, be located at drift region in, be located at ditch
Grid above road area, is formed with gate insulating layer therebetween；Wherein, groove, ditch are also formed near surface from epitaxial layer
Cover to slot part drift region and channel region, the trench fill region that trench fill has oxide to constitute.
Preferably, the first conduction type is p-type, and the second conduction type is N-type；Or first conduction type be N-type, second
Conduction type is p-type.
Preferably, the depth of groove is
Preferably, LDMOS device structure further includes grid curb wall, is located at grid two sides.
Preferably, grid includes the metallic silicon of the polysilicon layer being formed on gate insulating layer and formation on the polysilicon layer
Compound layer.
Preferably, LDMOS device structure further include: the dielectric layer of covering drift region surface and gate surface；Positioned at insulation
The shading ring of grid and drift region is partly covered in layer.
The beneficial effects of the utility model are as follows:
Technical solution described in the utility model, which provides one kind, can prevent the generation of hot carrier's effect, optimization drift region
Field distribution is to improve the LDMOS device structure of device lifetime.
Detailed description of the invention
Specific embodiment of the present utility model is described in further detail with reference to the accompanying drawing:
Fig. 1 is the cross-sectional view for showing the exemplary L DMOS device architecture according to the application；And
Fig. 2 to Figure 14 is the gradually diagram for showing the exemplary production method of the LDMOS device structure according to the application.
Specific embodiment
In order to illustrate more clearly of the utility model, the utility model is done into one below with reference to preferred embodiments and drawings
The explanation of step.Similar component is indicated in attached drawing with identical appended drawing reference.It will be appreciated by those skilled in the art that below
Specifically described content is illustrative and be not restrictive, and should not be limited the protection scope of the present invention.
LDMOS device structure 10 provided in this embodiment includes the substrate 101 of the first conduction type, the first conduction type
Epitaxial layer 103, the drift region 105 of the second conduction type being lightly doped, the channel region 107 of the first conduction type, the first conductive-type
The well region 109 of type, wherein the doping concentration of substrate 101 is greater than the doping concentration of epitaxial layer 103.In the drift region 105 being lightly doped
In include the second conduction type heavy doping drain region 111, drain region 111 is from the extension of the surface of separate the substrate 101 of epitaxial layer 103
Into drift region 105, LDMOS device structure 10 further includes the source region 113 of the heavy doping of the second conduction type, and source region 113 is certainly
The surface of the separate substrate 101 of epitaxial layer 103 extends into well region 109 and channel region 107 and partly covers 107 He of channel region
Well region 109.
It should be understood that the first conduction type can be p-type, the second conduction type can be N-type.Optionally, the first conductive-type
Type can be N-type, and the second conduction type can be p-type.Those skilled in the art can need to select according to product.
According to the LDMOS device structure 10 of the application, from the surface of the separate substrate 101 of epitaxial layer to another surface direction
It is formed with groove (115-1 in Fig. 2 is not specifically shown out), covers to trench portions drift region 105 and channel region 107, groove
In filled with oxide constitute trench fill region 115.The presence in trench fill region 115 can significantly reduce channel region 107
Peak voltage between the high electric field of lower section, especially channel region 107 and drift region 105, avoids the generation of hot carrier, thus
The degeneration of the performances such as device threshold voltage, mutual conductance is avoided, to effectively extend the service life of device.
In addition, it will be seen from figure 1 that the LDMOS device structure 10 of the application further includes drain electrode 117, source electrode 119 and grid
121 (including 121-1 and 121-2).Grid 121 can also include polycrystalline silicon grid layer 121-1 and metal silicide layer 121-2, with
Make grid 121 that there is better controlling.
It could be formed with the grid curb wall 123 of silicon oxide material in 119 two sides of source electrode, to reduce leakage current.In grid
The side of close drain electrode can also have shading ring 125, shading ring 125 partly covers grid and partly covers drift region
105.Preferably, shading ring 125 can be metal or alloy material.Shading ring 125 reduces spike electric field using field plate effect, from
And increase voltage endurance capability, further increase hot carrier resistance.
In the following, the illustrative methods in conjunction with Fig. 2 to Figure 14 description according to the manufacture LDMOS device structure 10 of the application, Fig. 2
It is the gradually diagram for showing the exemplary production method of the LDMOS device structure 10 according to the application to Figure 14.
In the present embodiment, for convenience of description and it can be readily appreciated that using the first conduction type as p-type, the second conductive-type
Type be N-type for come illustrate the utility model production method embodiment.It will be understood by those skilled in the art that when the first conduction
As long as the type of type is N-type when being p-type corresponding conversion ions.
In the present embodiment, see in Fig. 2 first, prepare 0.005~0.015cm of resistivity-3Heavy doping P-type silicon lining
Bottom 101 grows 10 on substrate 10114~1015cm-2, with a thickness of 9 μm of p-type epitaxial layers 103.Trap is formed in epitaxial layer 103
Area 109, the surface of well region 109 from epitaxial layer 103 extend in substrate 101.Specifically, to 109 corresponding region of well region carry out B from
Sub- heavily-doped implant promotes the well region of 450~500mins formation p-type heavy doping using disposable 1050~1150 DEG C of high temperature
109。
In Fig. 3, channel region 107 close to drain terminal part carry out shallow ridges it is groove etched, etching depthIt is formed
Groove 115-1 as shown in Figure 2.
In Fig. 4 the step of, the growth thickness above epitaxial layer 103Oxide layer 127.
In Fig. 5, the oxide layer 127-1 on 103 surface of epitaxial layers is gone by photoetching and dry etching, to form ditch
Slot filling region 115.
In Fig. 6, second of growth thicknessOxide layer 127-2, as gate insulating layer.In grid
Above insulating layer 127-2 accumulation and be lithographically formed with a thickness ofPolysilicon layer, photoetching and dry etching are formed
Polysilicon gate 121-1, as shown in Figure 7.
In fig. 8, it carries out N-type to drift region 105 to be lightly doped, it is preferable that drift region concentration can be 1012~1013cm-2, energy be 50keV~200keV P ion inject.Next, forming P-type channel area 107, it is preferable that utilize polysilicon gate
It is 10 that pole autoregistration, which carries out dosage,12~1014cm-2Energy is the p-type B foreign ion injection of 30keV, be can use thereafter primary
Property 900~1050 DEG C of high temperature promote 80~120mins to form P-type channel areas 107 and drift region 105, drift region 105 and channel
Area 107 is adjacent, so that the channel region 107 formed is between drift region 105 and well region 109.It will be understood by those skilled in the art that
N-type doping and the p-type doping of formation can be not limited to ion described above, other ions are also possible.
In Fig. 9, grid curb wall 123 is made using photoetching process, grid curb wall 123 can be nitride material.
In Figure 10, drain region 111 and source region 113 are formed.Preferably, channel region 107 is located at polysilicon gate 121-1 and grid
123 lower section of side wall.It is 4 × 10 followed by the dosage of drain region and source region15~6 × 1015cm-2, energy be 80~120keV
N-type As ion implanting.Finally with 1000~1100 DEG C of disposable short annealing activation source regions 113 and drain region 111.This field
It should be understood to the one skilled in the art that for the ion implanting of source region 113 and drain region 111, there is no sequence requirements.
In Figure 11, opening is formed on gate insulating layer 127-2 using mask photolithographic process with partially exposed source region
113 and drain region 111.Again utilize photoetching, on open area and polysilicon gate 121-1 formed metal silicide layer 129-1,
121-2 and 129-3 forms Ohmic contact to form being electrically connected for each pole metal and silicon face.Preferably, metal silicide
Layer 129-1,121-2 and 129-3 can be tungsten silicide layer 129-1,121-2 and 129-3.In addition, on polysilicon gate 121-1
It forms metal silicide layer 121-2 and is formed by grid 121 and forming being electrically connected at the same time it can also dropping of metal and polysilicon
Low 121 resistance of grid, to increase switching speed.
In Figure 12, accumulation thickness againDielectric layer 127-3.
In Figure 13, accumulation tungsten or Titanium and are dry-etched in the one of the close drain electrode to form grid 121 at photoetching
Side forms shading ring.And in Figure 14, depositDielectric layer 127-4.The formation of shading ring can significantly change
The characteristics such as breakdown voltage, the conducting resistance of kind device, increase voltage endurance capability, further increase hot carrier resistance.
Finally, opening is formed on dielectric layer 127-4 using photoetching, exposing metal silicide layer 129-1 and 129-3,
Source electrode 119 and drain electrode 117 are formed on metal silicide layer 129-1 and 129-3, to form LDMOS device structure shown in FIG. 1
10。
Obviously, the above embodiments of the present invention is merely examples for clearly illustrating the present invention, and
It is not limitations of the embodiments of the present invention, for those of ordinary skill in the art, in above description
On the basis of can also make other variations or changes in different ways, all embodiments can not be exhaustive here,
It is all to belong to obvious changes or variations that the technical solution of the utility model is extended out still in the utility model
The column of protection scope.
Claims (6)
1. a kind of LDMOS device structure, comprising:
The substrate of first conduction type,
Form the epitaxial layer of the first conduction type over the substrate；
It is formed in the drift region of the second conduction type in the epitaxial layer；
The well region of first conduction type extends in the substrate from the surface of the epitaxial layer；
The channel region of first conduction type is formed in the drift region and between the drift region and the well region；
The source region of second conduction type is located in the well region and the channel region；And
The drain region of second conduction type is located in the drift region,
Grid above the channel region, is formed with gate insulating layer therebetween；
It is characterized in that,
Wherein, be also formed with groove near surface from the epitaxial layer, cover to the trench portions drift region and
The channel region, the trench fill region that the trench fill has oxide to constitute.
2. LDMOS device structure as described in claim 1, which is characterized in that first conduction type is p-type, described the
Two conduction types are N-type；Or first conduction type is N-type, second conduction type is p-type.
3. LDMOS device structure as described in claim 1, which is characterized in that the depth of the groove is
4. LDMOS device structure as described in claim 1, which is characterized in that the LDMOS device structure further includes gate electrode side
Wall is located at the grid two sides.
5. LDMOS device structure as described in claim 1, which is characterized in that the grid is exhausted including being formed in the grid
Polysilicon layer in edge layer and the metal silicide layer being formed on the polysilicon layer.
6. LDMOS device structure as described in claim 1, which is characterized in that the LDMOS device structure further include:
Cover the dielectric layer of the drift region surface and the gate surface；
The shading ring of the grid and the drift region is partly covered in the insulating layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201821139718.9U CN208861995U (en) | 2018-07-18 | 2018-07-18 | A kind of LDMOS device structure |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201821139718.9U CN208861995U (en) | 2018-07-18 | 2018-07-18 | A kind of LDMOS device structure |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109119472A (en) * | 2018-07-18 | 2019-01-01 | 北京顿思集成电路设计有限责任公司 | A kind of LDMOS device structure and preparation method thereof |
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2018
- 2018-07-18 CN CN201821139718.9U patent/CN208861995U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109119472A (en) * | 2018-07-18 | 2019-01-01 | 北京顿思集成电路设计有限责任公司 | A kind of LDMOS device structure and preparation method thereof |
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