CN110010473A - A kind of LDMOS device and production method - Google Patents
A kind of LDMOS device and production method Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 43
- 238000009413 insulation Methods 0.000 claims abstract description 13
- 150000002500 ions Chemical class 0.000 claims description 21
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 18
- 239000002184 metal Substances 0.000 claims description 12
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 10
- 229910021332 silicide Inorganic materials 0.000 claims description 9
- 238000005516 engineering process Methods 0.000 claims description 8
- 238000000034 method Methods 0.000 claims description 8
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- 230000004888 barrier function Effects 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 108091006146 Channels Proteins 0.000 description 30
- 238000001259 photo etching Methods 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000003071 parasitic effect Effects 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 238000009825 accumulation Methods 0.000 description 3
- 238000004891 communication Methods 0.000 description 3
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 238000000137 annealing Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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Abstract
It includes: the substrate of the first conduction type that the present invention, which discloses a kind of LDMOS device and production method, the LDMOS device,；Epitaxial layer on the substrate；Drift region on the epitaxial layer；Well region on the epitaxial layer；On surface of the epitaxial layer far from the substrate and in the channel region between the drift region and the well region；Source region between the well region and the channel region；Bonding pad in the source region and the channel region；Drain region in the drift region；Gate insulating layer on surface of the channel region far from the epitaxial layer；The grid of side positioned at the gate insulating layer far from the epitaxial layer；And the outer insulation on covering surface and the grid surface far from the epitaxial layer of the drift region far from the epitaxial layer.The present invention can satisfy the reliability and anti-static ability of higher level.
Description
Technical field
The present invention relates to technical field of semiconductors, more particularly to a kind of LDMOS device and production method.
Background technique
Cross bimoment (Lateral Double Diffused
It MOSFET is) that a kind of market demand is big, the wide radio-frequency power amplifier part of development prospect.In Radio-Frequency Wireless Communication field, base
It stands and long range transmitter almost all uses silicon substrate LDMOS high-capacity transistor；In addition, LDMOS is also widely used for radio frequency
Amplifier, such as the communications field HF, VHF and UHF, pulse radar, industry, science and medical applications, aviation electronics and communication system
Equal fields.
Since LDMOS has many advantages, such as high-gain, High Linear, high voltage, high-output power and is easy to CMOS technology compatibility,
Silicon substrate ldmos transistor has become a new hot spot of radio frequency semiconductor power device.But in view of the special applications side of LDMOS
Formula, LDMOS need use in variety classes Amplifier Design, it is therefore desirable to its reliability for meeting higher level and prevent quiet
Electric energy power.
Summary of the invention
The purpose of the present invention is to provide a kind of LDMOS device and production methods, can satisfy the reliable of higher level
Property and anti-static ability.
In order to achieve the above objectives, first aspect present invention proposes a kind of LDMOS device, comprising:
The substrate of first conduction type；
The epitaxial layer of the first conduction type on the substrate；
The drift region of the second conduction type on surface of the epitaxial layer far from the substrate；
Positioned at surface of the epitaxial layer far from the substrate and extend to the first conduction type on the substrate surface
Well region；
On surface of the epitaxial layer far from the substrate and in the between the drift region and the well region
The channel region of one conduction type；
The source region of the second conduction type between the well region and the channel region；
The bonding pad of the second conduction type in the source region and the channel region；
The drain region of the second conduction type in the drift region；
Gate insulating layer on surface of the channel region far from the epitaxial layer；
The grid of side positioned at the gate insulating layer far from the epitaxial layer；And
Cover surface and grid surface far from the epitaxial layer of the drift region far from the epitaxial layer
Outer insulation.
It preferably, further include screen that is interior positioned at the outer insulation and partially covering the drift region and the grid
Cover ring.
Preferably, first conduction type is p-type, and second conduction type is N-type；Or
First conduction type is N-type, and second conduction type is p-type.
Preferably, the grid includes polycrystalline silicon grid layer and the metal silicide that is formed on the polycrystalline silicon grid layer.
Preferably, the two sides of the grid are formed with the grid curb wall of silicon nitride material.
Preferably, the bonding pad is the medium-doped area of the second conduction type；
Wherein, the forming step of the bonding pad includes:
The B ion that the first conduction type is injected using polycrystalline silicon grid layer self-registered technology, diffuses to form channel region；
The As ion of the intermediate concentration of the second conduction type is injected again by self-registered technology；
The As ion of heavy doping is carried out using the grid curb wall as barrier layer, forms source region；
Medium-doped As ion between the source region and the channel region is bonding pad.
The production method that second aspect of the present invention proposes a kind of LDMOS device according to, comprising the following steps:
The epitaxial layer of the first conduction type is formed in the side of the substrate；
The drift region of the second conduction type is formed on surface of the epitaxial layer far from the substrate；
The first conductive-type extended on the substrate surface is formed on surface of the epitaxial layer far from the substrate
The well region of type；
It is formed on surface of the epitaxial layer far from the substrate in the between the drift region and the well region
The channel region of one conduction type；
The source region of the second conduction type is formed between the well region and the channel region；
The bonding pad of the second conduction type is formed between the source region and the channel region；
The drain region of the second conduction type is formed in the drift region；
Gate insulating layer is formed on surface of the channel region far from the epitaxial layer；
Grid is formed far from the side of the epitaxial layer in the gate insulating layer；
The shape on surface and grid surface far from the epitaxial layer of the drift region far from the epitaxial layer
At outer insulation.
It preferably, further include having to be formed with the part covering drift region and the grid in the outer insulation
Shading ring the step of.
Preferably, further include the steps that having and be formed with the grid curb wall of silicon nitride material in the two sides of the grid.
Preferably, first conduction type is p-type, and second conduction type is N-type；Or
First conduction type is N-type, and second conduction type is p-type.
Beneficial effects of the present invention are as follows:
Technical solution of the present invention provides a kind of LDMOS device and production method, between channel region and source region
Bonding pad is formed, bonding pad can be effectively reduced LDMOS endobiosis transistor common emitter gain, effectively prevent parasitic crystal
Pipe is opened, and prevents electric current caused by opening because of parasitic transistor from burning, to effectively increase the reliability of device and prevent quiet
Electric energy power.
Detailed description of the invention
Specific embodiments of the present invention will be described in further detail with reference to the accompanying drawing.
Fig. 1 shows a kind of structural schematic diagram of LDMOS device of one embodiment of the present of invention proposition；
Fig. 2 shows a kind of step flow charts of the production method of LDMOS device of another embodiment of the invention proposition；
Fig. 3-Figure 11 shows a kind of gradually diagram of the production method of LDMOS device.
In figure: 10, LDMOS device；101, substrate；103, epitaxial layer；105, drift region；107, channel region；109, well region；
111, drain region；112, bonding pad；113, source region；121, grid；121-1, polycrystalline silicon grid layer；121-2, metal silicide；123,
Grid curb wall；125, shading ring；127, outer insulation；127-3, dielectric layer；129, gate insulating layer；129-1, source region are opened
Mouthful；129-3, drain region opening.
Specific embodiment
In order to illustrate more clearly of the present invention, the present invention is done further below with reference to preferred embodiments and drawings
It is bright.Similar component is indicated in attached drawing with identical appended drawing reference.It will be appreciated by those skilled in the art that institute is specific below
The content of description is illustrative and be not restrictive, and should not be limited the scope of the invention with this.
Fig. 1 shows a kind of structural schematic diagram of LDMOS device of one embodiment of the present of invention proposition, as shown in Figure 1, institute
State LDMOS device include the substrate of the first conduction type, the epitaxial layer of the first conduction type, the second conduction type drift region,
The connection of the well region of first conduction type, the channel region of the first conduction type, the source region of the second conduction type, the second conduction type
Area, the drain region of the second conduction type, grid and outer insulation.
Specifically, epitaxial layer is located on substrate and the doping concentration of substrate is greater than the doping concentration of epitaxial layer, drift about position
In on surface of the epitaxial layer far from the substrate, well region is located on surface of the epitaxial layer far from the substrate and extends to institute
State on substrate surface, and channel region is located on surface of the epitaxial layer far from the substrate and in the drift region with it is described
Between well region, between the well region and the channel region, bonding pad is located in the source region and the channel region source region,
Drain region is located in the drift region, and grid is located on surface of the channel region far from the epitaxial layer, and outer insulation is covered on institute
It states on the surface of surface and the grid far from the epitaxial layer of the drift region far from the epitaxial layer.
It should be understood that the first conduction type can be p-type, the second conduction type can be N-type.Optionally, first
Conduction type can be N-type, and the second conduction type can be p-type.Those skilled in the art can need to select according to product.
The content according to the present embodiment, the bonding pad in the source region and the channel region, can significantly drop
The common emitter gain of the parasitic transistor formed between low source region, channel region and drift region effectively prevents parasitic transistor from opening
Electric current caused by opening is burnt, to effectively increase the reliability and anti-static ability of device.
In addition, it will be seen from figure 1 that further including being located at the channel region far from described outer in content described in the present embodiment
Prolonging the gate insulating layer on the surface of layer, the grid is located at side of the gate insulating layer far from the epitaxial layer, and
Grid can also be including polycrystalline silicon grid layer and the metal silicide being formed on the polycrystalline silicon grid layer, so that grid resistance drops
It is low, obtain better frequency characteristic.
Further, further, it could be formed with the grid curb wall of silicon nitride material in grid two sides, it can be more preferable
Formation gate metal silicide, can also have a shading ring in the side of the close drain electrode of grid, shading ring is located at described outer
In layer insulating and part covers the drift region and the grid, and in actual use, shading ring can use field plate effect
Spike electric field should be reduced, to increase voltage endurance capability.
Further, the bonding pad is the medium-doped area of the second conduction type；
Wherein, the forming step of the bonding pad includes:
The B ion that the first conduction type is injected using polycrystalline silicon grid layer self-registered technology, diffuses to form channel region；
The As ion of the intermediate concentration of the second conduction type is injected again by self-registered technology；
The As ion of heavy doping is carried out using the grid curb wall as barrier layer, forms source region；
Medium-doped As ion between the source region and the channel region is bonding pad.
It should be noted that in this step, the AS ion of intermediate concentration doping, last benefit are injected by self-registered technology
It uses grid curb wall to carry out the As ion of heavy doping as barrier layer, will form between the channel region and source level below grid curb wall
Etc. doping concentrations bonding pad, herein, barrier layer is not limited only to grid curb wall, can also be by being formed the step for photoetching
Barrier layer, to form various sizes of bonding pad.
Fig. 2 shows another embodiment of the invention propose the production method according to DMOS device step flow chart,
As shown in Figure 2, which comprises
The epitaxial layer of the first conduction type is formed in the side of the substrate；
The drift region of the second conduction type is formed on surface of the epitaxial layer far from the substrate；
The first conductive-type extended on the substrate surface is formed on surface of the epitaxial layer far from the substrate
The well region of type；
It is formed on surface of the epitaxial layer far from the substrate in the between the drift region and the well region
The channel region of one conduction type；
The source region of the second conduction type is formed between the well region and the channel region；
The bonding pad of the second conduction type is formed between the source region and the channel region；
The drain region of the second conduction type is formed in the drift region；
Gate insulating layer is formed on surface of the channel region far from the epitaxial layer；
Grid is formed far from the side of the epitaxial layer in the gate insulating layer；
The shape on surface and grid surface far from the epitaxial layer of the drift region far from the epitaxial layer
At outer insulation.
It further include having to be formed in the outer insulation partially to cover in a preferred embodiment of the present embodiment
The step of covering the shading ring of the drift region and the grid.
It further include having to be formed with silicon nitride in the two sides of the grid in another preferred embodiment of the present embodiment
The step of grid curb wall of material.
In the following, Fig. 3 to Figure 11 is the method in conjunction with the production method that Fig. 3 to Figure 11 is further described LDMOS device
Gradually diagram.
In the example of this production method, for convenience of description and it can be readily appreciated that using the first conduction type as p-type, the
Two conduction types be N-type for come illustrate the present embodiment propose production method.It is led it will be understood by those skilled in the art that working as first
As long as the type of electric type is N-type when being p-type corresponding conversion ions.
See in Fig. 3 first, prepare the P-type silicon substrate of heavy doping, on substrate growing P-type epitaxial layer, be lithographically formed well region,
High temperature diffusion propulsion is connected to substrate.
In Fig. 4 the step of, the growth thickness above epitaxial layerOxide layer as gate insulating layer.
Above gate insulating layer accumulation and be lithographically formed with a thickness ofPolysilicon layer, further by photoetching and dry
Method etching, forms polycrystalline silicon grid layer, as shown in Figure 7.
In Fig. 5, N-type is carried out to drift region and is lightly doped, it is preferable that drift region concentration can be 1012~1013cm-2, energy
The P ion that amount is 50keV~200keV injects.Next, forming P-type channel area, it is preferable that utilize polycrystalline silicon grid layer autoregistration
Carrying out dosage is 1012~1014cm-2Energy is the p-type B foreign ion injection of 30keV-100keV, be can use thereafter disposable
900~1050 DEG C of high temperature promote the formation P-type channel area 80~120mins and drift region, drift region adjacent with channel region.This field
It should be understood to the one skilled in the art that n-type doping and the p-type doping formed can be not limited to ion described above, other ions are also can
With.
Carrying out dosage using polycrystalline silicon grid layer autoregistration in Fig. 6 is 1013~1014cm-2Energy is that the N-type As of 45keV is miscellaneous
Matter ion implanting forms bonding pad.
In Fig. 7, grid curb wall is made using photoetching process.
In fig. 8, drain region and source region are formed.Preferably, bonding pad is eventually formed between source region and channel region, is connected simultaneously
It meets area to be located at below grid curb wall, channel region is located at below polycrystalline silicon grid layer.It is 10 followed by the dosage of drain region and source region14
~6 × 1015cm-2, energy be 80~120keV N-type As ion implanting.Finally with 1000~1100 DEG C of disposable short annealings
Activate source region, drain region.
In Fig. 9, source region opening and drain region opening are formed on gate insulating layer using mask photolithographic process with part
Exposure source region and drain region.Photoetching is utilized again, forms metal silicide on open area and polycrystalline silicon grid layer, it is each to be formed
Pole metal and silicon face are electrically connected, and form Ohmic contact.It is formed in addition, forming metal silicide on polycrystalline silicon grid layer
Grid forming metal and while being electrically connected of polysilicon, the resistance of grid can also be reduced, to increase switch speed
Degree.
In Figure 10, accumulation thickness againDielectric layer.
In Figure 11, accumulation metal silicide, photoetching is formed with the side for being dry-etched in the close drain electrode to form grid
Shading ring.And it is deposited on shading ring againDielectric layer, to form outer insulation.The shape of shading ring
At can significantly improve the characteristics such as breakdown voltage, the conducting resistance of device, increase voltage endurance capability.Finally, using photoetching in medium
Opening is formed on layer, exposing metal silicide forms source electrode and drain electrode on metal silicide, to be formed shown in FIG. 1
LDMOS device.
Obviously, the above embodiment of the present invention be only to clearly illustrate example of the present invention, and not be pair
The restriction of embodiments of the present invention may be used also on the basis of the above description for those of ordinary skill in the art
To make other variations or changes in different ways, all embodiments can not be exhaustive here, it is all to belong to this hair
The obvious changes or variations that bright technical solution is extended out are still in the scope of protection of the present invention.
Claims (10)
1. a kind of LDMOS device characterized by comprising
The substrate of first conduction type；
The epitaxial layer of the first conduction type on the substrate；
The drift region of the second conduction type on surface of the epitaxial layer far from the substrate；
Positioned at surface of the epitaxial layer far from the substrate and extend to the trap of the first conduction type on the substrate surface
Area；
It is led on surface of the epitaxial layer far from the substrate and in first between the drift region and the well region
The channel region of electric type；
The source region of the second conduction type between the well region and the channel region；
The bonding pad of the second conduction type in the source region and the channel region；
The drain region of the second conduction type in the drift region；
Gate insulating layer on surface of the channel region far from the epitaxial layer；
The grid of side positioned at the gate insulating layer far from the epitaxial layer；And
Cover the outer layer on surface and grid surface far from the epitaxial layer of the drift region far from the epitaxial layer
Insulating layer.
2. LDMOS device according to claim 1, which is characterized in that further include and portion interior positioned at the outer insulation
Divide the shading ring for covering the drift region and the grid.
3. LDMOS device according to claim 1, which is characterized in that first conduction type be p-type, described second
Conduction type is N-type；Or
First conduction type is N-type, and second conduction type is p-type.
4. LDMOS device according to claim 1, which is characterized in that the grid includes polycrystalline silicon grid layer and formation
Metal silicide on the polycrystalline silicon grid layer.
5. LDMOS device according to claim 4, which is characterized in that the two sides of the grid are formed with silicon nitride material
Grid curb wall.
6. LDMOS device according to claim 5, which is characterized in that the bonding pad is the medium of the second conduction type
Doped region；
Wherein, the forming step of the bonding pad includes:
The B ion that the first conduction type is injected using polycrystalline silicon grid layer self-registered technology, diffuses to form channel region；
The As ion of the intermediate concentration of the second conduction type is injected again by self-registered technology；
The As ion of heavy doping is carried out using the grid curb wall as barrier layer, forms source region；
Medium-doped As ion between the source region and the channel region is bonding pad.
7. a kind of production method of LDMOS device according to claim 1 to 6, which is characterized in that including with
Lower step:
The epitaxial layer of the first conduction type is formed in the side of the substrate；
The drift region of the second conduction type is formed on surface of the epitaxial layer far from the substrate；
The first conduction type extended on the substrate surface is formed on surface of the epitaxial layer far from the substrate
Well region；
It is formed on surface of the epitaxial layer far from the substrate and is led in first between the drift region and the well region
The channel region of electric type；
The source region of the second conduction type is formed between the well region and the channel region；
The bonding pad of the second conduction type is formed between the source region and the channel region；
The drain region of the second conduction type is formed in the drift region；
Gate insulating layer is formed on surface of the channel region far from the epitaxial layer；
Grid is formed far from the side of the epitaxial layer in the gate insulating layer；
It is formed on surface and grid surface far from the epitaxial layer of the drift region far from the epitaxial layer outer
Layer insulating.
8. the method according to the description of claim 7 is characterized in that further including having to be formed with part in the outer insulation
The step of covering the shading ring of the drift region and the grid.
9. the method according to the description of claim 7 is characterized in that further including having to be formed with silicon nitride in the two sides of the grid
The step of grid curb wall of material.
10. described second is conductive the method according to the description of claim 7 is characterized in that first conduction type is p-type
Type is N-type；Or
First conduction type is N-type, and second conduction type is p-type.
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