CN104269437A - LDMOS device with double-layer shielding rings and manufacturing method of LDMOS device - Google Patents

LDMOS device with double-layer shielding rings and manufacturing method of LDMOS device Download PDF

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CN104269437A
CN104269437A CN201410457683.3A CN201410457683A CN104269437A CN 104269437 A CN104269437 A CN 104269437A CN 201410457683 A CN201410457683 A CN 201410457683A CN 104269437 A CN104269437 A CN 104269437A
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region
shading ring
channel region
polycrystalline silicon
grid polycrystalline
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杜寰
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SHANGHAI LIANXING ELECTRONIC CO Ltd
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SHANGHAI LIANXING ELECTRONIC CO Ltd
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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Abstract

The invention provides an LDMOS device with double-layer shielding rings and a manufacturing method of the LDMOS device, and belongs to the field of integrated circuit manufacture. The LDMOS device comprises a P+ silicon substrate, a P-type epitaxial region formed on the P+ silicon substrate in an epitaxial mode, a channel region, a source region, a drift region, a drain region, grid polycrystalline silicon, the first-layer shielding ring and the second-layer shielding ring. The shielding rings are additionally arranged in the LDMOS device, the breakdown voltages of the radio frequency LDMOS device are changed, and the performance of the radio frequency LDMOS device is optimized.

Description

A kind of have LDMOS device of double layer screen ring and preparation method thereof
Technical field
The invention belongs to integrated circuit fields, particularly relate to and a kind of there is LDMOS device of double layer screen ring and preparation method thereof.
Background technology
Horizontal dual pervasion field effect pipe (Lateral Double-diffused MOS, LDMOS) is the RF power device that a kind of market demand is large, development prospect is wide.In Radio-Frequency Wireless Communication field, base station and long range transmitter almost all use silica-based LDMOS high-capacity transistor; In addition, LDMOS is also widely used in radio frequency amplifier, as fields such as HF, VHF and UHF communication system, pulse radar, industry, science and medical applications, aviation electronics and WiMAXTM communication systems.Due to LDMOS have high-gain, High Linear, high withstand voltage, high-output power and easily with the advantage such as CMOS technology compatibility, silica-based ldmos transistor has become a new focus of radio frequency semiconductor power device.As compared to SiGe with GaAs technique, although the high frequency performance of SiLDMOS technology and noiseproof feature are not optimum, but its technique is the most ripe, cost is minimum, power consumption is minimum, application is also extensive, especially along with the scaled down of device feature size, frequency and the noise characteristic of ldmos transistor also improve gradually, therefore in the long run, silica-based LDMOS radio circuit will be the trend of future development.
As shown in Figure 1, be the structural representation of existing radio frequency LDMOS device; The basic structure of existing radio frequency LDMOS device comprises:
The substrate that namely P+ silicon substrate 101 mixes high concentration p type impurity and the P-epitaxial loayer 102 be formed at above described P+ silicon substrate; The resistivity of described P+ silicon substrate 101 is 0.01 ohmcm ~ 0.02 ohmcm, the thickness of described P-epitaxial loayer 102 is arranged according to the requirement of device withstand voltage is different with doping content, if device withstand voltage is 60 volts, the thickness of described P-epitaxial loayer 102 is about 5 microns ~ 8 microns.
Utilize the P+ sinking layer (P+SINKER) 103 injecting and diffuse to form, this P+ sinking layer 103 is through described P-epitaxial loayer 102 and the bottom of described P+ sinking layer 103 enters into described P+ silicon substrate 101.
P trap 104, this P trap 104 is for the formation of the channel region of device.
Grid oxic horizon and grid polycrystalline silicon 108, be covered in the top of described P trap 104, formed channel region by the described P trap 104 of described grid polycrystalline silicon 108.
Drift region 105, is made up of the N-doped region be formed in described P-epitaxial loayer 102, and the side of described drift region 105 and described grid polycrystalline silicon 108 is adjacent.
Source region 106, is made up of a N+ doped region, and the opposite side autoregistration of described grid polycrystalline silicon 108.
Drain region 107, is made up of a N+ doped region, and a segment distance of being separated by of described grid polycrystalline silicon 108, and is be connected with described P trap 104 by described drift region 105.
Source S, drain D and grid G is drawn by metallic pattern 109.Include more metal layers from drain region 107 to drain D and for the contact hole of the connection adjacent metal and through hole, wherein contact hole is used for the connection of drain region 107 and first layer metal, through hole is used for the connection between metal level.More metal layers is also included and for the contact hole of the connection between adjacent metal and through hole between source region 106 and source S, source S also can be the metal 110 of silicon chip back side, also includes more metal layers and for the contact hole of the connection between adjacent metal and through hole between grid polycrystalline silicon 108 and grid G.
Be formed with back metal 110 overleaf after described P+ silicon substrate 101 is thinning, described back metal 110 to be connected with described source S by described P+ silicon substrate 101, described P+ sinking layer 103 or as source electrode.
Puncture voltage is one of most important static parameter of LDMOS, and good voltage endurance is the important embodiment of LDMOS device reliability.Planar technique is adopted to make LDMOS device, because P-N junction surface is subject to the impact of positive charge and Si/SiO2 interfacial state in radius of curvature, oxide layer, the electric field of P-N junction surface is increased, P-N junction punctures first in surface generation, in order to the technology improving the reduction surface field that puncture voltage is taked at P-N junction edge is called knot terminal technology.The invention provides a kind of method that change by drift region implantation dosage improves radio frequency LDMOS puncture voltage, the method can be optimized major parameters such as the threshold voltage to device, puncture voltage and frequency characteristics, thus designs the RF LDMOS device with excellent properties index request.
Summary of the invention
The object of the embodiment of the present invention is that providing a kind of has LDMOS device of double layer screen ring and preparation method thereof, to solve the problem cannot optimizing radio-frequency devices puncture voltage of prior art.
The embodiment of the present invention is achieved in that a kind of LDMOS device with double layer screen ring, and described device comprises:
P+ silicon substrate;
The P type epi region that extension is formed on described P+ silicon substrate;
The channel region be made up of the P trap be formed in described P type epi region;
The source region be made up of the N+ doped region be formed in described P trap;
The drift region be made up of the N-doped region be formed in described P type epi region, described drift region is adjacent with described channel region;
The drain region be made up of the N+ doped region be formed in described drift region, described drain region and described channel region are separated by a lateral separation;
The grid polycrystalline silicon be made up of the polysilicon be formed at above described channel region, isolate between described grid polycrystalline silicon and described channel region and have grid oxic horizon, the side of described grid polycrystalline silicon and the autoregistration of described source region, the opposite side edge of described grid polycrystalline silicon is more than or equal to the edge that connects of described channel region and described drift region;
The shading ring be made up of tungsten silicon, described shading ring comprises ground floor shading ring and second layer shading ring.
Another object of the embodiment of the present invention is to provide a kind of preparation method with the LDMOS device of double layer screen ring, and described method comprises:
Preparation P+ silicon substrate;
P type epi region is formed by extension on described P+ silicon substrate;
By being formed at the P trap composition channel region in described P type epi region;
By being formed at the composition source region, N+ doped region in described P trap;
By being formed at the composition drift region, N-doped region in described P type epi region, described drift region is adjacent with described channel region;
By being formed at the composition drain region, N+ doped region in described drift region, described drain region and described channel region are separated by a lateral separation;
By being formed at the polysilicon composition grid polycrystalline silicon above described channel region, isolate between described grid polycrystalline silicon and described channel region and have grid oxic horizon, the side of described grid polycrystalline silicon and the autoregistration of described source region, the opposite side edge of described grid polycrystalline silicon is more than or equal to the edge that connects of described channel region and described drift region;
By the shading ring that tungsten silicon is formed, described shading ring comprises ground floor shading ring and second layer shading ring.
The embodiment of the present invention, by adding double layer screen ring in LDMOS device, making the puncture voltage of LDMOS device be changed, optimizing the performance of radio frequency LDMOS device.
Accompanying drawing explanation
In order to be illustrated more clearly in the technical scheme in the embodiment of the present invention, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is the structure chart of the radio frequency LDMOS device that prior art provides;
Fig. 2 is the LDMOS device structural representation obtained through ISE TCAD process simulation that the embodiment of the present invention provides;
Fig. 3 is the structure chart with the LDMOS device of double layer screen ring that the embodiment of the present invention provides.
Embodiment
In order to make object of the present invention, technical scheme and advantage clearly understand, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, be not intended to limit the present invention.
In order to technical solutions according to the invention are described, be described below by specific embodiment.
Embodiment one
Be illustrated in figure 2 the LDMOS device structural representation obtained through ISE TCAD process simulation that the embodiment of the present invention provides, the structure chart of this LDMOS device, as shown in Figure 3, for convenience of explanation, the part relevant to the embodiment of the present invention be only shown, comprise:
Resistivity is 0.05 ~ 0.15 Ω/cm 3p+ silicon substrate.
In embodiments of the present invention, radio frequency LDMOS (Lateral Double-diffused MOS, being called for short: horizontal dual pervasion field effect pipe) device is produced on P+ silicon substrate, and first this radio frequency LDMOS device comprises: resistivity is 0.05 ~ 0.15 Ω/cm 3p+ silicon substrate.
The thickness that extension is formed on described P+ silicon substrate is 9 μm, doping content is 6*10 14cm -3~ 8*10 14cm -3p type epi region.
In embodiments of the present invention, on this P+ silicon substrate, have that the thickness formed by extension is 9 μm, doping content is 6*10 14cm -3~ 8*10 14cm -3p type epi region.
The B impurity implantation dosage be made up of the P trap be formed in described P type epi region is 2*10 13cm -2~ 4*10 13cm -2, energy is 40 ~ 60Kev, 1000 ~ 1100 DEG C of high temperature advance the times to be the channel region of 40 ~ 60min.
In embodiments of the present invention, this radio frequency LDMOS device also comprises B impurity implantation dosage is 2*10 13cm -2~ 4*10 13cm -2, energy is 40 ~ 60Kev, 1000 ~ 1100 DEG C of high temperature advance the times to be the channel region of 40 ~ 60min.
The field oxygen thickness be made up of the N+ doped region be formed in described P trap is the source region of 1.8 ~ 2.2 μm.
In embodiments of the present invention, this radio frequency LDMOS device also comprises the source region that an oxygen thickness is 1.8 ~ 2.2 μm.
The As impurity implantation dosage be made up of the N-doped region be formed in described P type epi region is 1.1*10 12cm -2~ 1.5*10 12cm -2, energy is 140 ~ 160Kev, 1000 ~ 1100 DEG C of high temperature advances the time to be 40 ~ 70min, length is 2 μm ~ 4 μm drift region, described drift region is adjacent with described channel region.
In embodiments of the present invention, this radio frequency LDMOS device also comprises As impurity implantation dosage is 1.1*10 12cm -2~ 1.5*10 12cm -2, energy is 140 ~ 160Kev, 1000 ~ 1100 DEG C of high temperature advances the time to be 40 ~ 70min, length is 2 μm ~ 4 μm drift region, wherein this drift region is adjacent with above-mentioned channel region.
The AS impurity implantation dosage be made up of the N+ doped region be formed in described drift region is 4*10 15cm -2~ 6*10 15cm -2, energy is the drain region of 80 ~ 120Kev, 900 ~ 1000 DEG C of rapid thermal treatment 30min, described drain region and described channel region are separated by a lateral separation.
In embodiments of the present invention, this radio frequency LDMOS device also comprises AS impurity implantation dosage is 4*10 15cm -2~ 6*10 15cm -2, energy is the drain region of 80 ~ 120Kev, 900 ~ 1000 DEG C of rapid thermal treatment 30min, wherein this drain region and above-mentioned channel region are separated by a lateral separation.
The gate oxide thickness be made up of the polysilicon be formed at above described channel region is polysilicon thickness is grid polycrystalline silicon, isolate between described grid polycrystalline silicon and described channel region and have grid oxic horizon, the side of described grid polycrystalline silicon and the autoregistration of described source region, the opposite side edge of described grid polycrystalline silicon is more than or equal to the edge that connects of described channel region and described drift region.
In embodiments of the present invention, this radio frequency LDMOS device also comprises gate oxide thickness and is polysilicon thickness is grid polycrystalline silicon, between this grid polycrystalline silicon and above-mentioned channel region, isolation has grid oxic horizon, the side of this grid polycrystalline silicon and above-mentioned source region are aimed at, and the opposite side edge of this grid polycrystalline silicon is more than or equal to the edge that connects of above-mentioned channel region and above-mentioned drift region.
The double layer screen ring be made up of tungsten silicon, the length of ground floor shading ring is 0.7 ~ 0.8 μm, and the length of second layer shading ring is 2.4 ~ 2.8 μm.
In embodiments of the present invention, this radio frequency LDMOS device also comprise by tungsten silicon form shading ring, this shading ring comprises ground floor length to be the shading ring of 0.7 ~ 0.8 μm and second layer length the be shading ring of 2.4 ~ 2.8 μm, in some preferred embodiments, the length of this ground floor shading ring is 0.75 μm, and the length of second layer shading ring is 2.7 μm.
By simulation process, the puncture voltage of radio frequency LDMOS device provided by the invention is changed, and the puncture voltage of radio frequency LDMOS device is optimized.
As a preferred embodiment of the present invention, described in there is shading ring LDMOS device comprise:
Resistivity is 0.08 Ω/cm 3p+ silicon substrate;
The thickness that extension is formed on described P+ silicon substrate is 9 μm, doping content is 7*10 14cm -3p type epi region;
The B impurity implantation dosage be made up of the P trap be formed in described P type epi region is 3*10 13cm -2, energy is 50Kev, 1050 DEG C of high temperature advance the times to be the channel region of 40 ~ 60min;
The field oxygen thickness be made up of the N+ doped region be formed in described P trap is the source region of 2 μm;
The As impurity implantation dosage be made up of the N-doped region be formed in described P type epi region is 1.2*10 12cm -2, energy is 150Kev, 1050 DEG C of high temperature advance the times to be the drift region of 60min, described drift region is adjacent with described channel region;
The AS impurity implantation dosage be made up of the N+ doped region be formed in described drift region is 5*10 15cm -2, energy is the drain region of 100Kev, 950 DEG C of rapid thermal treatment 30min, described drain region and described channel region are separated by a lateral separation;
The gate oxide thickness be made up of the polysilicon be formed at above described channel region is polysilicon thickness is grid polycrystalline silicon;
The double layer screen ring be made up of tungsten silicon, the length of ground floor shading ring is 0.7 μm, and the length of second layer shading ring is 2.6 μm.
By implementing the present embodiment, the puncture voltage of radio frequency LDMOS device can be 110V.
As another preferred embodiment of the present invention, described in there is shading ring LDMOS device comprise:
Resistivity is 0.07 Ω/cm 3p+ silicon substrate;
The thickness that extension is formed on described P+ silicon substrate is 9 μm, doping content is 8*10 14cm -3p type epi region;
The B impurity implantation dosage be made up of the P trap be formed in described P type epi region is 4*10 13cm -2, energy is 40Kev, 1050 DEG C of high temperature advance the times to be the channel region of 40min;
The field oxygen thickness be made up of the N+ doped region be formed in described P trap is the source region of 2.2 μm;
The As impurity implantation dosage be made up of the N-doped region be formed in described P type epi region is 1.3*10 12cm -2, energy is 160Kev, 1100 DEG C of high temperature advance the times to be the drift region of 50min, described drift region is adjacent with described channel region;
The AS impurity implantation dosage be made up of the N+ doped region be formed in described drift region is 6*10 15cm -2, energy is the drain region of 120Kev, 1000 DEG C of rapid thermal treatment 30min, described drain region and described channel region are separated by a lateral separation;
The gate oxide thickness be made up of the polysilicon be formed at above described channel region is polysilicon thickness is grid polycrystalline silicon;
The shading ring be made up of tungsten silicon, the length of ground floor shading ring is 0.75 μm, and the length of second layer shading ring is 2.7 μm.
By implementing the present embodiment, the puncture voltage of radio frequency LDMOS device can be 120V.
As another preferred embodiment of the present invention, described in there is shading ring LDMOS device comprise:
Resistivity is 0.05 Ω/cm 3p+ silicon substrate;
The thickness that extension is formed on described P+ silicon substrate is 9 μm, doping content is 6*10 14cm -3p type epi region;
The B impurity implantation dosage be made up of the P trap be formed in described P type epi region is 2*10 13cm -2, energy is 60Kev, 1000 DEG C of high temperature advance the times to be the channel region of 60min;
The field oxygen thickness be made up of the N+ doped region be formed in described P trap is the source region of 1.8 μm;
The As impurity implantation dosage be made up of the N-doped region be formed in described P type epi region is 1.2*10 12cm -2, energy is 150Kev, 1000 DEG C of high temperature advance the times to be the drift region of 50min, described drift region is adjacent with described channel region;
The AS impurity implantation dosage be made up of the N+ doped region be formed in described drift region is 4*10 15cm -2, energy is the drain region of 80Kev, 900 DEG C of rapid thermal treatment 30min, described drain region and described channel region are separated by a lateral separation;
The gate oxide thickness be made up of the polysilicon be formed at above described channel region is polysilicon thickness is grid polycrystalline silicon;
The double layer screen ring be made up of tungsten silicon, the length of ground floor shading ring is 0.8 μm, and the length of second layer shading ring is 2.5 μm.
By implementing the present embodiment, the puncture voltage of radio frequency LDMOS device can be 110V.
Embodiment two
The flow chart of the shading device preparation method that the embodiment of the present invention provides, said method comprising the steps of:
Preparation resistivity is 0.05 ~ 0.15 Ω/cm 3p+ silicon substrate;
Formed by extension on described P+ silicon substrate that thickness is 9 μm, doping content is 6*10 14cm -3~ 8*10 14cm -3p type epi region;
Forming B impurity implantation dosage by the P trap be formed in described P type epi region is 2*10 13cm -2~ 4*10 13cm -2, energy is 40 ~ 60Kev, 1000 ~ 1100 DEG C of high temperature advance the times to be the channel region of 40 ~ 60min;
By the source region that composition field, the N+ doped region oxygen thickness be formed in described P trap is 1.8 ~ 2.2 μm;
Forming As impurity implantation dosage by the N-doped region be formed in described P type epi region is 1.1*10 12cm -2~ 1.5*10 12cm -2, energy is 140 ~ 160Kev, 1000 ~ 1100 DEG C of high temperature advances the time to be 40 ~ 70min, length is 2 μm ~ 4 μm drift region, described drift region is adjacent with described channel region;
Forming AS impurity implantation dosage by the N+ doped region be formed in described drift region is 4*10 15cm -2~ 6*10 15cm -2, energy is the drain region of 80 ~ 120Kev, 900 ~ 1000 DEG C of rapid thermal treatment 30min, described drain region and described channel region are separated by a lateral separation;
By the polysilicon composition gate oxide thickness be formed at above described channel region be polysilicon thickness is grid polycrystalline silicon, isolate between described grid polycrystalline silicon and described channel region and have grid oxic horizon, the side of described grid polycrystalline silicon and the autoregistration of described source region, the opposite side edge of described grid polycrystalline silicon is more than or equal to the edge that connects of described channel region and described drift region;
Shading ring is formed, described shading ring comprises ground floor length to be the shading ring of 0.7 ~ 0.8 μm and second layer length the be shading ring of 2.4 ~ 2.8 μm by tungsten silicon.
By implementing the present embodiment, the puncture voltage of radio frequency LDMOS device can be optimized.
Those of ordinary skill in the art it is also understood that, the all or part of step realized in above-described embodiment method is that the hardware that can carry out instruction relevant by program has come, described program can be stored in a computer read/write memory medium, described storage medium, comprises ROM/RAM, disk, CD etc.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, all any amendments done within the spirit and principles in the present invention, equivalent replacement and improvement etc., all should be included within protection scope of the present invention.

Claims (8)

1. have a LDMOS device for shading ring, it is characterized in that, described device comprises:
P+ silicon substrate;
The P type epi region that extension is formed on described P+ silicon substrate;
The channel region be made up of the P trap be formed in described P type epi region;
The source region be made up of the N+ doped region be formed in described P trap;
The drift region be made up of the N-doped region be formed in described P type epi region, described drift region is adjacent with described channel region;
The drain region be made up of the N+ doped region be formed in described drift region, described drain region and described channel region are separated by a lateral separation;
The grid polycrystalline silicon be made up of the polysilicon be formed at above described channel region, isolate between described grid polycrystalline silicon and described channel region and have grid oxic horizon, the side of described grid polycrystalline silicon and the autoregistration of described source region, the opposite side edge of described grid polycrystalline silicon is more than or equal to the edge that connects of described channel region and described drift region;
The shading ring be made up of tungsten silicon, described shading ring comprises ground floor shading ring and second layer shading ring.
2. LDMOS device as claimed in claim 1, it is characterized in that, described device comprises:
Resistivity is 0.05 ~ 0.15 Ω/cm 3p+ silicon substrate;
The thickness that extension is formed on described P+ silicon substrate is 9 μm, doping content is 6*10 14cm -3~ 8*10 14cm -3p type epi region;
The B impurity implantation dosage be made up of the P trap be formed in described P type epi region is 2*10 13cm -2~ 4*10 13cm -2, energy is 40 ~ 60Kev, 1000 ~ 1100 DEG C of high temperature advance the times to be the channel region of 40 ~ 60min;
The field oxygen thickness be made up of the N+ doped region be formed in described P trap is the source region of 1.8 ~ 2.2 μm;
The As impurity implantation dosage be made up of the N-doped region be formed in described P type epi region is 1.1*10 12cm -2~ 1.5*10 12cm -2, energy is 140 ~ 160Kev, 1000 ~ 1100 DEG C of high temperature advances the time to be 40 ~ 70min, length is 2 μm ~ 4 μm drift region, described drift region is adjacent with described channel region;
The AS impurity implantation dosage be made up of the N+ doped region be formed in described drift region is 4*10 15cm -2~ 6*10 15cm -2, energy is the drain region of 80 ~ 120Kev, 900 ~ 1000 DEG C of rapid thermal treatment 30min, described drain region and described channel region are separated by a lateral separation;
The gate oxide thickness be made up of the polysilicon be formed at above described channel region is polysilicon thickness is grid polycrystalline silicon, isolate between described grid polycrystalline silicon and described channel region and have grid oxic horizon, the side of described grid polycrystalline silicon and the autoregistration of described source region, the opposite side edge of described grid polycrystalline silicon is more than or equal to the edge that connects of described channel region and described drift region;
The double layer screen ring be made up of tungsten silicon, the length of ground floor shading ring is 0.7 ~ 0.8 μm, and the length of second layer shading ring is 2.4 ~ 2.8 μm.
3. the LDMOS device as described in any one of claim 1 ~ 2, is characterized in that, the length of described ground floor shading ring is 0.75 μm, and the length of second layer shading ring is 2.7 μm.
4. the LDMOS device as described in any one of claim 1 ~ 2, is characterized in that, the puncture voltage of described LDMOS device is 120v.
5. have a preparation method for the LDMOS device of shading ring, it is characterized in that, described method comprises:
Preparation P+ silicon substrate;
P type epi region is formed by extension on described P+ silicon substrate;
By being formed at the P trap composition channel region in described P type epi region;
By being formed at the composition source region, N+ doped region in described P trap;
By being formed at the composition drift region, N-doped region in described P type epi region, described drift region is adjacent with described channel region;
By being formed at the composition drain region, N+ doped region in described drift region, described drain region and described channel region are separated by a lateral separation;
By being formed at the polysilicon composition grid polycrystalline silicon above described channel region, isolate between described grid polycrystalline silicon and described channel region and have grid oxic horizon, the side of described grid polycrystalline silicon and the autoregistration of described source region, the opposite side edge of described grid polycrystalline silicon is more than or equal to the edge that connects of described channel region and described drift region;
By the shading ring that tungsten silicon is formed, described shading ring comprises ground floor shading ring and second layer shading ring.
6. preparation method as claimed in claim 5, it is characterized in that, described method comprises:
Preparation resistivity is 0.05 ~ 0.15 Ω/cm 3p+ silicon substrate;
Formed by extension on described P+ silicon substrate that thickness is 9 μm, doping content is 6*10 14cm -3~ 8*10 14cm -3p type epi region;
Forming B impurity implantation dosage by the P trap be formed in described P type epi region is 2*10 13cm -2~ 4*10 13cm -2, energy is 40 ~ 60Kev, 1000 ~ 1100 DEG C of high temperature advance the times to be the channel region of 40 ~ 60min;
By the source region that composition field, the N+ doped region oxygen thickness be formed in described P trap is 1.8 ~ 2.2 μm;
Forming As impurity implantation dosage by the N-doped region be formed in described P type epi region is 1.1*10 12cm -2~ 1.5*10 12cm -2, energy is 140 ~ 160Kev, 1000 ~ 1100 DEG C of high temperature advances the time to be 40 ~ 70min, length is 2 μm ~ 4 μm drift region, described drift region is adjacent with described channel region;
Forming AS impurity implantation dosage by the N+ doped region be formed in described drift region is 4*10 15cm -2~ 6*10 15cm -2, energy is the drain region of 80 ~ 120Kev, 900 ~ 1000 DEG C of rapid thermal treatment 30min, described drain region and described channel region are separated by a lateral separation;
By the polysilicon composition gate oxide thickness be formed at above described channel region be polysilicon thickness is grid polycrystalline silicon, isolate between described grid polycrystalline silicon and described channel region and have grid oxic horizon, the side of described grid polycrystalline silicon and the autoregistration of described source region, the opposite side edge of described grid polycrystalline silicon is more than or equal to the edge that connects of described channel region and described drift region;
Shading ring is formed, described shading ring comprises ground floor length to be the shading ring of 0.7 ~ 0.8 μm and second layer length the be shading ring of 2.4 ~ 2.8 μm by tungsten silicon.
7. the preparation method as described in any one of claim 5 ~ 6, is characterized in that, the length of described ground floor shading ring is 0.75 μm, and the length of second layer shading ring is 2.7 μm.
8. the preparation method as described in any one of claim 5 ~ 6, is characterized in that, the puncture voltage of described LDMOS device is 120v.
CN201410457683.3A 2014-09-10 2014-09-10 LDMOS device with double-layer shielding rings and manufacturing method of LDMOS device Pending CN104269437A (en)

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CN106206723A (en) * 2015-05-08 2016-12-07 北大方正集团有限公司 The horizontal DMOS device of radio frequency and manufacture method
CN106206311A (en) * 2015-05-08 2016-12-07 北大方正集团有限公司 A kind of high frequency horizontal double diffusion oxide semiconductor element and preparation method thereof
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