CN106206723A - The horizontal DMOS device of radio frequency and manufacture method - Google Patents
The horizontal DMOS device of radio frequency and manufacture method Download PDFInfo
- Publication number
- CN106206723A CN106206723A CN201510232641.4A CN201510232641A CN106206723A CN 106206723 A CN106206723 A CN 106206723A CN 201510232641 A CN201510232641 A CN 201510232641A CN 106206723 A CN106206723 A CN 106206723A
- Authority
- CN
- China
- Prior art keywords
- active area
- oxide
- area
- pad oxide
- sinker
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
The invention discloses a kind of horizontal DMOS device of radio frequency and preparation method thereof, the method that the present invention utilizes pad oxide to etch forms the alignment mark of sinker area, thus define active area, this method technique is simple, operability is stronger, avoid the groove formed in prior art by silicon etching makes injection region there is section situation simultaneously, so that injection region can preferably be connected with sinker area, effectively reduce the conducting resistance of device, additionally, due to there is no silicon etching, so it also avoid the lattice defect easily produced in silicon etching.
Description
Technical field
The present invention relates to semiconductor chip and manufacture field, be more particularly to radio frequency horizontal double diffusion gold
Belong to oxide semiconductor element and preparation method thereof.
Background technology
The horizontal double-diffused metal oxide semiconductor of radio frequency (RF LDMOS) is widely used in hands
The fields such as machine base station, radio and television and radar.The technique of RF LDMOS generally comprise sinking layer,
Polysilicon, body region layer, source-drain layer, implanted layer etc..The operation principle of RF LDMOS device is,
Sinker area is connected by injection region with source region, and injection region and source region again can be short by the metal of contact hole
Connect.After raceway groove under polysilicon is formed, electric current just can flow to source region from drain region, then passes through
The metal of contact hole flows to injection region, flows to the source at the back side finally by sinker area.
Traditional manufacture method, typically in exposed silicon face Shang Xianzuo lower floor lithographic definition, so
After carry out silicon etching, form alignment mark, it is provided that use to follow-up active layer alignment.This
Method disadvantageously, sinking layer silicon etching can silicon face formed a groove, this is recessed
Groove forms section when being subsequently implanted in injection region, as shown in Figure 1, it can be seen that dash area
Have a section, this section makes sinker area can not well be connected to source region, although under
Heavy ion drives in the impact that can reduce section, but the risk of yet suffering from.This risk makes device
The instability of the electric conduction resistive of part, and have trend bigger than normal.
Summary of the invention
(1) to solve the technical problem that
The technical problem to be solved in the present invention is how to make the horizontal bilateral diffusion metal oxide of radio frequency half
Conductor device has stable conducting resistance.
(2) technical scheme
In order to solve above-mentioned technical problem, the invention provides a kind of horizontal double diffused metal of radio frequency
The manufacture method of oxide semiconductor element, said method comprising the steps of:
S1, epitaxial layer upper surface formed continuous print pad oxide；
S2, in sinker area defined in described epitaxial layer, and etch the institute that contacts with described sinker area
State pad oxide, make the upper surface of described sinker area expose, form alignment slot；
S3, define active area with described alignment slot for alignment mark, in the both sides of described active area
Epitaxial layer upper surface formed field oxide, remove the described of described active area upper surface afterwards
Pad oxide；
S4, upper surface in the upper surface of described active area and described sinker area form continuous print
Gate oxide, and at the upper surface formation polysilicon of described gate oxide；
S5, in described active area, form body district, source region, drain region, drift region and injection region.
Preferably, the thickness of described pad oxide is between 500～800 angstroms.
Preferably, in described step S1, use thermal oxidation technology or chemical vapor deposition method shape
Become described pad oxide；
Preferably, in described step S2, after definition sinker area, etch described pad oxide
Before, described sinker area is carried out ion implanting and ion drives in operation.
Preferably, in described step S2, use photolithography plate to define described sinker area, use dry method
Etching forms described alignment slot, and removes photoresistance after described alignment slot is formed.
Preferably, described step S3 particularly as follows:
S31, upper surface, the bottom of described alignment slot and described alignment slot at described pad oxide
Sidewall formed continuous print silicon nitride, define described active area afterwards；
S32, etch the described silicon nitride of described active area both sides, expose the described pad of correspondence position
Oxide layer；
Field oxide is formed at S33, the described pad oxide exposed in described step S32；
S34, remove described silicon nitride and pad oxide successively.
Preferably, in described step S31, the employing photolithography plate described active area of definition, and
Photoresistance is removed after described step S32 etches the described silicon nitride of described active area both sides.
Preferably, in described step S33, wet oxidation is used to form described field oxide, institute
State the thickness of field oxide between 5000～30000 angstroms.
Preferably, the thickness of described silicon nitride is between 1500～3000 angstroms.
The invention also discloses a kind of horizontal DMOS device of radio frequency, institute
Stating device is that profit makes formation with the aforedescribed process.
(3) beneficial effect
The invention provides a kind of horizontal DMOS device of radio frequency and system thereof
Making method, the present invention utilizes pad oxide etching to form the alignment mark of sinker area, thus defines
Active area, this method technique is simple, and operability is relatively strong, avoids in prior art simultaneously
The groove formed by silicon etching makes injection region there is section situation, so that injection region can be more
Good is connected with sinker area, effectively reduces the conducting resistance of device, additionally, due to not having silicon
Etching, so it also avoid the lattice defect easily produced in silicon etching.
Accompanying drawing explanation
In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, below
The accompanying drawing used required in embodiment or description of the prior art will be briefly described, aobvious and
Easily insight, the accompanying drawing in describing below is only some embodiments of the present invention, for this area
From the point of view of those of ordinary skill, on the premise of not paying creative work, it is also possible to according to these
Accompanying drawing obtains other accompanying drawing
Fig. 1 is the structure of the horizontal DMOS device of radio frequency in prior art
Schematic diagram；
Fig. 2 is the system of the horizontal DMOS device of a kind of radio frequency of the present invention
Make method flow diagram；
Fig. 3 is the device architecture schematic diagram after forming pad oxide in the present invention；
Fig. 4 is the device architecture schematic diagram behind sinker area defined in the present invention；
Fig. 5 is the device architecture schematic diagram after forming alignment groove layer in the present invention；
Fig. 6 is the device architecture schematic diagram after active area defined in the present invention；
Fig. 7 is the device architecture schematic diagram in the present invention after etch silicon nitride；
Fig. 8 is the device architecture schematic diagram after forming field oxide in the present invention；
Fig. 9 is the device architecture schematic diagram after forming gate oxide and polysilicon in the present invention；
Figure 10 is the device architecture schematic diagram after forming body district in the present invention；
Figure 11 is the device architecture schematic diagram after forming source region, drain region and drift region in the present invention；
Figure 12 is the device architecture schematic diagram after forming injection region in the present invention.
Detailed description of the invention
With embodiment, the present invention is described in further detail below in conjunction with the accompanying drawings.Following example
For the present invention is described, but can not be used for limiting the scope of the present invention.
Fig. 1 is the structure of the horizontal DMOS device of radio frequency in prior art
Schematic diagram, from the figure, it can be seen that device include substrate 1, epitaxial layer 2, field oxide 3,
Gate oxide 4, body district 5, polysilicon 6, injection region 7, source region 8, drift region 9, drain region 10
And sinker area 11.Sinker area 11 is connected by injection region 7 with source region 8, injection region 7 and source region
8 again can be by the metal short circuit of contact hole.After raceway groove under polysilicon is formed, electric current just can be from
Drain region 10 flows to source region 8, then flows to injection region 7 by the metal of contact hole, then passes through
Sinker area 11 flows to the source at the back side, the silicon etching of sinking layer 11, can form one at silicon face
Individual groove, this groove is when being subsequently implanted into, and injection region forms section, as it is shown in figure 1, can
Having a section with see dash area, this section makes sinker area 11 well not connect
Knot is to source region 8.Although this section drives at sinker area 11 ion can reduce this impact, but
It is to yet suffer from risk.This risk makes the instability of the electric conduction resistive of device, and has partially
Big trend.
For above-mentioned technical problem, the present invention proposes a kind of radio frequency horizontal double diffused metal oxidation
The manufacture method of thing semiconductor device, as in figure 2 it is shown, said method comprising the steps of:
S1, epitaxial layer 2 upper surface formed continuous print pad oxide 12；
Further, thermal oxidation technology or chemical vapor deposition method is used to form described pad oxidation
Layer；For described thermal oxidation technology, it is passed through oxygen, allows oxygen and epi-layer surface react
Generating oxide layer, epitaxial layer can be silicon epitaxy layer, and the oxide layer of generation is silicon dioxide, its
The temperature of middle oxidizing process is between 900～1100 degree；For chemical vapor deposition method, temperature
Between 600～800 degree；
Further, the thickness of described pad oxide 12 is between 500～800 angstroms；This thickness
Extremely important, it forms alignment slot in follow-up etching, and to ensure follow-up photoetching level
In exposure machine can identify this alignment slot, as the thinnest in fruit dot oxide layer, exposure machine possibly cannot
Identify this alignment slot, if the thickest, during being subsequently generated field oxide, can be formed relatively
Long beak, so the thickness of pad oxide must meet exposure function identification and be directed at
Little thickness, as shown in Figure 3；
S2, in sinker area 11 defined in described epitaxial layer 2, and etch connect with described sinker area 11
The described pad oxide 12 touched, makes the upper surface of described sinker area 11 expose, and forms alignment slot,
As shown in Figure 5；
Further, after definition sinker area 11, before etching described pad oxide 12,
Described sinker area is carried out ion implanting and ion drives in operation, as shown in Figure 4；
Further, use photolithography plate to define described sinker area 11, use dry etching to form institute
State alignment slot, and remove after described alignment slot is formed used by the described sinker area 11 of definition
Photoresistance 14；
S3, the region being alignment mark definition active area with described alignment slot, at described active area
Both sides epitaxial layer upper surface formed field oxide 3, remove described active area upper surface afterwards
Described pad oxide 12, as shown in Figure 8；
S4, upper surface in the upper surface of described active area and described sinker area 11 form grid oxygen
Change layer 4, and at the upper surface formation polysilicon 6 of described gate oxide 4, as shown in Figure 9；
S5, in described active area formed body district 5, source region 8, drain region 10, drift region 9 and
Injection region 7, as shown in Figure 10,11,12；
Further, form described gate oxide 4, polysilicon 6 is by lithographic definition and etches reality
Existing；
Further, described body district 5 is formed particularly as follows: define body district；Ion implanting；Ion
Drive in；
Further, described drift region 9 is formed particularly as follows: define drift region；Ion implanting；
Further, described source region 8 is formed particularly as follows: define source region；Ion implanting；
Further, described drain region 10 is formed particularly as follows: define drain region；Ion implanting；
Further, described injection region 7 is formed particularly as follows: define injection region；Ion implanting,
Owing to avoiding silicon groove in traditional handicraft, described injection region 7 will not form section.
Last part technology, as aperture layer formation, surface metal connect, carry on the back gold process and prior art phase
With, repeat no more here.
Described step S3 particularly as follows:
S31, upper surface, the bottom of described alignment slot and alignment slot at described pad oxide 12
Sidewall formed continuous print silicon nitride 13, and with alignment slot for alignment mark define described active area,
As shown in Figure 6；
Further, the thickness of described silicon nitride is between 1500～3000 angstroms；
S32, etch the described silicon nitride 14 of described active area both sides, expose the described of correspondence position
Pad oxide 12, as described in Figure 7；
Field oxide 3 is formed at S33, the described pad oxide 12 exposed in described step S32；
S34, remove described silicon nitride 14 and pad oxide 12 successively, as shown in Figure 8.
In described step S31, photolithography plate is used to define described active area, and in described step
Photoresistance 14 is removed after S32 etches the described silicon nitride of described active area both sides.Described step
In S33, using wet oxidation to form described field oxide 3, the thickness of described field oxide 3 exists
Between 5000～30000 angstroms.
Further, by temperature 170 degree, concentration is the strong phosphoric acid described silicon nitride of removal of 85%
14, divest described pad oxide 12 with Fluohydric acid..
The doping content of the described injection region 7 of the device of the present invention is mixed more than described sinker area 11
Miscellaneous concentration, the doping content of described sinker area 11 is more than the doping content in described body district 5, described
The doping content in body district 5 is more than the dopant concentration of described epitaxial layer 2.
If the device N-type device of the present invention, then substrate 1 is P type substrate, and epitaxial layer 2 is
P-type epitaxial layer, body district 5 is PXing Ti district, and injection region 7 is p-type injection region, and source region 8 is N
Type source region, drift region 9 is N-type drift region, and drain region 10 is N-type drain region, and sinker area 11 is
P-type sinker area；If the device P-type device of the present invention, then substrate 1 is P type substrate, then
Epitaxial layer 2 is p-type epitaxial layer, and body district 5 is NXing Ti district, and injection region 7 is p-type injection region,
Source region 8 is p-type source region, and drift region 9 is P drift district, and drain region 10 is p-type drain region, under
Heavy district 11 is p-type sinker area.
The invention also discloses a kind of horizontal DMOS device of radio frequency, institute
Stating device is that profit makes formation with the aforedescribed process.
The present invention utilizes the method that pad oxide etches to form the alignment mark of sinker area, from depending on
Justice active area, this method technique is simple, and operability is relatively strong, avoids traditional handicraft simultaneously
In the groove that formed of silicon etching, thus avoid the existence of injection region section, make the injection region can
To be preferably connected with sinker area, effectively reduce the conducting resistance of device, additionally, due to not having
There is silicon etching, so it also avoid the lattice defect easily produced in silicon etching.
Embodiment of above is merely to illustrate the present invention, rather than limitation of the present invention.Although ginseng
According to embodiment, the present invention is described in detail, it will be understood by those within the art that,
Technical scheme is carried out various combination, amendment or equivalent, without departure from this
The spirit and scope of inventive technique scheme, all should contain in the middle of scope of the presently claimed invention.
Claims (10)
1. a manufacture method for the horizontal DMOS device of radio frequency, it is special
Levy and be, said method comprising the steps of:
S1, epitaxial layer upper surface formed continuous print pad oxide；
S2, in sinker area defined in described epitaxial layer, and etch the institute that contacts with described sinker area
State pad oxide, make the upper surface of described sinker area expose, form alignment slot；
S3, define active area with described alignment slot for alignment mark, in the both sides of described active area
Epitaxial layer upper surface formed field oxide, remove the described of described active area upper surface afterwards
Pad oxide；
S4, upper surface in the upper surface of described active area and described sinker area form continuous print
Gate oxide, and at the upper surface formation polysilicon of described gate oxide；
S5, in described active area, form body district, source region, drain region, drift region and injection region.
Method the most according to claim 1, it is characterised in that the thickness of described pad oxide
Degree is between 500～800 angstroms.
Method the most according to claim 2, it is characterised in that in described step S1,
Thermal oxidation technology or chemical vapor deposition method is used to form described pad oxide.
Method the most according to claim 3, it is characterised in that in described step S2,
After definition sinker area, before etching described pad oxide, described sinker area is carried out ion
Inject and ion drives in operation.
Method the most according to claim 4, it is characterised in that in described step S2,
Use photolithography plate to define described sinker area, use dry etching to form described alignment slot, and
Described alignment slot removes photoresistance after being formed.
Method the most according to claim 5, it is characterised in that described step S3 is concrete
For:
S31, upper surface, the bottom of described alignment slot and described alignment slot at described pad oxide
Sidewall formed continuous print silicon nitride, define described active area afterwards；
S32, etch the described silicon nitride of described active area both sides, expose the described pad of correspondence position
Oxide layer；
Field oxide is formed at S33, the described pad oxide exposed in described step S32；
S34, remove described silicon nitride and pad oxide successively.
Method the most according to claim 6, it is characterised in that in described step S31,
Use photolithography plate to define described active area, and in described step S32, etch described active area
Photoresistance is removed after the described silicon nitride of both sides.
Method the most according to claim 7, it is characterised in that in described step S33,
Using wet oxidation to form described field oxide, the thickness of described field oxide is 5000～30000
Between angstrom.
Method the most according to claim 8, it is characterised in that the thickness of described silicon nitride
Between 1500～3000 angstroms.
10. the horizontal DMOS device of radio frequency, it is characterised in that
Described device is to utilize the method described in any one of claim 1 to 9 to make to be formed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510232641.4A CN106206723B (en) | 2015-05-08 | 2015-05-08 | The horizontal DMOS device of radio frequency and production method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510232641.4A CN106206723B (en) | 2015-05-08 | 2015-05-08 | The horizontal DMOS device of radio frequency and production method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106206723A true CN106206723A (en) | 2016-12-07 |
| CN106206723B CN106206723B (en) | 2019-06-28 |
Family
ID=57459892
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510232641.4A Active CN106206723B (en) | 2015-05-08 | 2015-05-08 | The horizontal DMOS device of radio frequency and production method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106206723B (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5155563A (en) * | 1991-03-18 | 1992-10-13 | Motorola, Inc. | Semiconductor device having low source inductance |
| US20070228497A1 (en) * | 2006-03-31 | 2007-10-04 | Eudyna Devices Inc. | Semiconductor device and method for fabricating the same |
| CN103035610A (en) * | 2012-06-08 | 2013-04-10 | 上海华虹Nec电子有限公司 | Electric connection structure for connection trap and substrate in radio frequency (RF) laterally diffused metal oxide semiconductor (LDMOS) and manufacture method |
| US20140187012A1 (en) * | 2011-12-13 | 2014-07-03 | Freescale Semiconductor, Inc. | Customized shield plate for a field effect transistor |
| CN104269437A (en) * | 2014-09-10 | 2015-01-07 | 上海联星电子有限公司 | LDMOS device with double-layer shielding rings and manufacturing method of LDMOS device |
-
2015
- 2015-05-08 CN CN201510232641.4A patent/CN106206723B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5155563A (en) * | 1991-03-18 | 1992-10-13 | Motorola, Inc. | Semiconductor device having low source inductance |
| US20070228497A1 (en) * | 2006-03-31 | 2007-10-04 | Eudyna Devices Inc. | Semiconductor device and method for fabricating the same |
| US20140187012A1 (en) * | 2011-12-13 | 2014-07-03 | Freescale Semiconductor, Inc. | Customized shield plate for a field effect transistor |
| CN103035610A (en) * | 2012-06-08 | 2013-04-10 | 上海华虹Nec电子有限公司 | Electric connection structure for connection trap and substrate in radio frequency (RF) laterally diffused metal oxide semiconductor (LDMOS) and manufacture method |
| CN104269437A (en) * | 2014-09-10 | 2015-01-07 | 上海联星电子有限公司 | LDMOS device with double-layer shielding rings and manufacturing method of LDMOS device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106206723B (en) | 2019-06-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP6421570B2 (en) | Semiconductor device | |
| JP5601848B2 (en) | Method for manufacturing SiC semiconductor device | |
| US9698248B2 (en) | Power MOS transistor and manufacturing method therefor | |
| CN104254920A (en) | Semiconductor device and semiconductor device fabrication method | |
| CN103579311A (en) | Semiconductor device | |
| JP5583846B2 (en) | Semiconductor device | |
| JP2017152488A (en) | Method of manufacturing compound semiconductor device, and compound semiconductor device | |
| US9583587B2 (en) | Method for manufacturing injection-enhanced insulated-gate bipolar transistor | |
| CN105321824A (en) | Method for manufacturing semiconductor device | |
| CN103295907A (en) | Semiconductor device and method of manufacture thereof | |
| US20170288047A1 (en) | Shallow-Trench Semi-Super-Junction VDMOS Device and Manufacturing Method Therefor | |
| US20130221498A1 (en) | Semiconductor device and method for manufacturing the same | |
| JP5558243B2 (en) | Semiconductor device | |
| CN102916042A (en) | Reverse IGBT (insulated gate bipolar transistor) device structure and manufacturing method therefor | |
| US7732877B2 (en) | Gated diode with non-planar source region | |
| JP2015056643A (en) | Semiconductor device manufacturing method | |
| US20100163991A1 (en) | Laterally double-diffused metal oxide semiconductor, and method for fabricating the same | |
| CN104617045A (en) | Manufacturing method of trench gate power device | |
| CN104103693A (en) | U-groove power device and manufacturing method thereof | |
| KR20180104236A (en) | Method of Manufacturing Power Semiconductor Device | |
| JPWO2008123491A1 (en) | Semiconductor device using carrier multiplication by ionizing collision and method for manufacturing the same | |
| CN109860277A (en) | A kind of JFET device and preparation method thereof | |
| CN106206723A (en) | The horizontal DMOS device of radio frequency and manufacture method | |
| CN106206724A (en) | A kind of high frequency horizontal double diffusion oxide semiconductor element and preparation method thereof | |
| CN105225957B (en) | Slot type power device production method and slot type power device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20220722 Address after: 518116 founder Microelectronics Industrial Park, No. 5, Baolong seventh Road, Baolong Industrial City, Longgang District, Shenzhen, Guangdong Province Patentee after: SHENZHEN FOUNDER MICROELECTRONICS Co.,Ltd. Address before: 100871, fangzheng building, 298 Fu Cheng Road, Beijing, Haidian District Patentee before: PEKING UNIVERSITY FOUNDER GROUP Co.,Ltd. Patentee before: SHENZHEN FOUNDER MICROELECTRONICS Co.,Ltd. |
|
| TR01 | Transfer of patent right |