CN106206311A - A kind of high frequency horizontal double diffusion oxide semiconductor element and preparation method thereof - Google Patents
A kind of high frequency horizontal double diffusion oxide semiconductor element and preparation method thereof Download PDFInfo
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Abstract
The present invention relates to a kind of high frequency horizontal double diffusion oxide semiconductor element and manufacture method thereof, described method includes: sequentially generate the first pad oxide and the first silicon nitride layer at epitaxial layer upper surface；Define sunken regions on the first silicon nitride layer, and remove the silicon nitride of the first silicon nitride layer of sunken regions；Carry out ion implanting in sunken regions, form sinker area；Generated the oxide layer of preset thickness by thermal oxide on the first pad oxide surface of sunken regions；Remove the first silicon nitride layer, oxide layer and the first pad oxide respectively, the epitaxial layer of sunken regions is formed groove；On epitaxial layer, generate the second pad oxide and the second nitration case successively, and define active region；Active region according to definition prepares active area.The present invention forms alignment indentation by silicon selective oxidation technology, it is to avoid etching silicon forms the plasma damage during groove, does not results in the section of ion implanted region simultaneously, effectively reduces the conducting resistance of device.
Description
Technical field
The present invention relates to technical field of semiconductor device, especially relate to the double expansion of a kind of high frequency level
Dissipate oxide semiconductor element and preparation method thereof.
Background technology
The horizontal double-diffused metal oxide semiconductor of high frequency (RF LDMOS) is widely used in hands
The fields such as machine base station, radio and television and radar.As it is shown in figure 1, existing N-type RF LDMOS
Technique be commonly included on p-type epitaxial layer 20 preparation P sinking layer 30, active layer 50, polysilicon layer
60, body region layer 70, drift layer 80, drop ply 90 and P+ implanted layer 40 etc..RF LDMOS
The operation principle of device is, sinking layer 30 is connected with active layer 50 by P+ implanted layer 40, P+
Implanted layer 40 and active layer are further through the metal short circuit of contact hole.Raceway groove under polysilicon layer 60 is formed
After, electric current just can flow to active layer 50 from drop ply 90, then flows to P+ by the metal of contact hole
Injection region, then flows to the source at the back side by P sinker area.
The conventional fabrication method of RF LDMOS device, under typically first doing on exposed silicon face
Heavy layer photoetching definition, then carries out silicon etching, forms alignment mark, it is provided that to follow-up active
Layer, polysilicon layer alignment uses.This method disadvantageously, the silicon etching of sinking layer, meeting
Forming a groove 100 at silicon face, this groove 100 can be formed when follow-up P+ injects
P+ district section, P+ injection region as described in Figure 1, it is positioned at the P+ injection region of sinker area and is positioned at body
P+ injection region above district forms a section, and this section makes sinker area well not connect
Tie on the P+ injection region 40 near active layer 50.And the formation of this section, it is due in definition
During sinker area 30, employ silicon etching and form groove 100 as alignment mark.Although sink from
Son drives in and can reduce this impact, but the risk of yet suffering from.This risk makes leading of device
The instability of energising resistive, and have trend bigger than normal.
Summary of the invention
Based on the problems referred to above, the present invention provides a kind of high frequency horizontal double diffusion oxide semiconductor device
Part and preparation method thereof, forms alignment indentation by silicon selective oxidation technology, it is to avoid etching silicon
Form the plasma damage during groove, use the groove that silicon selective oxidation technology is formed simultaneously
Side ratio shallower, do not result in the section of ion implanted region, thus effectively reduce device
Conducting resistance.
According to an aspect of the present invention, it is provided that a kind of high frequency horizontal double diffusion oxide semiconductor
The manufacture method of device, it is characterised in that described method includes:
The first pad oxide and the first silicon nitride layer is sequentially generated at epitaxial layer upper surface；
Described first silicon nitride layer defines sunken regions, and removes the of described sunken regions
The silicon nitride of one silicon nitride layer；
Carry out ion implanting in described sunken regions, form sinker area；
Preset thickness is generated by thermal oxide on the first pad oxide surface of described sunken regions
Oxide layer, the thickness of described oxide layer is more than the thickness of described first pad oxide；
Remove described first silicon nitride layer, oxide layer and the first pad oxide respectively, under described
The extension outside groove, the bottom of described groove and described groove is formed on the epitaxial layer in heavy region
The surface of layer is parallel, and the bottom width of described groove is less than the open top width of described groove；
Generate the second pad oxide and the second nitration case the most on said epitaxial layer there, and described
Active region is defined with described groove for alignment mark on second silicon nitride layer；
Described active region according to definition prepares active area.
Wherein, described the first pad oxide and the first silicon nitride are sequentially generated at epitaxial layer upper surface
Layer, specifically includes:
Institute is formed at the upper surface of described epitaxial layer by the upper surface of epitaxial layer described in thermal oxide
State the first pad oxide；Or deposit at the upper surface of described epitaxial layer by chemical vapor deposition method
Form described first pad oxide；
By chemical vapor deposition method at the upper surface formation of deposits of described first pad oxide
Described first silicon nitride layer.
Wherein, the silicon nitride of the first silicon nitride layer of the etching technics described sunken regions of removal is used；
Wherein, the degree of depth of described groove is the 46% of described oxidated layer thickness.
Wherein, described groove be shaped as inverted trapezoidal.
Wherein, the side of described groove is arc.
Wherein, carry out ion implanting in described sunken regions, form sinker area, specifically include:
Using the first ion to carry out sinker area ion implanting in described sunken regions, high temperature drives in and makes
Obtain described first ion to be fully contacted with described substrate, form sinker area.
Wherein, active area is prepared in described region of having chance with according to definition, specifically includes:
Remove the silicon nitride of second silicon nitride layer in region outside described active area；
Area generation field oxide outside described active area；
Remove the second silicon nitride layer and second pad oxide of described active area；
Upper surface at the epitaxial layer of described active area generates gate oxide；
At the predeterminated position deposit polycrystalline silicon of the upper surface of described gate oxide, generate grid region；
Respectively in the epitaxial layer of described active area prepare drain region, source region, drift region, body district with
And ion implanted region, the ion injected in described ion implanted region is mutually similar with described sinker area
Type but the second ion of variable concentrations.
Wherein, described field oxide is generated by wet oxidation row.
According to another aspect of the present invention, it is provided that a kind of horizontal bilateral diffusion metal oxide of high frequency
Semiconductor device, it is characterised in that described semiconductor device is made up of said method.
A kind of high frequency horizontal double diffusion oxide semiconductor element of the present invention and making thereof
Method, forms alignment indentation by silicon selective oxidation technology, it is to avoid etching silicon forms groove mistake
Plasma damage in journey, uses the side of the groove of silicon selective oxidation technology formation to compare simultaneously
Gently, do not result in the section of ion implanted region so that ion implanted region can preferably with under
Heavy district is connected, thus effectively reduces the conducting resistance of device.Further, the method work
Skill is simple, strong operability, it is possible to increase the make efficiency of semiconductor device.
Accompanying drawing explanation
By being more clearly understood from the features and advantages of the present invention with reference to accompanying drawing, accompanying drawing is to show
Meaning property and should not be construed as the present invention is carried out any restriction, in the accompanying drawings:
Fig. 1 shows the structural representation of existing N-type RF LDMOS device.
Fig. 2 shows the flow chart of the method for the manufacture RF LDMOS device of the present invention.
Fig. 3 to Figure 14 shows the manufacture work of the RF LDMOS device of one embodiment of the invention
The sectional view of skill.
Detailed description of the invention
Below in conjunction with accompanying drawing, embodiments of the present invention is described in detail.
Fig. 2 shows the flow chart of the method for the manufacture RF LDMOS device of the present invention.
With reference to Fig. 2, the detailed process of the method for the manufacture RF LDMOS device of the present invention is as follows:
S1, sequentially generate the first pad oxide and the first silicon nitride layer at epitaxial layer upper surface；
In the present embodiment, the process use preparing substrate and epitaxial layer is of the prior art often
By technique, it is not described in detail in this, and the substrate and the epitaxial layer that use in the present embodiment are silicon
Sheet.
The first pad oxide in the present embodiment can use thermal oxidation technology, is passed through oxygen, allows oxygen
Gas and epi-layer surface react generation silicon dioxide layer, actual temp 900～1100 degree it
Between.Additionally can also use chemical vapor deposition method, deposit layer of oxide layer, temperature exists
Between 600～800 degree.The thickness of the first pad oxide is between 200～500 angstroms.First silicon nitride
Layer chemical vapor deposition method, temperature is between 600～800 degree, and thickness is 1000～3000
Between angstrom.
S2, on described first silicon nitride layer, define sunken regions, and remove described sunken regions
The silicon nitride of the first silicon nitride layer；
In this step, after definition sunken regions, with photoresistance as mask, use dry method
First silicon nitride layer of etching sunken regions, and expose the first silicon oxide layer in lower region.
S3, carry out ion implanting in described sunken regions, form sinker area；
Specifically, the first ion is used to carry out sinker area ion implanting, so in described sunken regions
Rear removal photoresistance, high temperature drives in so that described first ion is fully contacted with described substrate, is formed
Sinker area.
S4, on the first pad oxide surface of described sunken regions by thermal oxide generate preset thickness
The oxide layer of degree, the thickness of described oxide layer is more than the thickness of described first pad oxide；
Generating oxide layer by thermal oxide in the present embodiment, the thickness of this oxide layer is significantly larger than the
The thickness of one pad oxide, its oxidate temperature is between 900～1100 degree, the thickness of oxide layer
Between 1000～2000 angstroms.
By above-mentioned steps S1, S2 and S4, define a complete silicon selective oxidation technology
The technical process of LOCOS (LOCAL Oxidation of Silicon), and the purpose of step S4
It is to form the silicon groove for alignment, the oxidation thickness of the degree of depth of this groove thus step
Degree determines.According to silicon this consumption ratio in silica, this depth of groove is oxidation thickness
The 46% of degree.This silicon groove be mild rather than in traditional handicraft silicon etching formed non-
The most precipitous step, so it also avoid the tomography of follow-up ion implanted region.
S5, remove described first silicon nitride layer, oxide layer and the first pad oxide respectively, in institute
State and formed outside groove, the bottom of described groove and described groove on the epitaxial layer of sunken regions
The surface of epitaxial layer is parallel, and the bottom width of described groove is less than the open top width of described groove
Degree；
By temperature 170 degree in this step, concentration be 85% strong phosphoric acid remove the first silicon nitride layer,
Then the oxide layer of growth in the first pad oxide and upper step process is divested with Fluohydric acid..
After removing removing oxide layer, epitaxial layer defines the groove for alignment.The shape of this groove
Shape is approximately inverted trapezoidal, or base level, and side is minor arc shape.
S6, generate the second pad oxide and the second nitration case the most on said epitaxial layer there, and
Active region is defined with described groove for alignment mark on described second silicon nitride layer；
The thickness of the second pad oxide in the present embodiment is between 200～500 angstroms, and second nitrogenizes
The thickness of silicon layer is between 1500～3000 angstroms.In active area photoetching process, with aforesaid
The silicon groove that LOCOS technique is formed is directed at.
S7, according to definition described active region prepare active area.
In above process, the preparation technology of the structure of active area and the technique in existing method
Identical, i.e. detailed process is as follows:
Remove the silicon nitride of second silicon nitride layer in region outside described active area；
Area generation field oxide outside described active area；
In the present embodiment, use the method growth field oxide of wet oxidation, field oxide
Thickness is between 5000～30000 angstroms.
Remove the second silicon nitride layer and second pad oxide of described active area；
Typically by temperature 170 degree, concentration be 85% strong phosphoric acid remove the second silicon nitride layer, use
Fluohydric acid. divests the second pad oxide.
Upper surface at the epitaxial layer of described active area generates gate oxide；
At the predeterminated position deposit polycrystalline silicon of the upper surface of described gate oxide, generate grid region；
Respectively in the epitaxial layer of described active area prepare drain region, source region, drift region, body district with
And ion implanted region, the ion injected in described ion implanted region is mutually similar with described sinker area
Type but the second ion of variable concentrations.
After said process completes, carry out last part technology, as aperture layer is formed, surface metal line etc.
Deng, it is not described in detail in this.
In the embodiment of said method, can also be performed other according to alternative embodiment
The step of order.Such as, more than the alternate embodiment of the present invention can perform in different order
The step of general introduction.Additionally, independent step can include carrying out in various order in said method
Many sub-steps, as long as being suitable for independent step.Additionally, it is permissible according to specific application
Add or remove additional step.One of those skilled in the art it will be recognized that many change programmes,
Modification and replacement scheme.
The making of the RF LDMOS device of the present invention is described in detail below by specific embodiment
Technical process.The present embodiment is described as a example by the manufacture of N-type RF LDMOS device.
Fig. 3 to Figure 14 shows the manufacture work of the RF LDMOS device of one embodiment of the invention
The sectional view of skill.
With reference to Fig. 3, after preparation P type substrate 10 and p-type extension 20, p-type epitaxial layer 20 is made
For the first pad oxide 101, first pad oxide 101 of the present embodiment can use thermal oxidation technology,
It is passed through oxygen, allows oxygen and epitaxial layer 20 surface react generation silicon dioxide layer, specifically temperature
Degree is between 900～1100 degree.Additionally can also use chemical vapor deposition method, deposition the first pad
Oxide layer, temperature is between 600～800 degree.The thickness of the first pad oxide 101 is 200～500
Between angstrom.First silicon nitride layer 102 chemical gaseous phase amasss technique, temperature between 600～800 degree,
Thickness is between 1000～3000 angstroms.
The most as shown in Figure 4, the first silicon nitride layer 102 deposits the first photoresistance 103,
The first predeterminable area definition sunken regions on one pad oxide 102, and with the first photoresistance 103
For mask, remove the silicon nitride of the first silicon nitride layer 102 of described sunken regions.
Sunken regions in definition uses the first ion to carry out sinking ion implanting, then removes light
Resistance 103, high temperature drives in so that the first ion is fully contacted with substrate 10, forms sinker area 30,
As shown in Figure 5.
Then the surface at the first pad oxide 101 of sunken regions generates default by thermal oxide
The oxide layer 104 of thickness, in the present embodiment, the thickness of the oxide layer of generation is 1000～2000
Between angstrom, as shown in Figure 6.
As it is shown in fig. 7, remove described first silicon nitride layer 102, oxide layer 104 and first respectively
Pad oxide 101, due to the generation of oxide layer, defines tool on the epitaxial layer of sunken regions
Having the groove of certain depth, the degree of depth of this groove is determined by the thickness of oxide layer, according to silicon two
This consumption ratio in silicon oxide, the degree of depth of groove is the 46% of oxidated layer thickness, it addition, groove
Bottom surface parallel with the surface of the epitaxial layer outside groove, side is oblique line or minor arc line.
By the LOCOS technique of said process, the sunken regions at epitaxial layer defines conduct
The groove of alignment mark, and the side of this groove is mild rather than silicon in traditional handicraft
The most precipitous step that etching is formed, so it also avoid the tomography of follow-up ion implanted region.
After completing said process, as shown in Figure 8, on described epitaxial layer 20, generate second successively
Pad oxide 107 and the second silicon nitride layer 108, and with described recessed on the second silicon nitride layer 108
Groove is that alignment mark defines active region；In the present embodiment, owing to having in sunken regions
Groove, therefore, has groove on the second silicon nitride layer 108 generated equally, such that it is able to
The definition of active area is carried out as alignment mark during definition active area.
When defining active region, cover this active region by the second photoresistance 109, in order to
Prepare other structures of active area.
Definition based on above-mentioned active region, prepares the relevant knot of active area in the active areas
Structure, as prepare gate oxide, polysilicon layer, body district, drift region, source region, drain region and from
Sub-injection region etc..
In the present embodiment, prepare active area structure to specifically include:
The silicon nitride of second silicon nitride layer in the region outside removal active area, then removes second
Photoresist layer 109, as shown in Figure 9.
Then at the field oxide 105 of Area generation the second preset thickness removing the second silicon nitride,
The present embodiment uses the method growth field oxide 105 of wet oxidation, the thickness of field oxide 105
Degree is between 5000～30000 angstroms.Remove the second silicon nitride layer 108 on active area and the afterwards
Two pad oxides 107, as shown in Figure 10.
As shown in figure 11, the upper surface at active area generates gate oxide 106, and deposit polycrystalline
Silicon forms grid region 60.
In the epitaxial layer of active area the 3rd predeterminable area definition body district 70 and inject body district from
Son, then Zuo Ti district ion drives in, and forms body district 70, as shown in figure 12.
Then definition drift region 80 and drift region ion implanting, definition source region 50 and source region ion note
Enter, definition drain region 90 and drain region ion implanting, as shown in figure 13.
Then definition P+ injection region 40, does P+ district ion implanting, owing to avoiding use etching
Technique forms silicon groove, so P+ injection region does not just have tomography, as shown in figure 14.
After completing above-mentioned etching and injection technology, carry out aperture layer such as and formed, surface metal line
Etc. technique, it is not described in detail in this.
The present embodiment is be described as a example by N-type RF LDMOS device, but p-type RF
LDMOS is simultaneously suitable for the manufacture method of the present invention.
A kind of high frequency horizontal double diffusion oxide semiconductor element of the present invention and making thereof
Method, forms alignment indentation by silicon selective oxidation technology, it is to avoid etching silicon forms groove mistake
Plasma damage in journey, uses the side of the groove of silicon selective oxidation technology formation to compare simultaneously
Gently, do not result in the section of ion implanted region so that ion implanted region can preferably with under
Heavy district is connected, thus effectively reduces the conducting resistance of device.Further, the method work
Skill is simple, strong operability, it is possible to increase retouch although the make efficiency of semiconductor device combines accompanying drawing
State embodiments of the present invention, but those skilled in the art can be without departing from the present invention's
Making various modifications and variations in the case of spirit and scope, such amendment and modification each fall within
Within the scope of being defined by the appended claims.
Claims (10)
1. the manufacture method of a high frequency horizontal double diffusion oxide semiconductor element, it is characterised in that described method includes:
The first pad oxide and the first silicon nitride layer is sequentially generated at epitaxial layer upper surface；
Described first silicon nitride layer defines sunken regions, and removes the silicon nitride of the first silicon nitride layer of described sunken regions；
Carry out ion implanting in described sunken regions, form sinker area；
Generated the oxide layer of preset thickness by thermal oxide on the first pad oxide surface of described sunken regions, the thickness of described oxide layer is more than the thickness of described first pad oxide；
Remove described first silicon nitride layer, oxide layer and the first pad oxide respectively, the epitaxial layer of described sunken regions is formed groove, the bottom of described groove is parallel with the surface of the epitaxial layer outside described groove, and the bottom width of described groove is less than the open top width of described groove；
Generate the second pad oxide and the second nitration case the most on said epitaxial layer there, and define active region with described groove for alignment mark on described second silicon nitride layer；
Described active region according to definition prepares active area.
Manufacture method the most according to claim 1, it is characterised in that described sequentially generate the first pad oxide and the first silicon nitride layer at epitaxial layer upper surface, specifically includes:
Described first pad oxide is formed at the upper surface of described epitaxial layer by the upper surface of epitaxial layer described in thermal oxide；Or by chemical vapor deposition method at the first pad oxide described in the upper surface formation of deposits of described epitaxial layer；
By chemical vapor deposition method at the first silicon nitride layer described in the upper surface formation of deposits of described first pad oxide.
Manufacture method the most according to claim 1, it is characterised in that use the silicon nitride of the first silicon nitride layer of the etching technics described sunken regions of removal.
Manufacture method the most according to claim 1, it is characterised in that the degree of depth of described groove is the 46% of described oxidated layer thickness.
Manufacture method the most according to claim 1, it is characterised in that described groove be shaped as inverted trapezoidal.
Manufacture method the most according to claim 1, it is characterised in that the side of described groove is arc.
Manufacture method the most according to claim 1, it is characterised in that carry out ion implanting in described sunken regions, forms sinker area, specifically includes:
Using the first ion to carry out sinker area ion implanting in described sunken regions, high temperature drives in so that described first ion is fully contacted with described substrate, forms sinker area.
Manufacture method the most according to claim 1, it is characterised in that active area is prepared in described region of having chance with according to definition, specifically includes:
Remove the silicon nitride of second silicon nitride layer in region outside described active area；
Area generation field oxide outside described active area；
Remove the second silicon nitride layer and second pad oxide of described active area；
Upper surface at the epitaxial layer of described active area generates gate oxide；
At the predeterminated position deposit polycrystalline silicon of the upper surface of described gate oxide, generate grid region；
Preparing drain region, source region, drift region, body district and ion implanted region respectively in the epitaxial layer of described active area, the ion injected in described ion implanted region is and described sinker area same type but the second ion of variable concentrations.
Manufacture method the most according to claim 8, it is characterised in that described field oxide is generated by wet oxidation row.
10. the horizontal DMOS device of high frequency, it is characterised in that be made up of the method described in claim 1-9.
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| US5155563A (en) * | 1991-03-18 | 1992-10-13 | Motorola, Inc. | Semiconductor device having low source inductance |
| US20070228497A1 (en) * | 2006-03-31 | 2007-10-04 | Eudyna Devices Inc. | Semiconductor device and method for fabricating the same |
| CN103035610A (en) * | 2012-06-08 | 2013-04-10 | 上海华虹Nec电子有限公司 | Electric connection structure for connection trap and substrate in radio frequency (RF) laterally diffused metal oxide semiconductor (LDMOS) and manufacture method |
| US20140187012A1 (en) * | 2011-12-13 | 2014-07-03 | Freescale Semiconductor, Inc. | Customized shield plate for a field effect transistor |
| CN104269437A (en) * | 2014-09-10 | 2015-01-07 | 上海联星电子有限公司 | LDMOS device with double-layer shielding rings and manufacturing method of LDMOS device |
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2015
- 2015-05-08 CN CN201510233095.6A patent/CN106206311B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5155563A (en) * | 1991-03-18 | 1992-10-13 | Motorola, Inc. | Semiconductor device having low source inductance |
| US20070228497A1 (en) * | 2006-03-31 | 2007-10-04 | Eudyna Devices Inc. | Semiconductor device and method for fabricating the same |
| US20140187012A1 (en) * | 2011-12-13 | 2014-07-03 | Freescale Semiconductor, Inc. | Customized shield plate for a field effect transistor |
| CN103035610A (en) * | 2012-06-08 | 2013-04-10 | 上海华虹Nec电子有限公司 | Electric connection structure for connection trap and substrate in radio frequency (RF) laterally diffused metal oxide semiconductor (LDMOS) and manufacture method |
| CN104269437A (en) * | 2014-09-10 | 2015-01-07 | 上海联星电子有限公司 | LDMOS device with double-layer shielding rings and manufacturing method of LDMOS device |
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