CN109119472A - A kind of LDMOS device structure and preparation method thereof - Google Patents

A kind of LDMOS device structure and preparation method thereof Download PDF

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CN109119472A
CN109119472A CN201810791054.2A CN201810791054A CN109119472A CN 109119472 A CN109119472 A CN 109119472A CN 201810791054 A CN201810791054 A CN 201810791054A CN 109119472 A CN109119472 A CN 109119472A
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region
conduction type
type
device structure
layer
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李科
万宁
丛密芳
任建伟
李永强
黄苒
苏畅
李�浩
杜寰
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Beijing Dunsi Integrated Circuit Design Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7823—Lateral DMOS transistors, i.e. LDMOS transistors with an edge termination structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors

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Abstract

A kind of LDMOS device structure, comprising: the substrate of the first conduction type forms the epitaxial layer of the first conduction type on substrate；Form the drift region of the second conduction type in the epitaxial layer；The well region of first conduction type extends in substrate from the surface of epitaxial layer；The channel region of first conduction type, is formed in drift region and between drift region and well region；The source region of second conduction type is located in well region and channel region；And second conduction type drain region, be located at drift region in, the grid above channel region is formed with gate insulating layer therebetween；Wherein, it is also formed with groove near surface from epitaxial layer, covers to trench portions drift region and channel region, the trench fill region that trench fill has oxide to constitute.Invention additionally discloses a kind of methods for making the LDMOS device structure.

Description

A kind of LDMOS device structure and preparation method thereof
Technical field
The present invention relates to technical field of semiconductors.More particularly, to a kind of LDMOS device structure and preparation method thereof.
Background technique
Cross bimoment (Lateral Double Diffused It MOSFET is) that a kind of market demand is big, the wide radio-frequency power amplifier part of development prospect.In Radio-Frequency Wireless Communication field, base It stands and long range transmitter almost all uses silicon substrate LDMOS high-capacity transistor；In addition, LDMOS is also widely used for radio frequency Amplifier, as the communications field HF, VHF and UHF, pulse radar, industry, science and medical applications, aviation electronics and WiMAXTM are logical The fields such as letter system.
With the reduction of LDMOS device size, the reduction of the gate oxide thickness, junction depth, channel length of device, device is in high pressure Under environment, high electric field region will necessarily be generated, electric field strength increases in MOSFET channel, under the action of this strong electrical field of carrier Very high energy will be obtained, these high energy carriers are known as " hot carrier ".Hot carrier hits lattice atoms, and collide electricity From phenomenon, secondary electron hole pair is generated, wherein partial holes become substrate current, and part carrier can cross Si/SiO2 Potential barrier forms grid current, in Si/SiO2Place, which generates, generates trap in interfacial state and grid oxygen, so that device leads to device performance, As the degeneration of threshold voltage, mutual conductance and linear zone/saturation region electric current even results in device to influence the service life of device Part failure.
Accordingly, it is desirable to provide a kind of generation that can prevent hot carrier's effect, optimization drift region field distribution are to mention LDMOS device structure of high device lifetime and preparation method thereof, so as to be preferably applied in radio circuit and needs In the circuit for carrying out high voltage control.
Summary of the invention
The purpose of the present invention is to provide generation, optimization drift region field distributions that one kind can prevent hot carrier's effect To improve LDMOS device structure of device lifetime and preparation method thereof.
In order to achieve the above objectives, the present invention adopts the following technical solutions:
A kind of LDMOS device structure, comprising: the substrate of the first conduction type forms the first conduction type on substrate Epitaxial layer；Form the drift region of the second conduction type in the epitaxial layer；The well region of first conduction type, from the table of epitaxial layer Face extends in substrate；The channel region of first conduction type, is formed in drift region and between drift region and well region；Second The source region of conduction type is located in well region and channel region；And second conduction type drain region, be located at drift region in, be located at ditch Grid above road area, is formed with gate insulating layer therebetween；Wherein, groove, ditch are also formed near surface from epitaxial layer Cover to slot part drift region and channel region, the trench fill region that trench fill has oxide to constitute.
Preferably, the first conduction type is p-type, and the second conduction type is N-type；Or first conduction type be N-type, second Conduction type is p-type.
Preferably, the depth of groove is
Preferably, LDMOS device structure further includes grid curb wall, is located at grid two sides.
Preferably, grid includes the metallic silicon of the polysilicon layer being formed on gate insulating layer and formation on the polysilicon layer Compound layer.
Preferably, LDMOS device structure further include: the dielectric layer of covering drift region surface and gate surface；Positioned at insulation The shading ring of grid and drift region is partly covered in layer.
The another aspect of the application provides a kind of method for making LDMOS device structure, and method includes: to provide first to lead The substrate of electric type；The epitaxial layer of the first conduction type is formed on the substrate；The trap of the first conduction type is formed in the epitaxial layer Area, well region extend in substrate from the surface of epitaxial layer；Groove is formed, is extended into from the surface of epitaxial layer to another surface direction Enter epitaxial layer；The trench fill region for forming filling groove, is made of oxide；Gate insulating layer is formed on epitaxial layer；? Form grid on gate insulating layer, grid part ground covering groove filling region；The second conduction type is formed in the epitaxial layer The channel region of drift region and the first conduction type；The well region of the first conduction type, the source region of the second conduction type and drain region are formed, Source region is located in channel region and well region, and drain region is located in drift region.
It preferably, include: to form polysilicon layer simultaneously on gate insulating layer the step of forming grid on gate insulating layer Etching；And metal silicide layer is formed on the polysilicon layer.
Preferably, the first conduction type is p-type, and the second conduction type is N-type；Or first conduction type be N-type, second Conduction type is p-type.
Preferably, the depth of groove is
Beneficial effects of the present invention are as follows:
Technical solution of the present invention, which provides one kind, can prevent the generation of hot carrier's effect, optimization drift region electric field Distribution is to improve LDMOS device structure of device lifetime and preparation method thereof.
Detailed description of the invention
Specific embodiments of the present invention will be described in further detail with reference to the accompanying drawing:
Fig. 1 is the cross-sectional view for showing the exemplary L DMOS device architecture according to the application；And
Fig. 2 to Figure 14 is the gradually diagram for showing the exemplary production method of the LDMOS device structure according to the application.
Specific embodiment
In order to illustrate more clearly of the present invention, the present invention is done further below with reference to preferred embodiments and drawings It is bright.Similar component is indicated in attached drawing with identical appended drawing reference.It will be appreciated by those skilled in the art that institute is specific below The content of description is illustrative and be not restrictive, and should not be limited the scope of the invention with this.
LDMOS device structure 10 provided in this embodiment includes the substrate 101 of the first conduction type, the first conduction type Epitaxial layer 103, the drift region 105 of the second conduction type being lightly doped, the channel region 107 of the first conduction type, the first conductive-type The well region 109 of type, wherein the doping concentration of substrate 101 is greater than the doping concentration of epitaxial layer 103.In the drift region 105 being lightly doped In include the second conduction type heavy doping drain region 111, drain region 111 is from the extension of the surface of separate the substrate 101 of epitaxial layer 103 Into drift region 105, LDMOS device structure 10 further includes the source region 113 of the heavy doping of the second conduction type, and source region 113 is outside The surface for prolonging the separate substrate 101 of layer 103 extends into well region 109 and channel region 107 and partly covers channel region 107 and trap Area 109.
It should be understood that the first conduction type can be p-type, the second conduction type can be N-type.Optionally, the first conductive-type Type can be N-type, and the second conduction type can be p-type.Those skilled in the art can need to select according to product.
According to the LDMOS device structure 10 of the application, from the surface of the separate substrate 101 of epitaxial layer 103 to another surface Direction is formed with groove (115-1 in Fig. 2 is not specifically shown out), covers to trench portions drift region 105 and channel region 107, The trench fill region 115 constituted in groove filled with oxide.The presence in trench fill region 115 can significantly reduce ditch The high electric field of 107 lower section of road area, the especially peak voltage between channel region 107 and drift region 105, avoid the production of hot carrier It is raw, so that the degeneration of the performances such as device threshold voltage, mutual conductance is avoided, to effectively extend the service life of device.
In addition, it will be seen from figure 1 that the LDMOS device structure 10 of the application further includes drain electrode 117, source electrode 119 and grid 121 (including 121-1 and 121-2).Grid 121 can also include polycrystalline silicon grid layer 121-1 and metal silicide layer 121-2, with Make grid 121 that there is better controlling.
It could be formed with the grid curb wall 123 of silicon oxide material in 119 two sides of source electrode, to reduce leakage current.In grid The side of close drain electrode can also have shading ring 125, shading ring 125 partly covers grid and partly covers drift region 105.Preferably, shading ring 125 can be metal or alloy material.Shading ring 125 reduces spike electric field using field plate effect, from And increase voltage endurance capability, further increase hot carrier resistance.
In the following, the illustrative methods in conjunction with Fig. 2 to Figure 14 description according to the manufacture LDMOS device structure 10 of the application, Fig. 2 It is the gradually diagram for showing the exemplary production method of the LDMOS device structure 10 according to the application to Figure 14.
In the present embodiment, for convenience of description and it can be readily appreciated that using the first conduction type as p-type, the second conductive-type Type is for N-type the embodiment that illustrates production method of the invention.It will be understood by those skilled in the art that when the first conduction type As long as the type of corresponding conversion ions when being p-type for N-type.
In the present embodiment, see in Fig. 2 first, prepare 0.005~0.015cm of resistivity-3Heavy doping P-type silicon substrate 101,10 are grown on substrate 10114~1015cm-2, with a thickness of 9 μm of p-type epitaxial layers 103.Well region is formed in epitaxial layer 103 109, the surface of well region 109 from epitaxial layer 103 extends in substrate 101.Specifically, B ion is carried out to 109 corresponding region of well region Heavily-doped implant promotes the well region 109 of 450~500mins formation p-type heavy doping using disposable 1050~1150 DEG C of high temperature.
In Fig. 3, channel region 107 close to drain terminal part carry out shallow ridges it is groove etched, etching depthIt is formed Groove 115-1 as shown in Figure 2.
In Fig. 4 the step of, the growth thickness above epitaxial layer 103Oxide layer 127.
In Fig. 5, the oxide layer 127-1 on 103 surface of epitaxial layers is gone by photoetching and dry etching, to form ditch Slot filling region 115.
In Fig. 6, second of growth thicknessOxide layer 127-2, as gate insulating layer.In grid Above insulating layer 127-2 accumulation and be lithographically formed with a thickness ofPolysilicon layer, photoetching and dry etching are formed Polycrystalline silicon grid layer 121-1, as shown in Figure 7.
In fig. 8, it carries out N-type to drift region 105 to be lightly doped, it is preferable that drift region concentration can be 1012~1013cm-2、 The P ion that energy is 50keV~200keV injects.Next, forming P-type channel area 107, it is preferable that utilize polysilicon gate It is 10 that autoregistration, which carries out dosage,12~1014cm-2Energy is the p-type B foreign ion injection of 30keV, be can use thereafter disposable 900~1050 DEG C of high temperature promote 80~120mins to form P-type channel area 107 and drift region 105, drift region 105 and channel region 107 is adjacent, so that the channel region 107 formed is between drift region 105 and well region 109.It will be understood by those skilled in the art that shape At n-type doping and p-type doping can be not limited to ion described above, other ions are also possible.
In Fig. 9, grid curb wall 123 is made using photoetching process, grid curb wall 123 can be nitride material.
In Figure 10, drain region 111 and source region 113 are formed.Preferably, channel region 107 is located at polysilicon gate 121-1 and grid 123 lower section of side wall.It is 4 × 10 followed by the dosage of drain region and source region15~6 × 1015cm-2, energy be 80~120keV N-type As ion implanting.Finally with 1000~1100 DEG C of disposable short annealing activation source regions 113 and drain region 111.Art technology Personnel should be understood that the ion implanting for source region 113 and drain region 111, and there is no sequence requirements.
In Figure 11, opening is formed on gate insulating layer 127-2 using mask photolithographic process with partially exposed source region 113 and drain region 111.Again utilize photoetching, on open area and polysilicon gate 121-1 formed metal silicide layer 129-1, 121-2 and 129-3 forms Ohmic contact, it is preferable that the metal silication to form being electrically connected for each pole metal and silicon face Nitride layer 129-1,121-2 and 129-3 can be tungsten silicide layer 129-1,121-2 and 129-3.In addition, in polysilicon gate 121-1 Upper formation metal silicide layer 121-2 be formed by grid 121 formed metal and polysilicon be electrically connected at the same time it can also 121 resistance of grid is reduced, to increase switching speed.
In Figure 12, accumulation thickness againDielectric layer 127-3.
In Figure 13, accumulation tungsten or Titanium and are dry-etched in the one of the close drain electrode to form grid 121 at photoetching Side forms shading ring.And in Figure 14, depositDielectric layer 127-4.The formation of shading ring can significantly change The characteristics such as breakdown voltage, the conducting resistance of kind device, increase voltage endurance capability, further increase hot carrier resistance.
Finally, opening is formed on dielectric layer 127-4 using photoetching, exposing metal silicide layer 129-1 and 129-3, Source electrode 119 and drain electrode 117 are formed on metal silicide layer 129-1 and 129-3, to form LDMOS device structure shown in FIG. 1 10。
Obviously, the above embodiment of the present invention be only to clearly illustrate example of the present invention, and not be pair The restriction of embodiments of the present invention may be used also on the basis of the above description for those of ordinary skill in the art To make other variations or changes in different ways, all embodiments can not be exhaustive here, it is all to belong to this hair The obvious changes or variations that bright technical solution is extended out are still in the scope of protection of the present invention.

Claims (10)

1. a kind of LDMOS device structure, comprising:
The substrate of first conduction type,
Form the epitaxial layer of the first conduction type over the substrate；
It is formed in the drift region of the second conduction type in the epitaxial layer；
The well region of first conduction type extends in the substrate from the surface of the epitaxial layer；
The channel region of first conduction type is formed in the drift region and between the drift region and the well region；
The source region of second conduction type is located in the well region and the channel region；And
The drain region of second conduction type is located in the drift region,
Grid above the channel region, is formed with gate insulating layer therebetween；
It is characterized in that,
Wherein, be also formed with groove near surface from the epitaxial layer, cover to the trench portions drift region and The channel region, the trench fill region that the trench fill has oxide to constitute.
2. LDMOS device structure as described in claim 1, which is characterized in that first conduction type is p-type, described the Two conduction types are N-type；Or first conduction type is N-type, second conduction type is p-type.
3. LDMOS device structure as described in claim 1, which is characterized in that the depth of the groove is
4. LDMOS device structure as described in claim 1, which is characterized in that the LDMOS device structure further includes gate electrode side Wall is located at the grid two sides.
5. LDMOS device structure as described in claim 1, which is characterized in that the grid is exhausted including being formed in the grid Polysilicon layer in edge layer and the metal silicide layer being formed on the polysilicon layer.
6. LDMOS device structure as described in claim 1, which is characterized in that the LDMOS device structure further include:
Cover the dielectric layer of the drift region surface and the gate surface；
The shading ring of the grid and the drift region is partly covered in the insulating layer.
7. a kind of method for making LDMOS device structure, which is characterized in that the described method includes:
The substrate of first conduction type is provided；
The epitaxial layer of the first conduction type is formed over the substrate；
The well region of the first conduction type is formed in the epitaxial layer, the surface of the well region from the epitaxial layer extends to described In substrate；
Groove is formed, extends into the epitaxial layer from the surface of the epitaxial layer to another surface direction；
The trench fill region for filling the groove is formed, is made of oxide；
Gate insulating layer is formed on said epitaxial layer there；
Grid is formed on the gate insulating layer, covers to the grid part trench fill region；
The drift region of the second conduction type and the channel region of the first conduction type are formed in the epitaxial layer；
Source region and the drain region of the second conduction type are formed, the source region is located in the channel region and the well region, the drain region In the drift region.
8. the method for production LDMOS device structure as claimed in claim 7, which is characterized in that described in the gate insulator The step of forming grid, includes: on layer
Polysilicon layer is formed on the gate insulating layer and is etched；And
Metal silicide layer is formed on the polysilicon layer.
9. the method for production LDMOS device structure as claimed in claim 7, which is characterized in that first conduction type is P Type, second conduction type are N-type；Or first conduction type is N-type, second conduction type is p-type.
10. the method for production LDMOS device structure as claimed in claim 7, which is characterized in that the depth of the groove is
CN201810791054.2A 2018-07-18 2018-07-18 A kind of LDMOS device structure and preparation method thereof Pending CN109119472A (en)

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Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080197408A1 (en) * 2002-08-14 2008-08-21 Advanced Analogic Technologies, Inc. Isolated quasi-vertical DMOS transistor
US20120043608A1 (en) * 2010-08-20 2012-02-23 Hongning Yang Partially Depleted Dielectric Resurf LDMOS
CN103762238A (en) * 2013-12-31 2014-04-30 上海联星电子有限公司 Radio-frequency power LDMOS device with field plate and preparation method thereof
US20150014768A1 (en) * 2013-07-10 2015-01-15 United Microelectronics Corp. High voltage metal-oxide-semiconductor transistor device and manufacturing method thereof
CN104517848A (en) * 2013-09-29 2015-04-15 中芯国际集成电路制造(上海)有限公司 LDMOS (lateral double-diffused metal oxide semiconductor) transistor structure and formation method thereof
CN104599974A (en) * 2015-02-13 2015-05-06 杰华特微电子（杭州）有限公司 Semiconductor structure and forming method thereof
CN105374879A (en) * 2015-11-16 2016-03-02 上海华虹宏力半导体制造有限公司 Radio frequency laterally diffused metal oxide semiconductor (LDMOS) device
CN107887437A (en) * 2016-09-30 2018-04-06 中芯国际集成电路制造(上海)有限公司 Ldmos transistor and forming method thereof, semiconductor devices and forming method thereof
CN208861995U (en) * 2018-07-18 2019-05-14 北京顿思集成电路设计有限责任公司 A kind of LDMOS device structure

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080197408A1 (en) * 2002-08-14 2008-08-21 Advanced Analogic Technologies, Inc. Isolated quasi-vertical DMOS transistor
US20120043608A1 (en) * 2010-08-20 2012-02-23 Hongning Yang Partially Depleted Dielectric Resurf LDMOS
US20150014768A1 (en) * 2013-07-10 2015-01-15 United Microelectronics Corp. High voltage metal-oxide-semiconductor transistor device and manufacturing method thereof
CN104517848A (en) * 2013-09-29 2015-04-15 中芯国际集成电路制造(上海)有限公司 LDMOS (lateral double-diffused metal oxide semiconductor) transistor structure and formation method thereof
CN103762238A (en) * 2013-12-31 2014-04-30 上海联星电子有限公司 Radio-frequency power LDMOS device with field plate and preparation method thereof
CN104599974A (en) * 2015-02-13 2015-05-06 杰华特微电子（杭州）有限公司 Semiconductor structure and forming method thereof
CN105374879A (en) * 2015-11-16 2016-03-02 上海华虹宏力半导体制造有限公司 Radio frequency laterally diffused metal oxide semiconductor (LDMOS) device
CN107887437A (en) * 2016-09-30 2018-04-06 中芯国际集成电路制造(上海)有限公司 Ldmos transistor and forming method thereof, semiconductor devices and forming method thereof
CN208861995U (en) * 2018-07-18 2019-05-14 北京顿思集成电路设计有限责任公司 A kind of LDMOS device structure

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