CN107887437A - Ldmos transistor and forming method thereof, semiconductor devices and forming method thereof - Google Patents
Ldmos transistor and forming method thereof, semiconductor devices and forming method thereof Download PDFInfo
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- CN107887437A CN107887437A CN201610877464.XA CN201610877464A CN107887437A CN 107887437 A CN107887437 A CN 107887437A CN 201610877464 A CN201610877464 A CN 201610877464A CN 107887437 A CN107887437 A CN 107887437A
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- ldmos transistor
- isolation structure
- buffering area
- drift region
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- 230000003139 buffering effect Effects 0.000 claims abstract description 98
- 239000000758 substrate Substances 0.000 claims description 72
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
- H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1041—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface
- H01L29/1045—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface the doping structure being parallel to the channel length, e.g. DMOS like
Abstract
The invention provides a kind of ldmos transistor and forming method thereof, semiconductor devices and forming method thereof, the ldmos transistor includes drift region, the drain region in the drift region and isolation structure and the buffering area of the transoid in drift region of the isolation structure away from the drain region side.In ldmos transistor provided by the invention, by in isolation structure away from the drift region of drain region side in the buffering area of a transoid is set, to weaken the electric field of the juncture area of the isolation structure and drift region, it can so avoid that stronger ionization by collision occurs and triggers hot carrier's effect in the interface of the isolation structure, so as to further improve the performance of the ldmos transistor.
Description
Technical field
The present invention relates to technical field of semiconductors, more particularly to a kind of ldmos transistor and forming method thereof, semiconductor device
Part and forming method thereof.
Background technology
LDMOS (Laterally Diffused Metal Oxide
Semiconductor, LDMOS) transistor, because it is easier and complementary metal oxide semiconductor (Complementary
Metal Oxide Semiconductors, CMOS) logic process it is compatible and that is answered extensively be used in power integrated circuit.
Fig. 1 is a kind of existing structural representation of ldmos transistor, as shown in figure 1, the ldmos transistor includes：
Semiconductor substrate 11, the well region 12 of the first conduction type in Semiconductor substrate 11, positioned at first conduction type
The drift region 13 of the second conduction type in well region 12, the isolation structure 14 in the drift region 13, positioned at described first
Source region 15 in the well region 12 of conduction type, the drain region 16 in the drift region and on the surface of Semiconductor substrate 11
Grid structure 20.The isolation structure 14 is between the source region 15 and drain region 16.The grid structure 20 is across described
Well region 12 and the drift region 13, and part is on the isolation structure 14.The grid structure 20 includes being formed at
Gate dielectric layer 21 in Semiconductor substrate 11, the gate electrode 22 on the gate dielectric layer 21 and setting are positioned at grid electricity
The side wall 23 of the both sides of pole 22.
However, it has been found that the ldmos transistor of this structure under the working environment of high pressure, due to hot carrier
The influence of injection (Hot Carriers injection, HCI) effect causes device performance not ideal enough.
The content of the invention
It is an object of the invention to provide a kind of ldmos transistor and forming method thereof, semiconductor devices and its formation side
Method, to solve existing ldmos transistor during device works, due to hot carrier in jection to ldmos transistor
Performance the problem of impacting.
In order to solve the above technical problems, the present invention provides a kind of ldmos transistor, including：
Well region and drift region in semi-conductive substrate；
Source region in the well region；
Drain region in the drift region；
Isolation structure in the drift region, the isolation structure is between the source region and the drain region；With
And
In the drift region and close to buffering area of the isolation structure away from drain region side, the buffering area and institute
The doping type for stating drift region is opposite.
Optionally, the well region is opposite with the doping type of the drift region.
Optionally, the doping depth of the buffering area is more than the thickness of the isolation structure.
Optionally, the buffering area covers the described one end of isolation structure away from the drain region.
Optionally, the buffering area extends to the isolation structure bottom to cover the part area of the isolation structure bottom
Domain.
Optionally, the ldmos transistor also includes the grid structure in the Semiconductor substrate, the grid knot
Structure is across the well region and drift region, and part is above the isolation structure.
Optionally, the ldmos transistor also includes the epitaxial layer being located in the Semiconductor substrate, and the well region is located at
In the epitaxial layer, the epitaxial layer is opposite with the doping type of the well region.
Optionally, the ldmos transistor also includes the first diffusion region being located in the drift region, and the drain region is located at
In first diffusion region, the doping type in the drain region, first diffusion region and the drift region is identical.
Optionally, the ldmos transistor also includes the second diffusion region being located in the well region, second diffusion region
Positioned at the side of the drift region, the source region is located in second diffusion region, second diffusion region and the well region
Doping type is identical, and second diffusion region is opposite with the doping type of the source region.
Optionally, the doping type of the well region and buffering area is N-type, the source region, drain region and the doping of drift region class
Type is p-type；Or the doping type of the well region and buffering area is p-type, the source region, drain region and the doping type of drift region
For N-type.
Corresponding, the present invention also provides a kind of method for forming LDMOS crystal as described above, including：
Semi-conductive substrate is provided, formed with a well region and a drift region, the drift in the Semiconductor substrate
Formed with an isolation structure in area；And
A source region is formed in the well region, a drain region is formed in the drift region, in the isolation structure away from institute
State and a buffering area is formed in the drift region of drain region side, the source region is located at the both sides of the isolation structure, institute with drain region respectively
It is opposite with the doping type of the drift region to state buffering area.
Optionally, the buffering area is formed using ion implantation technology at least once.
Optionally, the buffering area using ion implantation technology three times respectively at three different depths in the drift region
Position forms three mutually overlapping doped regions, and the doped region of three different depth positions is collectively forming the buffering area.
Optionally, also include before the source region and the drain region is formed：
In forming a grid structure in the Semiconductor substrate, the grid structure across the well region and drift region, and
Part is on the isolation structure.
It is a further object of the present invention to provide a kind of semiconductor devices with ldmos transistor as described above, with
And a resistive element, the ldmos transistor are located in the firstth area of semi-conductive substrate, the resistive element is positioned at described half
In secondth area of conductor substrate.
Optionally, the resistive element is the polysilicon of doping.
Optionally, it is additionally provided with an insulating barrier between the resistive element and the Semiconductor substrate.
In addition, present invention also offers the forming method of the semiconductor devices described in more than one, including：
Semi-conductive substrate is provided, a well region is formed in the Semiconductor substrate, the first of the Semiconductor substrate
A drift region is formed in area, formed with an isolation structure in the drift region；And
A resistive element is formed in the secondth area of the Semiconductor substrate, in the drift close to the isolation structure side
A buffering area is formed in area, the buffering area is opposite with the doping type of the drift region.
Optionally, the forming method of the resistive element and buffering area includes：
A polysilicon layer is formed on a semiconductor substrate；
Photoetching process is performed in forming patterned photoresist, the figure in the Semiconductor substrate using a mask plate
The photoresist of change exposes the region that need to form resistive element and the region that need to form buffering area；
The first ion implantation technology is performed, to not being doped by the polysilicon layer that the photoresist covers with described in formation
Resistive element；
The second ion implantation technology is performed, the drift region of the isolation structure side is doped to form the buffering
Area.
Optionally, first ion implantation technology is first carried out, then performs second ion implantation technology；Or first
Second ion implantation technology is performed, then performs first ion implantation technology.
Compared with prior art, in ldmos transistor provided by the invention, isolation structure close to raceway groove side (that is, every
From structure away from drain region side) drift region in the buffering area of a transoid is set, it is anti-so as to form one by the buffering area
To P-N junction, to weaken the electric field of the isolation structure interface and semiconductor substrate surface, and then can avoid in the isolation
Stronger ionization by collision occurs at structural interface and triggers hot carrier's effect.So the ldmos transistor can be made not only to have
There are relatively low conducting resistance and larger breakdown voltage, and can further improve hot carrier's effect, and then described in raising
The service behaviour of ldmos transistor.
In addition, being based on ldmos transistor provided by the invention, the present invention also provides a kind of semiconductor devices and its formation side
Method, in the method for forming the semiconductor devices, by carrying out appropriate modification to the mask plate for defining resistive element,
So as to by formed buffering area when ion implantation technology with formed resistive element when ion implantation technology in same step
Perform, its one side can simplification of flowsheet, on the other hand be also not required to additionally increase a mask plate, saving cost of manufacture.
Brief description of the drawings
Fig. 1 is the structural representation of existing ldmos transistor；
Fig. 2 is the distribution map of hot carrier quantity in existing ldmos transistor；
Fig. 3 is the structural representation of the ldmos transistor in the embodiment of the present invention one；
Fig. 4 is the diagrammatic cross-section of the ldmos transistor in the embodiment of the present invention one shown in Fig. 3；
Fig. 5 is the distribution map of hot carrier quantity in the ldmos transistor in the embodiment of the present invention one；
Fig. 6 is the schematic flow sheet of the forming method of the ldmos transistor in the embodiment of the present invention two；
Fig. 7 a~Fig. 7 e are structural representation of the ldmos transistor in forming process in the embodiment of the present invention two；
Fig. 8 is the structural representation of the semiconductor devices in the embodiment of the present invention three；
Fig. 9 is the schematic flow sheet of the forming method of the semiconductor devices in the embodiment of the present invention four；
Figure 10 a~Figure 10 e are structural representation of the semiconductor devices in forming process in the embodiment of the present invention four.
Embodiment
As stated in the Background Art, for existing ldmos transistor under the working environment of high pressure, electric conductivity is bad.Study carefully it
Reason, it is when there is highfield in device, its channel carrier will obtain very high energy in the presence of this highfield
Measure and form hot carrier, so as to which these hot carriers can collide lattice atoms and the phenomenon for the ionization that collides, and produce secondary
Level electron hole pair, which part hole turns into substrate current, and the energy of part hot carrier can exceed silicon-silica
(Si-SiO) interface potential barrier, and then interfacial state is produced in the interface of silicon-silica (Si-SiO), and in gate oxide
Defect is produced, and then causes electron mobility to decline and influence the performance of device, i.e. due to hot carrier in jection (Hot
Carriers injection, HCI) influence of effect causes device performance not enough to understand.
Specifically as shown in Fig. 2 for existing ldmos transistor, the region of highfield then focuses primarily upon isolation
Structure 14 close to raceway groove side and drift region juncture area and drift region and semiconductor substrate surface juncture area (i.e.,
Region a) shown in Fig. 2, therefore above-mentioned two juncture area is also the region that electric current is more concentrated, corresponding is also to touch
Hit the intensity of ionization region the strongest.That is, as shown in Fig. 2 in existing ldmos transistor, ionization is collided the most
Strong position is region a, and is stretched out centered on a of region, and the intensity for the ionization that collides gradually weakens.
Therefore, the present invention provides a kind of ldmos transistor, further to optimize the performance of ldmos transistor.It is described
Ldmos transistor includes：Semiconductor substrate；Well region and drift region in the Semiconductor substrate；In the well region
Source region；Drain region in the drift region；Isolation structure in the drift region, the isolation structure is positioned at described
Between source region and the drain region；And in the drift region and in buffering area of the isolation structure away from drain region side,
The doping type of the buffering area is opposite with the doping type of the drift region.
In ldmos transistor provided by the invention, in isolation structure, close to raceway groove side, (that is, isolation structure is away from leakage
Area side) drift region in the buffering area of a transoid is set, so as to form a reverse P-N junction by the buffering area, to cut
The weak isolation structure can be avoided in the isolation structure in the electric field close to groove side and the juncture area of drift region
Interface stronger ionization by collision occurs and triggers hot carrier's effect, the performance of the ldmos transistor is further carried
Rise.
Ldmos transistor proposed by the present invention and forming method thereof is made below in conjunction with the drawings and specific embodiments further
Describe in detail.According to following explanation and claims, advantages and features of the invention will become apparent from.It should be noted that accompanying drawing
Non- accurately ratio is used using very simplified form and, only implemented conveniently, lucidly to aid in illustrating the present invention
The purpose of example.
<Embodiment one>
Fig. 3 is the structural representation of the ldmos transistor in the embodiment of the present invention one, and Fig. 4 is that the present invention shown in Fig. 3 is real
The diagrammatic cross-section of the ldmos transistor in example one is applied, with reference to shown in Fig. 3 and Fig. 4, the ldmos transistor includes：
Well region 120 and drift region 130 in semi-conductive substrate 110；
Source region 150 in the well region 120；
Drain region 160 in the drift region 130；
Isolation structure 140 in the drift region 130, also, the isolation structure 140 is located at the source region 150
Between the drain region 160；
In the drift region 130 and close to buffering area of the isolation structure 140 away from the side of drain region 160
170, the buffering area 170 is opposite with the doping type of the drift region 130.
In addition, in the present embodiment, in addition to being provided with isolation structure 140 in drift region 130, in ldmos transistor
Periphery be also equipped with isolation structure 141, the isolation structure 141 is used to make the ldmos transistor and other devices or crystalline substance
Body pipe is kept apart.
In the present embodiment, the doping type of the drift region 130 is N-type, then the doping type of the buffering area 170 is P
Type.In other embodiments, the doping type of the drift region 130 can also be p-type, and accordingly, the buffering area 170 is mixed
Miscellany type is N-type.
In ldmos transistor provided by the invention, by setting the buffering area 170 of a transoid to form a reverse P-N junction,
So as to alleviate the electric field of the interface of isolation structure 140 and substrate surface, and then can avoid larger in interface generation
Ionization by collision and trigger hot carrier's effect.
Preferably, the doping depth of the buffering area 170 is more than the thickness of the isolation structure 140, and the buffering area
170 are disposed proximate to isolation structure 140, i.e. the isolation structure 140 is at the interface 140a away from described one end of drain region 160
Covered by the buffering area 170.It is furthermore preferred that the isolation structure away from described one end of drain region 160 corner region (such as
Region shown in dotted line circle in Fig. 3) also covered by the buffering area 170, that is to say, that buffering area 170 also extends to isolation junction
The subregion of the bottom surface of structure 140 is so that the bottom surface of itself and isolation structure 140 is also covered by the part of buffering area 170, thus, original
Collide the buffering area 170 for ionizing and transoid being set on most strong interface zone, to avoid that hot carrier effect occurs in the region
Should.
As shown in Figure 3 and Figure 4, in the present embodiment, the drift region 130 is formed in the well region 120, and the drift
It is opposite with the doping type of the well region 120 to move area 130, i.e. when the doping type of the well region 120 is p-type, then drift region
130 doping type is N-type, and when the doping type of the well region 120 is N-type, then the doping type of the drift region 130 is
P-type.In the present embodiment, the doping type of the well region 120 is p-type, and the doping type of the drift region 130 is N-type.Such as
This, due to the doping type of the drift region 130 and the well region 120 on the contrary, the drift region 130 can be made to form a high resistance area
Domain, so as to having higher voltage dividing ability, and then the breakdown voltage of ldmos transistor can be effectively improved and can be reduced between source and drain
Parasitic capacitance.
In the ldmos transistor of the present embodiment, by setting the isolation structure 140, so as to increase LDMOS crystal
The guiding path of pipe, further to improve the breakdown voltage of the ldmos transistor.Specifically, the isolation structure 140 can be adopted
With fleet plough groove isolation structure, the material of the isolation structure 140 can be silica (SiO) or silicon nitride (SIN).In addition, work as
When the area of the drift region 130 is sufficiently large, the size of isolation structure 140 can not be reduced, directly form the buffering area 170
In the side of the isolation structure 140；If in order to not increase the size of the ldmos transistor, isolation structure 140 can be reduced
Size, such as, the isolation structure 140 can be reduced away from the one end in drain region 160.With specific reference to shown in Fig. 4, this
In embodiment, the isolation structure 140 is list structure, then now to isolation structure 140 carry out size reduction, equivalent to make every
Reduced in the width direction from structure 140, for example, an end position of the isolation structure 140 close to drain region 160 is constant, far
One end from drain region 160 is then reduced so that the cross sectional dimensions of isolation structure 140 reduces, with remote in isolation structure 140
The side in drain region 160 forms a region for accommodating the buffering area 170, in this way, can make formed with the buffering area 170
Ldmos transistor still keeps original size.
Referring next to shown in Fig. 3 and Fig. 4, the ldmos transistor also includes the grid in the Semiconductor substrate 110
Pole structure 210, the grid structure 210 is across the well region 120 and the drift region 130, and part is located at the isolation junction
On structure 140.Further, the grid structure 210 includes the gate dielectric layer 211 positioned at the surface of Semiconductor substrate 110, positioned at institute
State the gate electrode 212 on gate dielectric layer 211 and the side wall 213 positioned at the both sides of gate electrode 212.The gate dielectric layer 211
Material can be silica (SiO), hafnium oxide (HfO2) or other hafniums；The material of the gate electrode 212 can be with
For polysilicon or metal；The material of the side wall 213 can be silica (SiO) or silicon nitride (SIN).That is, by by described in
Gate electrode 212 is expanded on the gate dielectric layer 211 of drift region 130, serves as field plate, can weaken the surface of the drift region 130
Electric field, and then be advantageous to improve the breakdown voltage of the ldmos transistor.
The source electrode 150 and drain electrode 160 are located in the Semiconductor substrate 110 of both sides of the grid structure 210 respectively,
Wherein, the drain region 160 is located in the drift region 130, and the source region 150 is located in the well region 120.Preferably, in institute
Stating also has one first diffusion region 180 in drift region 130, the drain region 160 is located in first diffusion region 180.Enter one
Step, the doping type in the drain region 160, first diffusion region 180 and drift region 130 is consistent, i.e. the present embodiment
In, the doping type in the drain region 160, the first diffusion region 180 and drift region 130 is N-type.Specifically, the drift region
130 doping concentration is less than the doping concentration of first diffusion region 180.That is, by the way that drain region 160 is arranged at into drift region 130
In the first diffusion region 180 in, rather than directly the drain region 160 is arranged in the drift region 130, in this way, on the one hand
The doping concentration of drift region 130 is enough relative to the width of the drift region 130, also, the now drain region 160 to institute
Grid structure 210 is stated not change in the distance on channel direction, therefore can't be to the breakdown of the ldmos transistor
Voltage has an impact；On the other hand, can but have with the first diffusion region 180 in the drift region 130 by the way that drain region 160 is set
Effect lowers conducting resistance, so as to be advantageous to improve the performance of the ldmos transistor.
With continued reference to shown in Fig. 3 and Fig. 4, also there is one second diffusion region 190, the source region 150 in the well region 120
It is located in second diffusion region 190.Further, second diffusion region 190 and the doping type one of the well region 120
Cause, second diffusion region 190 is opposite with the doping type of the source region 150.For example, mixing when second diffusion region 190
When miscellany type is N-type, then the doping type of the well region 120 is also N-type, and now the doping type of the source region 150 is P
Type.In the present embodiment, the well region 120 and the doping type of second diffusion region 190 are p-type, the source region 150
Doping type is N-type.Specifically, the doping concentration of second diffusion region 190 is more than the doping concentration of the well region 120.
In the present embodiment, an epitaxial layer 111 is additionally provided with the Semiconductor substrate 110, the well region 120 is positioned at described
In epitaxial layer 111.Specifically, the epitaxial layer 111 is opposite with the doping type of the well region 120.In the present embodiment, the trap
The doping type in area 120 is p-type, and the doping type of the epitaxial layer 111 is N-type.In the ldmos transistor, by setting
Put an epitaxial layer 111, so as to can make the epitaxial layer 111 completely depleted under backward voltage, therefore epitaxial layer 111 with it is described
The depletion width at P-N junction surface that well region 120 joins is larger, the electric field at this can so weakened, and then can effectively carry
The breakdown voltage of high ldmos transistor.
As described above, in existing ldmos transistor, in juncture area of the isolation structure away from drain region side and drift region
And the juncture area of drift region and Semiconductor substrate is strong electric field region, i.e. the region is the strongest for the ionization that collides
Region.The service behaviour of ldmos transistor is influenceed to avoid producing strong ionization by collision in the strong electric field region,
In ldmos transistor provided by the invention, by setting the buffering area of a transoid in a strong electric field region, can avoid it is described every
Trigger hot carrier's effect from stronger ionization by collision occurs at structural interface.Fig. 5 is the LDMOS in the embodiment of the present invention one
The distribution map of hot carrier quantity in transistor, as shown in figure 5, due to there are the buffering area in the ldmos transistor,
Weaken the electric-field strength in juncture area (that is, b region Fig. 5 shown in) of the isolation structure 140 away from drain region side and drift region
Degree, collided the intensity of ionization so as to alleviate the juncture area.That is, ldmos transistor provided by the invention
In, the ionization that makes to collide it is the strongest be located away from the isolation structure 140, so as to avoid in isolation structure 140
Intersection produces interfacial state.As can be seen here, ldmos transistor provided by the invention not only have relatively low conducting resistance and compared with
Big breakdown voltage, and can also further improve hot carrier's effect, and then improve the workability of the ldmos transistor
Energy.
Further, by carrying out appropriate reduction in one end away from drain region to accommodate the buffering to isolation structure
Area, so as to be impacted to the size of ldmos transistor.Further, since it is now placed in the drift below the gate electrode
The width in area does not change, and the gate electrode is still partly covered in the top of the isolation structure, therefore, described
The characteristics such as the conducting resistance and breakdown voltage of ldmos transistor can't be affected.Table 1 is in the embodiment of the present invention one
Ldmos transistor and the comparison form of the performance of the existing ldmos transistor for being not provided with buffering area, as shown in table 1, pass through
Experimental comparison is found, although the width of the isolation structure of the ldmos transistor in the present embodiment is smaller, this set structure
Ldmos transistor and existing ldmos transistor conducting resistance, breakdown voltage and substrate current without obvious poor
It is different.That is, accommodating the buffering area by reducing the width of isolation structure, it is not but not to ldmos transistor
The parameter such as conducting resistance and breakdown voltage impacts, and can also on the basis of the size of ldmos transistor is not increased,
Improve hot carrier's effect, further to improve the performance of device.
Table 1
<Embodiment two>
Accordingly, the present invention also provides a kind of method for forming above-described ldmos transistor.Fig. 6 is real for the present invention
The schematic flow sheet of the forming method of ldmos transistor in example two is applied, Fig. 7 a- Fig. 7 e are LDMOS in instrument embodiment two of the present invention
The structural representation of the forming process of transistor, with reference to shown in Fig. 6 and Fig. 7 a- Fig. 7 e, the formation side of the ldmos transistor
Method includes：
Step S10, there is provided semi-conductive substrate 110, a well region 120 is respectively formed with the Semiconductor substrate 110
With a drift region 130, and an isolation structure 140 is formed in the drift region 130；
Step S20, a source region 150 is formed in the well region 120, a drain region 160 is formed in drift region 130, it is described
Source region 150 is located at the both sides of the isolation structure 140 with drain region 160 respectively, and in the isolation structure 140 away from the leakage
A buffering area 170, the buffering area 170 and the doping type of the drift region 130 are formed in the drift region 130 of the side of area 160
Conversely.
With specific reference to shown in Fig. 7 a, in the present embodiment, the drift region 130 is formed in the well region 140.Therefore, exist
In step S10, it can then be mixed prior to forming the well region 120 in Semiconductor substrate 110 in the well region 120 by ion
It is miscellaneous to form the drift region 130.Specifically, the well region 120 and drift region 130 can be formed by ion implantation technology,
Wherein, the ion implantation dosage of the well region 120 is preferably 3e+14/cm3~3e+17/cm3, the ion of the drift region 130
Implantation dosage is preferably 5e+14/cm3~5e+17/cm3.
After formed with drift region 130, the isolation structure 140 is formed in the drift region 130, specifically, institute
The formation for stating isolation structure 140 refers to following method：First, the Semiconductor substrate of etching part thickness is to form shallow trench；
Then, isolated material is filled in the shallow trench to form isolated film；Then, cmp planarization institute can be used
Isolated film is stated to form isolation structure.In the present embodiment, in addition to the isolation structure 140 in drift region 130, in shape
Into the outside in ldmos transistor region also need to be formed isolation structure 141, the isolation structure 141 is used to be formed
Ldmos transistor is isolated with other transistors or device, avoids interfering between different components.Wherein, the isolation
Structure 140 and isolation structure 141 can be formed in same processing step.
In addition, being formed in the present embodiment in ldmos transistor, also there is an epitaxial layer in the Semiconductor substrate 110
111, well region 120 is formed in the epitaxial layer 111, wherein, the epitaxial layer 111 can be formed using existing technology, herein
Do not repeat.Further, in the forming method of the ldmos transistor in the present embodiment, also it is included in drift region 130 and is formed
One first diffusion region 180, and one second diffusion region 190, first diffusion region 180 and second are formed in well region 120
Diffusion region 190 can be formed by ion implantation technology.
With continued reference to Fig. 6 and with reference to shown in Fig. 7 b- Fig. 7 e, in step S20, in the Semiconductor substrate 110 respectively
Form source region 150, drain region 160 and buffering area 170.Further, before the source region 150 and drain region 160 is formed, also wrap
Include in forming a grid structure 210 in the Semiconductor substrate 110.Wherein, because the buffering area 170 can pass through a mask plate
And ion implantation technology is formed in the specific region of drift region 130, therefore, the buffering area 170 and grid structure 210 with
And the formation order in source region 150 and drain region 160 does not limit herein.That is, described buffering area 170 can be in grid structure 210, source region
150 and drain region 160 formed before be formed in the Semiconductor substrate 110；Also can grid structure 210, source region 150 and
Drain region 160 forms the buffering area 170 after being formed in Semiconductor substrate 110；Or in the shape of grid structure 210
Into the buffering area 170 afterwards, is subsequently formed, then the source region 150 and drain region 160 are being formed.In the present embodiment, with preferential
Explanation is further explained exemplified by formation grid structure 210, source region 150 and drain region 160.
With specific reference to shown in Fig. 7 b, before source region 150 and drain region 160 is formed, in forming one in the Semiconductor substrate
Grid structure 210, the grid structure 210 is across the well region 120 and drift region 130, and part is located at the isolation
In structure 140.Specifically, the grid structure 210 includes a gate dielectric layer 211, a gate electrode 212 and positioned at grid electricity
The side wall 213 of the both sides of pole 212.In the present embodiment, the material of the gate dielectric layer 211 can be silica, the gate electrode 212
Material is polysilicon, and the material of the side wall 213 is silicon nitride.
With continued reference to shown in Fig. 7 b, distinguish in the both sides after the grid structure 210 for forming the grid structure 210
Source region 150 and drain region 160 are formed, wherein, source region 150 is located in the well region 120, and the drain region 160 is located at drift region
130, and the source region 150 is located at the both sides of the isolation structure 140 with the drain region 160 respectively.
Emphasis with reference to shown in figure 7c~Fig. 7 e, be respectively formed with grid structure 210, source region 150 and drain region 160 it
Afterwards, buffering area 170 is then formed in isolation structure 140 is away from the drift region 130 of the side of drain region 160, the buffering area 170
Doping type is opposite with the doping type of drift region 130.Specifically, the forming method of the buffering area 170 refers to walk as follows
Suddenly.
First, with reference to shown in figure 7c, position and the size that need to form the buffering area are defined using photoetching process.That is,
In the photoresist of spin coating in Semiconductor substrate one；Patterned photoresist 410 is formed after photoetching process is performed, it is described graphical
Photoresist 410 expose the region that need to be doped, and cover the region for being not required to be doped.
Then, continue shown in Fig. 7 c, can use described in ion implantation technology is formed in the drift region 130 at least once
Buffering area.In the present embodiment, using ion implantation technology three times respectively at the drift region 130 three different depth position shapes
The doped region mutually overlapping into three, the doped region of three different depth positions are collectively forming the buffering area.Due to ion note
The injection type of ion, implantation concentration and the characteristic for injecting depth can be flexibly accurately controlled by entering technique, therefore its injection
Foreign ion can be that control is adjusted in any position.Thus, can be by adjusting ion implanting in the present embodiment
Energy realizes the ion implanting of different depth position, i.e., as shown in figure 7d, respectively in drift region 130 after ion implanting three times
Middle formation shallow implant doped region 170a, middle injection doped region 170b and deep injection doped region 170c, these three doped region phases
It is mutually overlapping that the buffering area 170 is formed with combination.Multiple ion implanting is used to form buffering area 170, institute's shape can be effectively improved
Into the intermediate ion concentration distribution of buffering area 170 uniformity, it is larger in particular for the depth bounds for the buffering area 170 that need to be formed
When, the advantage of multiple ion implanting will be apparent from.Wherein, in the ion implantation technology of the buffering area 170, when needing to be formed
The doping type of buffering area when being p-type, then it can be boron ion (B) to inject ion, and when the doping for the buffering area that need to be formed
When type is N-type, then the ion injected can be phosphonium ion (P).Preferably, the agent injected in ion implantation process three times
Amount is 3e+12/cm3~3e+14/cm3.
Referring next to shown in Fig. 7 e, after formed with buffering area 170, photoresist is removed.So far, that is, being formed has transoid
The ldmos transistor of buffering area.
To sum up, in the forming method of ldmos transistor provided by the invention, by isolation structure away from drain region side
The buffering area of transoid is formed in drift region, so as to produce ionization by collision area the strongest in its ldmos transistor for being formed
Juncture area of the domain away from isolation structure and drift region, and then hot carrier's effect can be improved.
<Embodiment three>
Based on above-described ldmos transistor, the present invention also provides a kind of semiconductor with the ldmos transistor
Device, Fig. 8 is the structural representation of the semiconductor devices in the embodiment of the present invention three, and as Fig. 8 shows, the semiconductor devices includes
The resistive element 330 of ldmos transistor 100 and one as described in embodiment one.In high voltage integrated circuit, it usually needs apply to
Resistive element 330, and the inside of integrated circuit is directly integrated in, so that the physical dimension of the device of the formation subtracts
It is small.Therefore, in the present embodiment, by forming resistance member in setting a doped polysilicon layer 332 in semi-conductive substrate 110
Part 330.
Specifically, the ldmos transistor 100 is located on the first area 110a of Semiconductor substrate 110, resistive element
330 on the second area 110b of Semiconductor substrate 110, same in the Semiconductor substrate of the lower section of doped polysilicon layer 332
Formed with the well region 120.At present, the doped polysilicon layer 332 typically by polysilicon layer carry out ion implanting with
Make it have higher resistance value and form high resistant value polysilicon (High Resistance Polysilicon, HRP).Influence institute
Stating the factor of the resistance value of doped polysilicon layer 332 mainly includes：Thickness, the critical size (Critical of polysilicon layer
Dimension, CD) and ion implantation dosage etc..In the present embodiment, doped with boron ion (B), institute in the polysilicon layer
The ion implantation dosage for stating doped polysilicon layer 332 is preferably 3e+13/cm3~3e+15/cm3.Preferably, in the polysilicon
An insulating barrier 331 is additionally provided between layer 332 and the Semiconductor substrate, the material of the insulating barrier 331 can be silica
(SiO), hafnium oxide (HfO2) or other hafniums etc..
<Example IV>
Fig. 9 be the embodiment of the present invention four in semiconductor devices forming method schematic flow sheet, Figure 10 a~Figure 10 e
For structural representation of the semiconductor devices in the embodiment of the present invention four in forming process.As shown in figure 9, the semiconductor device
The forming method of part includes：
Step S100, there is provided semi-conductive substrate, a well region is formed in the Semiconductor substrate, served as a contrast in the semiconductor
A drift region is formed in firstth area at bottom, and an isolation structure is formed in the drift region；
Step S200, in forming a resistive element in the secondth area of the Semiconductor substrate, close to the isolation structure
A buffering area, the buffering area and the doping class of the drift region are formed in the drift region of ldmos transistor raceway groove side
Type is opposite.
With reference to shown in Figure 10 e and Figure 10 e, compared with embodiment two, the semiconductor devices formed in the present embodiment is not only
Including ldmos transistor, include the resistive element of a high value.The resistive element can pass through a doped polysilicon layer 332
Formed.Further, an insulating barrier 331 is also formed between the doped polysilicon layer 332 and Semiconductor substrate, wherein,
The material of the insulating barrier 331 can be silica.Specifically, the forming method of the polysilicon layer refers to walk as follows
Suddenly：First, in forming the insulating barrier 331 in Semiconductor substrate；Then, in forming polysilicon layer on the insulating barrier 331；So
Afterwards, ion doping is carried out to form doped polysilicon layer 332 to the part polysilicon layer by ion implantation technology.
In the present embodiment, the insulating barrier 331 can be made to use identical with the gate dielectric layer 211 in grid structure 210
Material is made, so as to form the gate dielectric layer 211 and insulating barrier 331 simultaneously in same processing step.Likewise,
The gate electrode 212 that polysilicon can be used to be formed in grid structure, so that in the gate electrode 212 and the resistive element 330
Polysilicon layer material it is also identical, then now the polysilicon layer can also be formed with gate electrode in same processing step, from
And optimize technique and cost can be saved.
With specific reference to shown in Figure 10 a, in depositing a medium on the first area 110a and the second area 110b of Semiconductor substrate 110
Layer, and photoetching and etch process are performed to form gate dielectric layer 211 and insulating barrier 331 respectively, wherein, the gate dielectric layer
211 across the well region 120 and drift region 130 and part is positioned at the top of the isolation structure 140.
Referring next to shown in Figure 10 b, a polysilicon is formed in the first area 110a and the second area 110b of Semiconductor substrate 110
Film, and gate electrode 212 and polysilicon layer 332a are formed by photoetching and etch process respectively, wherein, the shape of gate electrode 212
Described in Cheng Yu on gate dielectric layer 211, the polysilicon layer 332a is formed on the insulating barrier 331.Further, grid are being formed
After electrode 212, the both sides for being additionally included in the gate electrode 212 form a side wall 213 respectively.
Referring next to shown in Figure 10 c, spin coating photoresist, and photoetching is performed using a mask plate on semiconductor substrate 110
Technique is to form patterned photoresist 420.Wherein, the patterned photoresist 420, which exposes, need to carry out ion doping
Region, i.e., it need to form the region of doped polysilicon layer.Then, using ion implantation technology to the polysilicon that is not covered by photoresist
Layer 332a is doped to form the doped polysilicon layer 332 with certain resistance.In the present embodiment, made using boron ion (B)
For foreign ion injection in the polysilicon layer 332a to form doped polysilicon layer 332, wherein, the implantation dosage of boron ion
Preferably 3e+13/cm3~3e+15/cm3.
Further, in order to simplify processing step, cost of manufacture is saved, in the present embodiment, when making to form buffering area
Ion implantation technology is realized with ion implantation technology when forming the doped polysilicon layer in same processing step.Emphasis is joined
Examine shown in Figure 10 c~Figure 10 d, i.e. the modification to carrying out adaptability for defining the mask plate of doped polysilicon layer, to cause
The patterned photoresist 420 formed after photoetching process is performed, not only exposes the area that need to form doped polysilicon layer 332
Domain, also expose the region that need to form buffering area 170.And then the first ion implanting can performed with shape to polysilicon layer 332a
Into after doped polysilicon layer 332, the second ion implantation technology is continued executing with to form buffering area 170 in drift region 130, and
An extra mask plate need not be further added by define the position of buffering area and size, and then a photoetching process step can be saved
Suddenly.In addition, when performing ion implanting to form buffering area 170, in the Semiconductor substrate 110 under doped polysilicon layer 332
It can also form a doped region 340 accordingly.However, as described above, the ion implantation dosage of the buffering area 170 is preferably 3e+
12/cm3~3e+14/cm3, i.e. the ion implanting of the doped region 340 below the doped polysilicon layer 332, which is measured, is also
3e+12/cm3~3e+14/cm3, and the ion implantation dosage in the doped polysilicon layer 332 is preferably 3e+13/cm3~3e
+ 15/cm3, through comparison, it is seen that, the difference of both ion implantation dosages is simultaneously little, therefore, in doped polysilicon layer 332
The doped region 340 that lower section is additionally formed can't impact to the performance of the resistive element formed.
Referring next to shown in Figure 10 e, source region 150 and drain region 160 are formed respectively in the both sides of the grid structure 210,
The source region 150 is located in well region 120, and the drain region 160 is located in drift region 130, and source region 150 is distinguished with drain region 160
It is arranged at the both sides of isolation structure 140.In the present embodiment, the doped polysilicon layer 332 and buffering area 170 are in source region
150 and drain region 160 formation before formed.Certainly, and the type of embodiment two, the doped polysilicon layer 332 and slow
It can also be formed after source region 150 and drain region 160 are formed to rush area 170.
In the present embodiment, make the shapes in same processing step of the polysilicon layer 332a in gate electrode 212 and resistive element 330
Into, and by changing lithography mask version, make to be formed the ion implantation technology of buffering area 170 with formed doped polysilicon layer from
Sub- injection technology performs in same step, so as on the basis of the performance of formed device is not influenceed, optimize technique
Step simultaneously saves cost of manufacture.Certainly, in other embodiments, the gate electrode and the polysilicon layer in resistive element 330
Can be formed in different processing steps；And ion implantation technology during formation buffering area is with forming DOPOS doped polycrystalline silicon
The ion implantation technology of layer, likewise, can also be formed in different processing steps.
In the forming method of the semiconductor devices provided described in the present embodiment, by the way that ion when forming buffering area is noted
Enter technique to perform in same step with ion implantation technology when forming doped polysilicon layer, so as to simplification of flowsheet,
Save cost of manufacture.
Each embodiment is described by the way of progressive in this specification, what each embodiment stressed be and other
The difference of embodiment, between each embodiment identical similar portion mutually referring to.
Foregoing description is only the description to present pre-ferred embodiments, not to any restriction of the scope of the invention, this hair
Any change, the modification that the those of ordinary skill in bright field does according to the disclosure above content, belong to the protection of claims
Scope.
Claims (20)
1. a kind of ldmos transistor, including：
Well region and drift region in semi-conductive substrate；
Source region in the well region；
Drain region in the drift region；
Isolation structure in the drift region, the isolation structure is between the source region and the drain region；And
In the drift region and close to buffering area of the isolation structure away from drain region side, the buffering area and the drift
The doping type for moving area is opposite.
2. ldmos transistor as claimed in claim 1, it is characterised in that the well region and the doping type of the drift region
Conversely.
3. ldmos transistor as claimed in claim 1, it is characterised in that the doping depth of the buffering area be more than it is described every
From the thickness of structure.
4. ldmos transistor as claimed in claim 1, it is characterised in that it is remote that the buffering area covers the isolation structure
The one end in the drain region.
5. ldmos transistor as claimed in claim 4, it is characterised in that the buffering area extends to the isolation structure bottom
Portion is to cover the subregion of the isolation structure bottom.
6. ldmos transistor as claimed in claim 1, it is characterised in that the ldmos transistor is also included positioned at described half
Grid structure on conductor substrate, the grid structure is across the well region and drift region, and part is located at the isolation structure
Top.
7. ldmos transistor as claimed in claim 1, it is characterised in that the ldmos transistor is also included positioned at described half
Epitaxial layer in conductor substrate, the well region are located in the epitaxial layer, the doping type phase of the epitaxial layer and the well region
Instead.
8. ldmos transistor as claimed in claim 1, it is characterised in that the ldmos transistor also includes being located at the drift
The first diffusion region moved in area, the drain region are located in first diffusion region, the drain region, first diffusion region and institute
The doping type for stating drift region is identical.
9. ldmos transistor as claimed in claim 1, it is characterised in that the ldmos transistor also includes being located at the trap
The second diffusion region in area, second diffusion region are located at the side of the drift region, and the source region is positioned at the described second diffusion
In area, second diffusion region is identical with the doping type of the well region, second diffusion region and the doping class of the source region
Type is opposite.
10. ldmos transistor as claimed in claim 1, it is characterised in that the doping type of the well region and buffering area is N
Type, the source region, drain region and the doping type of drift region are p-type；Or the doping type of the well region and buffering area is p-type,
The source region, drain region and the doping type of drift region are N-type.
A kind of 11. forming method of ldmos transistor, it is characterised in that including：
Semi-conductive substrate is provided, formed with a well region and a drift region in the Semiconductor substrate, in the drift region
Formed with an isolation structure；And
A source region is formed in the well region, a drain region is formed in the drift region, in the isolation structure away from the leakage
A buffering area is formed in the drift region of area side, the source region is located at the both sides of the isolation structure with drain region respectively, described slow
It is opposite with the doping type of the drift region to rush area.
12. the forming method of ldmos transistor as claimed in claim 11, it is characterised in that the buffering area is using at least
Primary ions injection technology is formed.
13. the forming method of ldmos transistor as claimed in claim 12, it is characterised in that the buffering area is using three times
Ion implantation technology forms three mutually overlapping doped regions respectively at three different depth positions in the drift region, three
The doped region of different depth position is collectively forming the buffering area.
14. the forming method of ldmos transistor as claimed in claim 11, it is characterised in that forming the source region and institute
Also include before stating drain region：
In forming a grid structure in the Semiconductor substrate, the grid structure is across the well region and drift region, and part
On the isolation structure.
15. a kind of semiconductor devices, including ldmos transistor and a resistance as described in one of claim 1~10
Element, the ldmos transistor are located in the firstth area of semi-conductive substrate, and the resistive element is located at the Semiconductor substrate
The secondth area on.
16. semiconductor devices as claimed in claim 15, it is characterised in that the resistive element is the polysilicon of doping.
17. semiconductor devices as claimed in claim 15, it is characterised in that in the resistive element and the Semiconductor substrate
Between be additionally provided with an insulating barrier.
A kind of 18. forming method of semiconductor devices as described in one of claim 15~17, it is characterised in that bag
Include：
Semi-conductive substrate is provided, a well region is formed in the Semiconductor substrate, in the firstth area of the Semiconductor substrate
A drift region is formed, formed with an isolation structure in the drift region；And
A resistive element is formed in the secondth area of the Semiconductor substrate, in the drift region close to the isolation structure side
A buffering area is formed, the buffering area is opposite with the doping type of the drift region.
19. the forming method of semiconductor devices as claimed in claim 18, it is characterised in that the resistive element and buffering area
Forming method include：
A polysilicon layer is formed on a semiconductor substrate；
Photoetching process is performed in forming patterned photoresist in the Semiconductor substrate using a mask plate, it is described patterned
Photoresist exposes the region that need to form resistive element and the region that need to form buffering area；
The first ion implantation technology is performed, to not being doped by the polysilicon layer that the photoresist covers to form the resistance
Element；
The second ion implantation technology is performed, the drift region of the isolation structure side is doped to form the buffering area.
20. the forming method of ldmos transistor as claimed in claim 19, it is characterised in that first carry out first ion
Injection technology, then perform second ion implantation technology；Or second ion implantation technology is first carried out, then perform institute
State the first ion implantation technology.
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