CN101770983A - Production method of N-type high-voltage laterally diffused metal oxide semiconductor (LDNMOS) transsitor structure - Google Patents
Production method of N-type high-voltage laterally diffused metal oxide semiconductor (LDNMOS) transsitor structure Download PDFInfo
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Abstract
The invention relates to a production method of a N-type high-voltage laterally diffused metal oxide semiconductor transistor(LDNMOS) structure. The production method comprises the following steps of: forming narrow-groove isolation regions in a substrate layer; injecting phosphorus ions into two regions in the substrate layer; injecting phosphorous ions again into the regions in the substrate layer so as to form two N-type drift regions which are respectively taken as a source electrode and a drain electrode of the high-voltage laterally diffused metal oxide semiconductor structure; injecting p-type ions into the substrate layer so as to form a p-type drift region which surrounds the two N-type drift regions; injecting P-type ions in the substrate layer to form a P-type drift region around the two N-type drift regions; and sequentially forming an oxidation layer and a polysilicon layer on the substrate layer, wherein the oxidation layer and the polysilicon layer are positioned between the two N-type drift regions and taken as grid electrodes of the high-voltage laterally diffused metal oxide semiconductor structure. The method effectively lightens the HCI effect in the high-voltage LDNMOS structure and prolongs the lifetime of a transistor.
Description
Technical field
The present invention relates to a kind of manufacture method of high pressure lateral diffused metal oxide semiconductor transistor structure, more relate to a kind of manufacture method that reduces the high pressure lateral diffused metal oxide semiconductor transistor structure of hot carrier's effect.
Background technology
(Laterally Diffused Metal Oxidesemiconductor LDMOS) has critical role in integrated circuit (IC) design and in making to LDMOS transistor.For example high pressure LDMOS transistor (HV LDMOS) just is widely used in the chip for driving of thin film transistor liquid crystal display screen.
In power integrated circuit, high-voltage LDMOS is usually operated under the high voltage condition, and its device drain transverse electric field and current density be all much larger than general logical device, especially N transistor npn npn spare.Thereby hot carrier (Hot Carrier Injection, HCI) effect is a unavoidable problem in the high pressure LDNMOS design, also is the principal element that influences device reliability.Usually, the power of HCI effect can reflect by the substrate current Ib of measuring element.The logical device Ib that operating voltage is lower raises to increase afterwards earlier with grid voltage and reduces, and is unimodal shape, reduces this value and can effectively suppress the HCI effect.And in high pressure LDNMOS, Ib reduces with first the increase afterwards of the rising of grid voltage, increase again then, be double-peak shape, first peak value is relevant with the electric field near the channel region drain edge, and second peak value is relevant away from the other end electric field of channel region with drain electrode, and the size of two peak values all can directly influence the HCI effect of device.
The structural representation of present horizontal proliferation N type metal oxide semiconductor transistor (LDNMOS) as depicted in figs. 1 and 2, Fig. 1 is the schematic top plan view of known LDNMOS structure; The generalized section that Fig. 2 draws along dotted line l for LDNMOS among Fig. 1.LDNMOS comprises basalis B, oxide layer GOX, polysilicon layer P from bottom to top.Have N type drift region N-d, P type drift region P-d in the basalis B and be used to isolate N type drift region N-d and P type drift region P-d shallow channel isolation area (Shallow TrenchIsolation, STI).Wherein N type drift region N-d, P type drift region P-d are injected by P type ion respectively and N type ion injects and forms, the P type and the N type ion that have more on it by bigger concentration inject formed pin P+ and N+, and pin P+ and N+ are used for the LDNMOS and the external world are done ohmic contact.
In practical operation, the N type drift region N-d of polysilicon layer P both sides is used for doing source electrode and drain electrode, forms by injecting very dark P type ion (for example phosphonium ion) usually.Because the degree that P type ion need be squeezed into is deep, therefore, P type ion dose is big, energy is high, after squeezing into N type drift region N-d, edge at N type drift region N-d forms rough surface, and electric current can form electric field strength and concentrate the place through out-of-date among the N type drift region N-d, cause the HCI effect obvious, device lifetime is short.
Summary of the invention
The present invention proposes a kind of manufacture method that reduces high pressure horizontal proliferation N type metal oxide semiconductor transistor (LDNMOS) structure of hot carrier's effect, and it is unsmooth and the electric field strength that causes is concentrated, the tangible problem of HCI effect to solve the edge.
For the attainment of one's purpose, the present invention proposes a kind of manufacture method of high pressure lateral diffused metal oxide semiconductor transistor structure.This method may further comprise the steps: form shallow channel isolation area in basalis; Phosphonium ion is injected in two zones in the basad layer; Phosphonium ions are injected forming two N type drift regions in these zones in the basad once more layer, and these two N type drift regions are respectively as the source electrode and the drain electrode of high pressure lateral diffused metal oxide semiconductor transistor structure; Inject P type ion in the basad layer to form P type drift region around these two N type drift regions; And on the basalis between two N type drift regions, form oxide layer and polysilicon layer successively, as the grid of high pressure lateral diffused metal oxide semiconductor transistor structure, wherein isolate by shallow channel isolation area between two N type drift regions, P type drift region, the grid.
Further, the phosphate ion concentration that wherein injects to above-mentioned basalis for the second time is less than the phosphate ion concentration that injects for the first time.
Further, wherein shallow to the phosphonium ion position that above-mentioned basalis injects for the second time than the phosphonium ion position of injecting for the first time.
Further, after the step that forms above-mentioned oxide layer and polysilicon layer, also comprise: above above-mentioned N type drift region and above-mentioned P type drift region, form pin respectively, respectively ohmic contact is done in above-mentioned basalis, source electrode, drain electrode and the external world by denseer ion injection.
The manufacture method of the high pressure LDNMOS structure that the present invention proposes to N type drift region, makes that the phosphate ion concentration in the N type drift region is evenly distributed by twice injection phosphonium ion, and the edge-smoothing of N type drift region reduces the electric field strength concentrated area.This method has alleviated the HCI effect in the high pressure LDNMOS structure effectively, has increased the transistorized life-span.
Description of drawings
Fig. 1 is the schematic top plan view of known LDNMOS structure;
The generalized section that Fig. 2 draws along dotted line l for LDNMOS among Fig. 1.；
Figure 3 shows that the process chart of high pressure LDNMOS structure of the present invention;
Fig. 4 a～4f is depicted as the structural representation of high pressure LDNMOS manufacturing process of the present invention.
Figure 5 shows that the variation diagram of the base electric current of the high pressure LDNMOS structure among the present invention with grid voltage.
Fig. 6 a, 6b are depicted as the HCI test comparison figure of the high pressure LDNMOS structure among the present invention.
Embodiment
In order more to understand technology contents of the present invention, especially exemplified by specific embodiment and cooperate appended graphic being described as follows.
The N type drift region of LDNMOS of the present invention is similar to shallow doping diffusion (LightlyDoped Drain, LDD) structure and forming method thereof in the logical device.In gold oxygen semiconductor field effect transistor (MOSFET), for weaken the drain region electric field, to improve the hot electron degradation effect, near near the drain electrode a low-doped drain region being set, allow low-doped drain region also bear part voltage in raceway groove, this structure can prevent the hot electron degradation effect.
The LDD structure can be injected ion by single, also can inject ion several times, the normal scheme of using is to inject heavy dose of arsenic ion, the phosphonium ion of the less dosage that reinjects earlier, so, phosphonium ion surrounds arsenic ion in the LDD structure, forms electric-force gradient, compares the single injection and can further reduce electric field strength, suppress the HCI effect, improve the reliability of device.
And when the N type drift region of high pressure LDNMOS being carried out the ion injection, because regional deep (generally will penetrate STI) of its injection, if in substrate, implant arsenic ion by the energetic ion implanter, cause the damage of lattice easily, form dislocation and defective, cause serious electric leakage, influence the performance of high pressure LDNMOS.Therefore, in the technology of making high tension apparatus, the means that adopt the P+As ion to inject for two times are difficult to effectively suppress the HCI effect.
Present embodiment employing making operating voltage is that the LDNMOS structure of 32V is an example, and spiritual place of the present invention is described.
Figure 3 shows that the present invention makes the flow chart of steps of high pressure LDNMOS structure; Fig. 4 a～4f is depicted as the present invention and makes high pressure LDNMOS structural representation.Please also refer to Fig. 3, Fig. 4 a～4f.
Step S301:(such as Fig. 4 a) form shallow channel isolation area in basalis (ShallowTrenchIsolation STI), is used to isolate follow-up N type drift region N-d that forms and P type drift region P-d in basalis B.
Step S303:(such as Fig. 4 b) interior two the zone injection phosphonium ion of basad layer.Here two of indication zones determine that method is as follows: select the zone that desire forms grid earlier between two adjacent STI, G ' shown in Fig. 4 b, the selected again zone with the only adjacent STI of regional G ' is the zone that desire forms source electrode and drain electrode, prepares to inject phosphonium ion.In the present embodiment, basalis B is a P type substrate, injects phosphonium ion and forms source S and the drain D of N type drift region N-d as LDNMOS.
Step S305:(such as Fig. 4 c) phosphonium ions are injected to form N type drift region in these two zones in the basad once more layer.Formed N type drift region is as the source electrode and the drain electrode of high pressure LDNMOS structure among the step S305.
The phosphate ion concentration that is injected in step S303 position big, that inject is dark.Because the electrical parameter of the final LDNMOS structure that forms is identical with the electrical parameter that single injects the formed LDNMOS structure of phosphonium ion in the present embodiment, therefore, though the phosphate ion concentration that is injected in step S303 is bigger, still the phosphate ion concentration that injects less than single, therefore also can to inject the N type drift region of phosphonium ion than single level and smooth at the edge of the N type drift region that forms in the adjacent channel place, and everywhere electric field strength also reduces on year-on-year basis.
It is more shallow than the position of step S303 that the phosphate ion concentration that is injected in step S305 is lower than the position of concentration, injection of step S303, but still darker than STI.
The formed N type of the phosphonium ion drift region N-d edge-smoothing that step S303 and S305 inject, near and can not form outstanding especially border away from the drain electrode N type drift region at channel region place, electric field strength can be too unconcentrated in certain.Further, the phosphonium ion variation gently is distributed in the N type drift region N-d, and electric field strength can effectively be reduced.
Step S307:(such as Fig. 4 d) inject P type ion to form P type drift region in the basad layer.The P type drift region P-d that is formed with annular in the source S and drain D (the N type drift region) periphery of high pressure LDNMOS structure is with drawing as basalis B.
Step S309:(such as Fig. 4 e) on basalis, form oxide layer and polysilicon layer successively.
Usually oxide layer GOX utilizes wet method growth oxide layer GOX, reacted by the silicon among oxygen atom and the basalis B, thereby the oxide of generation silicon finally forms oxide layer GOX on basalis B.The present invention is not as limit.
Oxide layer GOX goes up the grid G of the polysilicon layer P of formation as LDNMOS.
Step S311:(such as Fig. 4 f) above N type drift region and P type drift region, form pin respectively.The N type ion that N type drift region N-d has by bigger concentration injects formed pin N+, and pin N+ is used for source S and drain D and the external world are done ohmic contact.The P type ion that has on the P type drift region P-d by bigger concentration injects formed pin P+, and pin P+ is used for the basalis B and the external world are done ohmic contact.
The data of position, size and the degree of depth of P type drift region in the present embodiment and N type drift region are provided with according to technological requirement according to those skilled in the art, and the present invention is not limited.
Figure 5 shows that the variation diagram of the substrate current of the high pressure LDNMOS structure among the present invention with grid voltage.Test condition is that (being determined by the width in source region and drain region)/length is 50/2.5 for the channel width of LDNMOS structure.Inject on the drain D of LDNMOS of phosphonium ion making alive Vd=32V and 35.2V respectively at single, inject for two times on the drain D of LDNMOS of phosphonium ions under the making alive Vd=32V and these four kinds of situations of 35.2V, (wherein 35.2V is that 1.1 times of values of bearing voltage of high pressure LDNMOS are to carry out destructive test), bias voltage on the grid G rises to 35V from 0, measure the current Ib among the substrate B, obtain curve as shown in Figure 5.
Wherein dotted line represents that single injects the measurement result of the LDNMOS structure of phosphonium ion, and solid line is represented the measurement result of the LDNMOS structure of two injection phosphonium ions.By obtaining following result among Fig. 5:
Table 1
By the brief summary of last table clearly as can be seen, adopt the high pressure LDNMOS structure of injecting phosphonium ion to N type drift region mode two times, current peak is lower among the substrate B, can know by inference, Electric Field Distribution in the LDNMOS structure that the method according to this invention is made is even, and intensity is lower.
Fig. 6 a, 6b are depicted as the HCI test comparison figure of the high pressure LDNMOS structure among the present invention.
Fig. 6 a is depicted as the LDNMOS test model of getting a plurality of singles injection phosphonium ions and tests at HCI, simulate the useful life of this LDNMOS structure, the coordinate that is intersected by matched curve and abscissa illustrates, find out that by Fig. 6 a the life-span that single injects the LDNMOS test model of phosphonium ion is 0.0525 year.
Fig. 6 b is depicted as the LDNMOS test model of getting a plurality of two injection phosphonium ions and tests (direct current) at HCI, simulate the useful life of this LDNMOS structure, the coordinate that is intersected by matched curve and abscissa illustrates, find out that by Fig. 6 b the life-span that single injects the LDNMOS test model of phosphonium ion is 0.373 (industrywide standard is greater than 0.2 year).
From Fig. 6 a and Fig. 6 b more as can be seen, the LDNMOS according to method among the present invention is made has alleviated the HCI effect, thereby has had the longer life-span.
Though the present invention discloses as above with preferred embodiment, so it is not in order to limit the present invention.The persond having ordinary knowledge in the technical field of the present invention, without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations.Therefore, protection scope of the present invention is as the criterion when looking claims person of defining.
Claims (4)
1. the manufacture method of a high pressure lateral diffused metal oxide semiconductor transistor structure is characterized in that, may further comprise the steps:
In basalis, form shallow channel isolation area;
Phosphonium ion is injected in two zones in above-mentioned basalis;
Phosphonium ions are injected forming two N type drift regions in described two zones in above-mentioned basalis once more, and above-mentioned these two N type drift regions are respectively as the source electrode and the drain electrode of high pressure lateral diffused metal oxide semiconductor transistor structure;
In above-mentioned basalis, inject P type ion to form P type drift region around above-mentioned these two N type drift regions; And
On the basalis between above-mentioned two N type drift regions, form oxide layer and polysilicon layer successively, as the grid of high pressure lateral diffused metal oxide semiconductor transistor structure, isolate by above-mentioned shallow channel isolation area between wherein above-mentioned two N type drift regions, above-mentioned P type drift region, the above-mentioned grid.
2. the manufacture method of high pressure lateral diffused metal oxide semiconductor transistor structure according to claim 1 is characterized in that, wherein the phosphate ion concentration that injects to above-mentioned basalis for the second time is less than the phosphate ion concentration that injects for the first time.
3. the manufacture method of high pressure lateral diffused metal oxide semiconductor transistor structure according to claim 1 is characterized in that, and is wherein shallow than the phosphonium ion position of injecting for the first time to the phosphonium ion position that above-mentioned basalis injects for the second time.
4. the manufacture method of high pressure lateral diffused metal oxide semiconductor transistor structure according to claim 1, it is characterized in that, after the step that forms above-mentioned oxide layer and polysilicon layer, also comprise: above above-mentioned N type drift region and above-mentioned P type drift region, form pin respectively, respectively ohmic contact is done in above-mentioned basalis, source electrode, drain electrode and the external world by denseer ion injection.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102683187A (en) * | 2012-05-09 | 2012-09-19 | 上海宏力半导体制造有限公司 | Transverse double-diffusion MOS (metal oxide semiconductor) device and manufacturing method thereof |
| CN104916575A (en) * | 2014-03-11 | 2015-09-16 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of semiconductor device |
| CN107887437A (en) * | 2016-09-30 | 2018-04-06 | 中芯国际集成电路制造(上海)有限公司 | Ldmos transistor and forming method thereof, semiconductor devices and forming method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1967870A (en) * | 2005-11-16 | 2007-05-23 | 台湾积体电路制造股份有限公司 | Semiconductor structure and its forming method, transverse diffusion p-type mos device |
| CN101447433A (en) * | 2007-11-27 | 2009-06-03 | 上海华虹Nec电子有限公司 | Manufacturing method of double diffusion field effect transistor |
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2010
- 2010-01-12 CN CN201010022706A patent/CN101770983A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1967870A (en) * | 2005-11-16 | 2007-05-23 | 台湾积体电路制造股份有限公司 | Semiconductor structure and its forming method, transverse diffusion p-type mos device |
| CN101447433A (en) * | 2007-11-27 | 2009-06-03 | 上海华虹Nec电子有限公司 | Manufacturing method of double diffusion field effect transistor |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102683187A (en) * | 2012-05-09 | 2012-09-19 | 上海宏力半导体制造有限公司 | Transverse double-diffusion MOS (metal oxide semiconductor) device and manufacturing method thereof |
| CN102683187B (en) * | 2012-05-09 | 2016-09-28 | 上海华虹宏力半导体制造有限公司 | Lateral double-diffused metal-oxide semiconductor device and manufacture method thereof |
| CN104916575A (en) * | 2014-03-11 | 2015-09-16 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of semiconductor device |
| CN104916575B (en) * | 2014-03-11 | 2018-03-16 | 中芯国际集成电路制造(上海)有限公司 | A kind of manufacture method of semiconductor devices |
| CN107887437A (en) * | 2016-09-30 | 2018-04-06 | 中芯国际集成电路制造(上海)有限公司 | Ldmos transistor and forming method thereof, semiconductor devices and forming method thereof |
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