TWI525813B - Transistor device and manufacturing method thereof - Google Patents

Description

Transistor device and method of manufacturing same

The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a transistor device and a method of fabricating the same.

With the development of semiconductor technology, semiconductor components continue to evolve. These semiconductor elements have been widely used in electronic products.

Among them, the transistor is a solid-state semiconductor component used as a voltage amplifier, an audio amplifier, a radio frequency amplifier, a voltage regulator circuit or a switch. The transistor has the advantages of small size, high efficiency, long life and high speed, which makes the transistor widely used in various electronic products. In recent years, it has developed a transistor that is resistant to high voltage and can withstand high power.

The present invention relates to a transistor device and a method of fabricating the same, which utilizes a shallow trench isolation structure having a suspended island active region design such that a breakdown voltage can be increased and a turn-on-resistance (Ron) Can be effectively reduced.

According to a first aspect of the present invention, an electro-optical device is proposed. The crystal device comprises a substrate, a first well, a second well, a shallow trench isolation structure, a source, a drain and a gate. The first well is disposed in the substrate. The second well is disposed in the substrate. The shallow trench isolation structure is disposed in the second well. The shallow trench isolation structure has at least one floating island active region. The source is disposed in the first well. The bungee is placed in the second well. Suspended island active zone The conductivity type of the bungee is opposite or the same. The gate is disposed above the first well and the second well and overlaps with the first well and the second well.

According to a second aspect of the present invention, a method of fabricating a transistor device is presented. The manufacturing method of the transistor device includes the following steps. A substrate is provided. A first well is formed in the substrate. A second well is formed in the substrate. A shallow trench isolation (STI) is formed in the second well. The shallow trench isolation structure has at least one floating island active region. A source is formed in the first well. Form a pole in the second well. The suspended island active region is opposite or identical to the conductivity type of the drain. A gate is formed above the first well and the second well, and the gate overlaps with the first well and the second well.

In order to better understand the above and other aspects of the present invention, the following specific embodiments, together with the drawings, are described in detail below:

The following is a detailed description of the embodiments, which are intended to be illustrative only and not to limit the scope of the invention. In addition, the drawings in the embodiments are omitted to partially illustrate the technical features of the present invention.

1 to 2, FIG. 1 is a plan view of a transistor device 100 of the present embodiment, and FIG. 2 is a cross-sectional view of the transistor device 100 of FIG. 1 taken along a section line 2-2. The crystal device 100 includes a substrate 110, a first well 141, a second well 142, a shallow trench isolation (STI) 150, a source 170S, a drain 170D, and a gate. Extreme 180G.

The substrate 110 is, for example, a P-type germanium substrate or an N-type germanium substrate. The first well 141 and the second well 142 are, for example, P-type wells doped with boron (Bon), or elements such as phosphorous (P), arsenic (As) or antimony (Sb). N-type well. In the present embodiment, the substrate 110 is exemplified by a P-type germanium substrate. The first well 141 and the second well 142 are respectively illustrated by a P-type well and an N-type well. The first well 141 and the second well 142 are disposed in the substrate 110. As shown in FIG. 2, the first well 141 and the second well 142 may be separated. In another embodiment, the first well 141 and the second well 142 can be connected.

Some shallow trench isolation structures 150 are disposed within the second well 142 and surrounded by the second well 142. The shallow trench isolation structure 150 has at least one floating island of diffusion 150a. As shown in FIG. 1, the shallow trench isolation structure 150 has a plurality of floating island active regions 150a. The floating island active regions 150a are arranged along a straight line, and the floating island active regions 150a are not connected. The periphery of the suspended island active region 150a is covered by the shallow trench isolation structure 150 without being injected with current or applying a voltage.

The source 170S is disposed in the first well 141 and the drain 170D is disposed in the second well 142. The source 170S and the drain 170D are, for example, an N-type heavily doped region or a P-type heavily doped region. In this embodiment, the source 170S and the drain 170D are N-type heavily doped regions. The gate 180G is disposed above the first well 141 and the second well 142 and overlaps a portion of the first well 141 and the second well 142. The material of the gate 180G is, for example, a polysilicon. The source 170S, the drain 170D and the gate 180G form a laterally diffused metal oxide semiconductor (laterally diffused metal oxide semiconductor). LDMOS).

In terms of the design of the suspended island active region 150a, the suspended island active region 150a of the present embodiment is disposed within the shallow trench isolation structure 150 rather than under the shallow trench isolation structure 150. Therefore, the channel of the drain 170D to the source 170S is not elongated, and the turn-on-resistance (Ron) can be kept at a low level.

Further, the floating island active region 150a is located between the drain 170D and the source 170S, so that the breakdown voltage can be increased, and the on-resistance (Ron) can be effectively reduced.

As shown in FIG. 1, the width W1 of the shallow trench isolation structure 150 is about three times the width W2 of the suspended island active region 150a in terms of the relationship between the shallow trench isolation structure 150 and the suspended island active region 150a. And the suspended island active region 150a is substantially located at the center of the shallow trench isolation structure 150. That is, the width W3, the width W2, and the width W4 are substantially about 1:1:1.

Further, as shown in Fig. 1, the number of suspended island-shaped active regions 150a may be greater than or equal to 2, and several island-like structures are formed. In one embodiment, the number of floating island active regions 150a may also be one, forming a long strip structure. When the suspended island active region 150a adopts several island structures, the structural strength of the shallow trench isolation structure 150 can be maintained. When the floating island active region 150a adopts a single elongated structure, the suspended island active region 150a can be maximized.

As shown in FIG. 1 , in the present embodiment, the floating island active region 150 a adopts several island structures, and the distance D1 between the adjacent floating island active regions 150 a is greater than or equal to 0.3 micrometers (μm) to effective The structural strength of the shallow trench isolation structure 150 is maintained, but the spacing D1 can be varied and is not limited to 0.3 microns in different process generations or in conjunction with different design rules.

Further, as shown in Fig. 2, the deeper the depth L1 of the suspended island active region 150a, the deeper the depth L1 of the suspended island active region 150a, the greater the effect can be exhibited. However, the depth L1 of the floating island active region 150a must still be less than the thickness L2 of the shallow trench isolation structure 150 to avoid affecting the channel of the drain 170D to the source 170S.

As shown in FIG. 2, in terms of the relationship between the gate 180G and the floating island active region 150a, the gate 180G and the floating island active region 150a may have no overlap or may partially overlap. When the gate 180G partially overlaps the floating island active region 150a, the breakdown voltage and the on-resistance (Ron) are further affected.

Referring to FIG. 2, the transistor device 100 further includes a deep well 130 and a buried layer 120 in terms of conductivity type and concentration of the floating island active region 150a. The deep well 130 and the buried layer 120 are, for example, N-type or P-type. In this embodiment, both the deep well 130 and the buried layer 120 are N-type. The deep well 130 is disposed in the substrate 110. The second well 142 and the first well 141 are disposed within the deep well 130. The conductivity type of the floating island active region 150a may be the same as or opposite to the conductivity type of the drain electrode 170D, and the conductivity type of the floating island active region 150a is preferably the same as that of the drain electrode 170D. The concentration of the suspended island active zone 150a is of the same order of magnitude as the concentration of the deep well 130.

Please refer to FIGS. 3A-3E for a flowchart of a method of manufacturing the transistor device 100 of the present embodiment. First, as shown in Fig. 3A, a substrate 110 is provided. Next, the buried layer 120 and the deep well 130 are formed on the substrate 110. in. The first well 141 is then formed within the deep well 130. Next, a second well 142 is formed within the deep well 130. In another embodiment, after the substrate 110 is provided, a buried layer 120 is formed on top of the substrate 110, and then an epitaxial layer is formed over the buried layer 120 to accommodate the deep well 130, the first well 141, and the second to be formed later. Well 142.

Then, as shown in FIG. 3B, a shallow trench isolation structure 150 is formed in the second well 142 while defining a gap 150b between the shallow trench isolation structures 150.

Next, as shown in FIG. 3C, a region to be ion implanted is defined by a mask (not shown) to form a floating island active region 150a in the gap 150b. In this step, the process time and energy intensity are appropriately controlled such that the depth L1 of the floating island active region 150a is smaller than the thickness L2 of the shallow trench isolation structure 150.

Then, as shown in FIG. 3D, a region to be ion implanted is defined by a mask (not shown) to form a source 170S and a heavily doped region 170 in the first well 141, and a drain 170D is formed. Within the second well 142.

Next, as shown in FIG. 3E, the gate 180G is formed over the first well 141 and the second well 142. The transistor device 100 is thus completed.

In this embodiment, the fabrication process of the transistor device 100 does not require additional cost, and the suspension island active region 150a is disposed within the shallow trench isolation structure 150 to increase the breakdown voltage. The on-resistance (Ron) can be effectively reduced.

In summary, although the present invention has been disclosed above by way of example, it is not intended to limit the present invention. Those who have ordinary knowledge in the technical field of the present invention can make various changes and refinements without departing from the spirit and scope of the present case. Therefore, the scope of protection of this case is subject to the definition of the scope of the patent application attached.

100‧‧‧Optical device

110‧‧‧Base

120‧‧‧buried layer

130‧‧‧Shenjing

141‧‧‧First Well

142‧‧‧Second well

150‧‧‧Shallow trench isolation structure

150a‧‧‧suspension island active area

150b‧‧‧ gap

170‧‧‧ heavily doped area

170D‧‧‧Bungee

170S‧‧‧ source

180G‧‧‧ gate

D1‧‧‧ spacing

L1, L2‧‧‧ Depth

W1, W2, W3, W4‧‧‧ width

FIG. 1 is a plan view showing a transistor device according to an embodiment.

2 is a cross-sectional view of the transistor device of FIG. 1 taken along section line 2-2.

3A to 3E are flow charts showing a method of manufacturing the transistor device of the embodiment.

100‧‧‧Optical device

110‧‧‧Base

120‧‧‧buried layer

130‧‧‧Shenjing

141‧‧‧First Well

142‧‧‧Second well

150‧‧‧Shallow trench isolation structure

150a‧‧‧suspension island active area

170‧‧‧ heavily doped area

170D‧‧‧Bungee

170S‧‧‧ source

180G‧‧‧ gate

L1, L2‧‧‧ Depth

Claims (16)

A transistor device includes: a substrate; a first well disposed in the substrate; a second well disposed in the substrate; a shallow trench isolation (STI), Provided in the second well, the shallow trench isolation structure surrounds a periphery of at least one floating island of floating diffusion; one source is disposed in the first well; and one drain is disposed in the second In the well, the conductivity type of the floating island active region is opposite or the same as the conductivity type of the drain electrode; and a gate disposed on the first well and the second well and partially with the first well and the first The two wells overlap. The transistor device of claim 1, wherein the gate partially overlaps the floating island active region. The transistor device of claim 1, wherein the depth of the floating island active region is less than the thickness of the shallow trench isolation structure. The transistor device of claim 1, wherein the shallow trench isolation structure has a width that is three times the width of the floating island active region. The transistor device of claim 1, wherein the floating island active region is substantially located at a center of the shallow trench isolation structure. The transistor device of claim 1, wherein the number of the at least one floating island active region is greater than or equal to two, the suspensions The island active areas are isolated from each other. The transistor device of claim 6, wherein a distance between the suspended island active regions is greater than or equal to 0.3 micrometers (um). The transistor device of claim 1, further comprising: a deep well disposed on the substrate, the second well and the first well disposed in the deep well, the concentration of the suspended island active region and The concentration of the deep well is of the same order of magnitude. A method of manufacturing a crystal device, comprising: providing a substrate; forming a first well in the substrate; forming a second well in the substrate; forming a shallow trench isolation structure STI) in the second well, the shallow trench isolation structure surrounds a periphery of at least one floating island of floating diffusion; forming a source in the first well; forming a bungee in the second well Internally, the suspended island active region is opposite or identical to the conductivity type of the drain; and a gate is formed over the first well and the second well, the gate and a portion of the first well and the second well overlap. The method of fabricating a transistor device according to claim 9, wherein in forming the gate, the gate partially overlaps the floating island active region. The method of manufacturing a transistor device according to claim 9, wherein in the step of forming the shallow trench isolation structure, the depth of the floating island active region is smaller than the thickness of the shallow trench isolation structure. The method of manufacturing a transistor device according to claim 9, wherein in the step of forming the shallow trench isolation structure, the width of the shallow trench isolation structure is three times the width of the floating island active region. The method of manufacturing a transistor device according to claim 9, wherein in the step of forming the shallow trench isolation structure, the floating island active region is substantially located at a center of the shallow trench isolation structure. The method of manufacturing a transistor device according to claim 9, wherein in the step of forming the shallow trench isolation structure, the number of the at least one floating island active region is greater than or equal to two. The method of manufacturing a transistor device according to claim 14, wherein in the step of forming the shallow trench isolation structure, the distance between the adjacent floating island active regions is greater than or equal to 0.3 micrometers (micrometer, um). . The method of manufacturing a transistor device according to claim 9, wherein before the step of forming the second well and the step of forming the first well, the manufacturing method further comprises: forming a deep well on the substrate, The second well and the first well are disposed in the deep well, and the concentration of the suspended island active zone is of the same order of magnitude as the concentration of the deep well.