CN103515414B - Transistor device and manufacturing method thereof - Google Patents
Transistor device and manufacturing method thereof Download PDFInfo
- Publication number
- CN103515414B CN103515414B CN201210212660.7A CN201210212660A CN103515414B CN 103515414 B CN103515414 B CN 103515414B CN 201210212660 A CN201210212660 A CN 201210212660A CN 103515414 B CN103515414 B CN 103515414B
- Authority
- CN
- China
- Prior art keywords
- trap
- active area
- isolation structure
- plough groove
- fleet plough
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 238000002955 isolation Methods 0.000 claims abstract description 40
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 239000000725 suspension Substances 0.000 claims description 53
- 238000000034 method Methods 0.000 claims description 18
- 230000005516 deep trap Effects 0.000 claims description 17
- 238000009792 diffusion process Methods 0.000 claims description 4
- 230000015556 catabolic process Effects 0.000 description 8
- 239000004065 semiconductor Substances 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 229910052787 antimony Inorganic materials 0.000 description 2
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 229910001423 beryllium ion Inorganic materials 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005034 decoration Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Element Separation (AREA)
- Junction Field-Effect Transistors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The present invention discloses a transistor device and a manufacturing method thereof. The transistor device comprises the following components: a substrate, a first trap, a second trap, a shallow trench isolation structure, a source, a drain and a grid. The first trap is arranged in the substrate. The second trap is also arranged in the substrate. The shallow trench isolation structure is arranged in the second trap. The shallow trench isolation structure is provided with at least one suspended island-shaped active region. The source is arranged in the first trap. The drain is arranged in the second trap. The conductive type of the suspended island-shaped active region is opposite from or same with the conductive type of the drain. The grid is arranged above the first trap and the second trap and is overlapped with partial first trap and partial second trap.
Description
Technical field
The present invention relates to a kind of semiconductor device and its manufacture method, and more particularly to a kind of transistor unit and its system
Make method.
Background technology
With the development of semiconductor technology, semiconductor element is constantly weeded out the old and bring forth the new.These semiconductor elements widely should
In electronic product.
Wherein, transistor is a kind of solid semiconductor element, to put as voltage amplifier, audio frequency amplifier, radio frequency
Big device, mu balanced circuit or switch.Transistor has the advantages that small volume, efficiency high, life-span length and speed are fast so that transistor is wide
It is general to be applied in various electronic product.In recent years, more develop it is high pressure resistant, powerful transistor can be born.
The content of the invention
It is an object of the invention to provide a kind of transistor unit and its manufacture method, it utilizes fleet plough groove isolation structure to have
There is the design of suspension island active area so that breakdown voltage (breakdown voltage) can increase, and conducting resistance
(turn-on-resistance, Ron) can be effectively reduced.
It is the first aspect of the invention up to above-mentioned purpose, proposes a kind of transistor unit.Transistor unit includes one
Substrate, one first trap, one second trap, a fleet plough groove isolation structure, a source electrode, a drain electrode and a grid.First trap is arranged at base
Among bottom.Second trap is arranged among substrate.Fleet plough groove isolation structure is arranged in the second trap.Fleet plough groove isolation structure has extremely
A few suspension island active area.Source electrode is arranged in the first trap.Drain electrode is arranged in the second trap.Suspension island active area and drain electrode
Conduction type it is contrary or identical.Grid is arranged on the first trap and the second trap and the first trap and the second trap with part are handed over
It is folded.
Second aspect of the invention, proposes a kind of manufacture method of transistor unit.The manufacturer of transistor unit
Method is comprised the following steps.One substrate is provided.One first trap (well) is formed among substrate.Formed one second trap in substrate it
In.A fleet plough groove isolation structure (Shallow trench isolation, STI) is formed in the second trap.Shallow trench isolation junction
Structure has an at least suspension island active area.A source electrode is formed in the first trap.Form one to drain in the second trap.Suspension island
Active area is contrary or identical with the conduction type of drain electrode.A grid is formed on the first trap and the second trap, grid and part
First trap and the second trap are overlapping.
In order to know more about to the above-mentioned and other aspect of the present invention, special embodiment below, and coordinate institute's accompanying drawings, make detailed
Carefully it is described as follows：
Description of the drawings
Fig. 1 is the top view of a transistor unit of one embodiment of the invention；
Fig. 2 is the sectional view of the transistor unit along section line 2-2 of Fig. 1；
Fig. 3 A～Fig. 3 E are the flow chart of the manufacture method of the transistor unit of this embodiment of the invention.
Main element symbol description
100：Transistor unit
110：Substrate
120：Buried horizon
130：Deep trap
141：First trap
142：Second trap
150：Fleet plough groove isolation structure
150a：Suspension island active area
150b：Gap
170：Heavily doped region
170D：Drain electrode
170S：Source electrode
180G：Grid
D1：Spacing
L1、L2：Depth
W1、W2、W3、W4：Width
Specific embodiment
Embodiment set forth below is described in detail, and embodiment can't limit the present invention only to illustrate as example
The scope to be protected.Additionally, the element of the schema clipped in embodiment, to clearly show that the technical characterstic of the present invention.
Fig. 1～Fig. 2 is refer to, Fig. 1 illustrates the top view of a transistor unit 100 of the present embodiment, and Fig. 2 illustrates Fig. 1's
Sectional view of the transistor unit 100 along section line 2-2.Transistor unit 100 includes a substrate 110, one first trap (well)
141st, one second trap 142, a fleet plough groove isolation structure (shallow trench isolation, STI) 150, one source electrode 170S,
An one drain electrode 170D and grid 180G.
Substrate 110 is, for example, a P-type silicon substrate or a N-type silicon substrate.First trap 141 and the second trap 142 e.g. adulterate
The p-type trap or doping phosphorus (phosphorous, P), arsenic (arsenic, As) or antimony of boron (boron, B) element
The N-type trap of elements such as (antimony, Sb).In the present embodiment, substrate 110 is explained by taking P-type silicon substrate as an example, the first trap
141 and second trap 142 explain by taking p-type trap and N-type trap as an example respectively.First trap 141 and the second trap 142 are arranged at substrate 110
Among.As shown in Fig. 2 the first trap 141 and the second trap 142 can separate.In another embodiment, the first trap 141 and the second trap
142 can connect.
Some fleet plough groove isolation structures 150 are arranged in the second trap 142, and are surround by the second trap 142.Shallow trench is isolated
Structure 150 has an at least suspension island active area (floating diffusion island) 150a.As shown in figure 1, shallow ridges
Recess isolating structure 150 have several suspension island active area 150a, this bit suspension island active area 150a arrange along a straight line, hang
Without connection between the shape active area 150a of chinampa.The periphery of suspension island active area 150a is wrapped by fleet plough groove isolation structure 150
Cover, without being injected into electric current or applied voltage.
Source electrode 170S is arranged in the first trap 141, and drain electrode 170D is arranged in the second trap 142.Source electrode 170S and drain electrode
170D is, for example, N-type heavily doped region or p-type heavily doped region.In the present embodiment, source electrode 170S and drain electrode 170D are N-type heavy doping
Area.Grid 180G is arranged on the first trap 141 and the second trap 142 and the first trap 141 with part and the second trap 142 are overlapped.
The material of grid 180G is, for example, polysilicon.Source electrode 170S, drain electrode 170D and grid 180G then form the gold of Planar Quadratic diffusion
Category MOSFET (laterally diffused metal oxide semiconductor, LDMOS).
For the design of suspension island active area 150a, the suspension island active area 150a of the present embodiment is arranged at shallow ridges
In recess isolating structure 150 rather than it is arranged at the lower section of fleet plough groove isolation structure 150.Therefore drain electrode 170D's to source electrode 170S is logical
Road will not be elongated, and conducting resistance (turn-on-resistance, Ron) can be maintained at into low water-mark.
Additionally, suspension island active area 150a is located between drain electrode 170D and source electrode 170S so that breakdown voltage
(breakdown voltage) can increase, and conducting resistance (Ron) can be effectively reduced.
As shown in figure 1, for the relation of fleet plough groove isolation structure 150 and suspension island active area 150a, shallow trench every
It is about three times of width W2 of suspension island active area 150a from the width W1 of structure 150.And suspend island active area 150a
It is positioned essentially at the centre of fleet plough groove isolation structure 150.That is, width W3, width W2 and width W4 are substantially about
1：1：1.
Additionally, as shown in figure 1, suspension island active area 150a quantity can be more than or equal to 2, and the several islands of formation are tied
Structure.In one embodiment, the quantity of suspension island active area 150a can also be 1, and form strip structure.When suspension island
When shape active area 150a adopts several island structures, the structural strength of fleet plough groove isolation structure 150 can be maintained.When suspension island
When active area 150a adopts single strip structure, suspension island active area 150a can be made to play maximum effect.
As shown in figure 1, in the present embodiment, suspension island active area 150a adopts several island structures, and neighbouring
The space D 1 of suspension island active area 150a more than or equal to 0.3 micron (micrometer, μm), with effectively maintain shallow trench every
From the structural strength of structure 150, but in different processing technology from generation to generation (process generation) or coordinate different
Design rule (design rule), space D 1 can change and be not limited to 0.3 micron.
Furthermore, as shown in Fig. 2 for depth L1 of suspension island active area 150a, suspension island active area 150a's
Depth L1 is deeper, then can give play to bigger effect.However, depth L1 of suspension island active area 150a must still be less than shallow trench
The thickness L2 of isolation structure 150, to avoid affecting the passage of drain electrode 170D to source electrode 170S.
As shown in Fig. 2 for the relation of grid 180G and suspension island active area 150a, grid 180G and suspension island
Active area 150a can be without any overlap, it is also possible to partly overlap.When grid 180G and suspension island active area 150a parts
During overlap, breakdown voltage (breakdown voltage) and conducting resistance (Ron) will be further affected.
Fig. 2 is refer to, for the conduction type and concentration of suspension island active area 150a, transistor unit 100 is also wrapped
Include a deep trap 130 and a buried horizon (buried layer) 120.Deep trap 130 and buried horizon 120 are, for example, N-type or p-type.At this
In embodiment, deep trap 130 and buried horizon 120 are all N-type.Deep trap 130 is arranged in substrate 110.Second trap 142 and the first trap
141 are arranged in deep trap 130.The conduction type of suspension island active area 150a can or phase identical with the conduction type of drain electrode 170D
Instead, the conduction type of suspension island active area 150a is preferably identical with the conduction type of drain electrode 170D.Suspension island active area
The concentration of 150a has same order with the concentration of deep trap 130.
Fig. 3 A～Fig. 3 E are refer to, it illustrates the flow chart of the manufacture method of the transistor unit 100 of the present embodiment.It is first
First, as shown in Figure 3A, there is provided substrate 110.Then, formation buried horizon 120 and deep trap 130 are among substrate 110.Then, formed
First trap 141 is in deep trap 130.Then, the second trap 142 of formation is in deep trap 130.In another embodiment, substrate is being provided
Buried horizon 120 can be formed after 110 in the top of substrate 110, epitaxial layer is then re-formed follow-up to accommodate in the top of buried horizon 120
By the deep trap 130, the first trap 141 and the second trap 142 that are formed.
Then, as shown in Figure 3 B, formed fleet plough groove isolation structure 150 in the second trap 142, while define shallow trench every
Gap 150b between structure 150.
Then, as shown in Figure 3 C, the region for being intended to be ion implanted is defined using mask (not shown) to form suspension
Island active area 150a is in the 150b of gap.In this step, processing technology time and energy intensity are suitably controlled so that outstanding
Thickness L2 of depth L1 of chinampa shape active area 150a less than fleet plough groove isolation structure 150.
Then, as shown in Figure 3 D, using mask (not shown) region for being intended to be ion implanted is defined to form source electrode
170S and heavily doped region 170 in the first trap 141, and formed drain electrode 170D in the second trap 142.
Then, as shown in FIGURE 3 E, formation grid 180G is on the first trap 141 and the second trap 142.So far crystal is completed
Pipe device 100.
In the present embodiment, the manufacturing process of transistor unit 100 need not increase extra cost, only need to be by the island that suspends
Active area 150a is arranged within fleet plough groove isolation structure 150, you can increase breakdown voltage (breakdown voltage),
And conducting resistance (Ron) is effectively reduced.
In sum, although disclose the present invention with reference to above example, however it is not limited to the present invention.This
Skilled person in bright art, without departing from the spirit and scope of the present invention, can make various changes with profit
Decorations.Therefore, protection scope of the present invention should be by being defined that the claim enclosed is defined.
Claims (16)
1. a kind of transistor unit, including：
Substrate；
First trap (well), among being arranged at the substrate；
Second trap, among being arranged at the substrate；
Fleet plough groove isolation structure (shallow trench isolation, STI), is arranged in second trap, the shallow trench every
There is an at least suspension island active area (floating diffusion island) from structure, the suspension island active area
Periphery is coated by the fleet plough groove isolation structure；
Source electrode, is arranged in first trap；
Drain electrode, is arranged in second trap, the conduction type of the suspension island active area it is contrary with the conduction type of the drain electrode or
It is identical；And
Grid, is arranged on first trap and second trap and overlaps with first trap and second trap of part.
2. transistor unit as claimed in claim 1, wherein grid is Chong Die with the suspension island active region.
3. transistor unit as claimed in claim 1, the wherein depth of the suspension island active area are less than shallow trench isolation
The thickness of structure.
4. transistor unit as claimed in claim 1, the wherein width of the fleet plough groove isolation structure are that the suspension island is active
Three times of the width in area.
5. transistor unit as claimed in claim 1, wherein the suspension island active area are positioned essentially at shallow trench isolation
The centre of structure.
6. transistor unit as claimed in claim 1, the quantity of a wherein at least suspension island active area is more than or equal to
Two, those suspension island active areas mutually completely cut off.
7. transistor unit as claimed in claim 6, wherein the spacing of those neighbouring suspension island active areas is more than or waits
In 0.3 micron (micrometer, μm).
8. transistor unit as claimed in claim 1, also includes：
Deep trap, is arranged in the substrate, and second trap and first trap are arranged in the deep trap, the suspension island active area it is dense
Degree has same order with the concentration of the deep trap.
9. a kind of manufacture method of transistor unit, including：
One substrate is provided；
One first trap (well) is formed among the substrate；
One second trap is formed among the substrate；
A fleet plough groove isolation structure (shallow trench isolation, STI) is formed in second trap, the shallow trench every
There is an at least suspension island active area (floating diffusion island) from structure, the suspension island active area
Periphery is coated by the fleet plough groove isolation structure；
A source electrode is formed in first trap；
Form one to drain in second trap, the suspension island active area is contrary with the conduction type of the drain electrode or identical；And
A grid is formed on first trap and second trap, the grid is overlapping with first trap and second trap of part.
10. the manufacture method of transistor unit as claimed in claim 9, wherein in the grid is formed, the grid hangs with this
Chinampa shape active region is overlapped.
The manufacture method of 11. transistor units as claimed in claim 9, wherein the step of the fleet plough groove isolation structure is formed
In, the depth of the suspension island active area is less than the thickness of the fleet plough groove isolation structure.
The manufacture method of 12. transistor units as claimed in claim 9, wherein in the step for forming the fleet plough groove isolation structure
Suddenly, the width of the fleet plough groove isolation structure is three times of the width of the suspension island active area.
The manufacture method of 13. transistor units as claimed in claim 9, wherein in the step for forming the fleet plough groove isolation structure
Suddenly, the suspension island active area is positioned essentially at the centre of the fleet plough groove isolation structure.
The manufacture method of 14. transistor units as claimed in claim 9, wherein the step of the fleet plough groove isolation structure is formed
In, the quantity of an at least suspension island active area is more than or equal to two.
The manufacture method of 15. transistor units as claimed in claim 14, wherein in the step for forming the fleet plough groove isolation structure
In rapid, the spacing of neighbouring those suspension island active areas is more than or equal to 0.3 micron (micrometer, μm).
The manufacture method of 16. transistor units as claimed in claim 9, wherein the step of second trap is formed and forming this
Before the step of first trap, the manufacture method also includes：
A deep trap is formed in the substrate, second trap and first trap are arranged in the deep trap, the suspension island active area
Concentration has same order with the concentration of the deep trap.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210212660.7A CN103515414B (en) | 2012-06-21 | 2012-06-21 | Transistor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210212660.7A CN103515414B (en) | 2012-06-21 | 2012-06-21 | Transistor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103515414A CN103515414A (en) | 2014-01-15 |
| CN103515414B true CN103515414B (en) | 2017-04-12 |
Family
ID=49897845
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210212660.7A Active CN103515414B (en) | 2012-06-21 | 2012-06-21 | Transistor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103515414B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105448990B (en) * | 2014-08-26 | 2019-07-02 | 中芯国际集成电路制造(上海)有限公司 | Ldmos transistor and forming method thereof |
| CN104835837B (en) * | 2015-06-05 | 2017-07-28 | 杭州士兰微电子股份有限公司 | High-voltage semi-conductor device and its manufacture method |
| CN108630745A (en) * | 2018-04-13 | 2018-10-09 | 上海华力集成电路制造有限公司 | Semiconductor devices |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1414639A (en) * | 2001-10-22 | 2003-04-30 | 联华电子股份有限公司 | Silicon rectifier set in silicon covered insulator and its application circuit |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6573566B2 (en) * | 2001-07-09 | 2003-06-03 | United Microelectronics Corp. | Low-voltage-triggered SOI-SCR device and associated ESD protection circuit |
| US7825473B2 (en) * | 2005-07-21 | 2010-11-02 | Industrial Technology Research Institute | Initial-on SCR device for on-chip ESD protection |
| US7372104B2 (en) * | 2005-12-12 | 2008-05-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | High voltage CMOS devices |
-
2012
- 2012-06-21 CN CN201210212660.7A patent/CN103515414B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1414639A (en) * | 2001-10-22 | 2003-04-30 | 联华电子股份有限公司 | Silicon rectifier set in silicon covered insulator and its application circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103515414A (en) | 2014-01-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9412809B2 (en) | Semiconductor device and manufacturing method thereof | |
| CN102034876B (en) | Semiconductor device having SOI substrate and method for manufacturing the same | |
| CN102832234B (en) | Groove type semiconductor power device, method for producing same and terminal protection structure | |
| CN103579343A (en) | Super-junction trench mosfet and manufacturing method thereof | |
| US8836067B2 (en) | Transistor device and manufacturing method thereof | |
| CN103515414B (en) | Transistor device and manufacturing method thereof | |
| CN110459539A (en) | The shield grid groove MOSFET and manufacturing method of integrated ESD protection | |
| CN103811485B (en) | Esd protection circuit | |
| CN105914231B (en) | Charge storage type IGBT and its manufacturing method | |
| US9466687B2 (en) | Methods for producing bipolar transistors with improved stability | |
| CN103872123B (en) | N-channel radio frequency LDMOS device and manufacture method | |
| CN102945843B (en) | Detection structure and resistance measurement method | |
| CN103972096A (en) | Method for manufacturing semiconductor power device | |
| TWI525813B (en) | Transistor device and manufacturing method thereof | |
| CN103151380A (en) | Groove-type semiconductor power device, manufacture method thereof and terminal protective structure | |
| CN106298869A (en) | A kind of power semiconductor and manufacture method thereof | |
| CN104716184B (en) | High voltage lateral with improved drift layer contact extends drain MOS transistor | |
| CN103887240B (en) | A kind of preparation method of inverse conductivity type IGBT device | |
| CN103390654B (en) | Multi-groove terminal Schottky device and preparation method thereof | |
| CN202948930U (en) | Semiconductor device with a plurality of transistors | |
| CN107346738B (en) | Manufacturing method of super junction power device | |
| CN103390635B (en) | One kind has passive metal PN junction semiconductor device and preparation method thereof | |
| CN104681609B (en) | A kind of n-type LDMOS device and its manufacture method | |
| CN103515387B (en) | Semiconductor device with adjustable potential distribution and manufacturing method of semiconductor device | |
| CN105355594B (en) | Integrated circuit structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |