CN103811485B - Esd protection circuit - Google Patents
Esd protection circuit Download PDFInfo
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- CN103811485B CN103811485B CN201310306060.1A CN201310306060A CN103811485B CN 103811485 B CN103811485 B CN 103811485B CN 201310306060 A CN201310306060 A CN 201310306060A CN 103811485 B CN103811485 B CN 103811485B
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- 238000002955 isolation Methods 0.000 claims abstract description 53
- 239000000758 substrate Substances 0.000 claims abstract description 38
- 238000009792 diffusion process Methods 0.000 claims abstract description 35
- 239000004065 semiconductor Substances 0.000 claims description 26
- 229910045601 alloy Inorganic materials 0.000 claims description 20
- 239000000956 alloy Substances 0.000 claims description 20
- 239000000126 substance Substances 0.000 claims 1
- 229910021332 silicide Inorganic materials 0.000 description 19
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 16
- 239000002019 doping agent Substances 0.000 description 7
- 230000035755 proliferation Effects 0.000 description 5
- 239000004020 conductor Substances 0.000 description 4
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- 230000005611 electricity Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
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- 229910052814 silicon oxide Inorganic materials 0.000 description 2
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- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910019001 CoSi Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
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- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
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- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
- H01L27/027—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements specially adapted to provide an electrical current path other than the field effect induced current path
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
- H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/456—Ohmic electrodes on silicon
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
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- Microelectronics & Electronic Packaging (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses a kind of esd protection circuit, and a kind of device, including substrate; definition has device region it is characterised in that this device region has the esd protection circuit at least with first and second transistor; it is characterized in that, respectively this transistor includes grid, has the first side and the second side；First diffusion zone, in this device region of this first side of this grid neighbouring；Second diffusion zone, in this device region of this second side being located remotely from this grid；And drift isolation domain, it is arranged between this grid and this second diffusion zone；First device trap, surrounds this device region, second device trap, is arranged in this first device trap；Drift trap, surround this second diffusion zone it is characterized in that, the edge of this drift trap does not extend to below this grid and away from channel region；And drain well, it is arranged on below this second diffusion zone and in this drift trap.
Description
Technical field
The present invention relates to semiconductor device.
Background technology
Integrated circuit（integrated circuit；IC）Can be by static discharge（electrostatic discharge；
ESD）Destroy.For example, ESD can destroy the gate oxide of transistor.For protecting transistor damage, protect electricity using ESD
Road discharges ESD electric current with the substrate through integrated circuit.When static discharge is detected on the weld pad of integrated circuit, start
ESD circuit with through substrate release current, thus protecting gate oxide.
Using various types of esd protection circuits.A type of esd protection circuit is lateral diffused metal oxide
Quasiconductor（lateral diffused metal oxide semiconductor；LDMOS）Transistor.ESD with this LDMOS
Performance-relevant thermal runaway electric current（thermal runaway current）（Such as It2）The direct phase with the overall width of this LDMOS
Close.For example, the overall width of ldmos transistor is bigger, It2Higher.But, conventional LDMOS transistor is in width and It2Between pass
System is in heterogeneity.For example, the overall width increasing ldmos transistor is not result in It2Expected property increase.In certain situation
Under, the overall width increasing this ldmos transistor will lead to It2Reduce.Such heterogeneity negatively affects ESD design rule,
IC designer is made to be difficult to provide necessary ESD protection.
This exposure is intended to provide improved uniformity in ldmos transistor.
Content of the invention
The specific embodiment of the invention is usually directed to semiconductor device.A kind of device is provided in one embodiment, including：
Substrate, definition has the device region with esd protection circuit it is characterised in that this esd protection circuit at least includes first and the
Two-transistor, respectively this transistor include：Grid, has the first side and the second side；First diffusion zone, positioned at this grid neighbouring
In this device region of this first side；Second diffusion zone, in this device region of this second side being located remotely from this grid, its
It is characterised by, this first and second diffusion zone includes the alloy of the first polarity type, and located at this grid and this second expansion
Dissipate interregional drift isolation domain.This device includes first device trap, surrounds this device region；Second device trap, is arranged at
In this first device trap；Drift trap, surrounds this second diffusion zone, and the edge of this drift trap do not extend to below this grid and
Away from channel region；And drain well, there is the alloy of this first polarity type, and be arranged at below this second diffusion zone
And in this first device trap.
In another specific embodiment, disclose a kind of device, including：Substrate, definition have device region it is characterised in that
This device region includes the esd protection circuit at least with first and second transistor.Those transistors each include：Grid, tool
There are the first side and the second side；First diffusion zone, in this device region of this first side of this grid neighbouring；Second diffusion
Region, in this device region of this second side being located remotely from this grid；And drift isolation domain, it is arranged at this grid and be somebody's turn to do
Between the second diffusion zone.This device includes first device trap, surrounds this device region；Second device trap, is arranged at this first dress
Put in trap；Drift trap, surrounds this second diffusion zone, and the edge of this drift trap does not extend to below this grid and away from raceway groove
Region；And drain well, it is arranged at below this second diffusion zone and in this drift trap.
By referring to description below and accompanying drawing, the above-mentioned and further advantage of specific embodiment described herein and feature will
Become more fully apparent.Furthermore, it is to be understood that the feature of various specific embodiment described herein not having to be mutually exclusive, but
May be present in various combination and permutation.
Brief description
In accompanying drawing, similar reference typically represents the same components in different views.In addition, accompanying drawing not necessarily press than
Example is drawn, but stresses the principle of the present invention.With reference to the accompanying drawings to describe the present invention various concrete in the following description
Embodiment, wherein：
Fig. 1 is the sectional view of a specific embodiment of display device；And
Fig. 2 is the transmission line pulse showing various devices（TLP（transmission line pulse）Measurement result.
Specific embodiment
The specific embodiment of the invention is usually directed to semiconductor device.Those devices are provided with ESD circuit.For example, those ESD electricity
Road can be used in high voltage applications or device.For example, ESD circuit can be started in esd event, to discharge ESD electric current.Those dresses
Putting is can be for example any kind of semiconductor device, such as integrated circuit（IC）.For example, such device may be included in independent
Device or integrated circuit, such as microcontroller or SOC(system on a chip)（system on chip；SOC）In.For example, those devices or collection
Circuit is become to may be included in such as speaker, computer, mobile phone and personal digital assistant（personal digitial
assistant；PDA）It is used in combination Deng in electronic product or with those electronic products.
The sectional view of one specific embodiment of Fig. 1 display device 100.As illustrated, setting substrate 105.This substrate is for example
For semiconductor substrate, such as silicon substrate.In one embodiment, this substrate can be p-type doped substrate.For example, this p-type doping
Substrate is lightly doped substrate for p-type.It is also possible to use other types of semiconductor substrate, including mixing doped with other types or concentration
Debris, or plain semiconductor substrate.For example, this substrate can be SiGe, germanium, GaAs, or crystal on insulator
（crystal-on-insulator；COI）, such as silicon-on-insulator（silicon-on-insulator；SOI）.This substrate can
For doped substrate.
This device may include the doped region with different levels of doping or trap.For example, this device may include heavily doped region
Domain, medium-doped region and lightly doped region.Those doped regions can be by x-, x and x+Represent, wherein x represents the pole of doping
Property, such as p represents p-type, or n represents N-shaped, and：
x-=be lightly doped；
X=medium-doped；And
x+=heavy doping.
Lightly doped region can have and is less than about 5E13/cm3Doping content.For example, lightly doped region can have about
1E11/cm3To 5E13/cm3Doping content.Medium-doped region can have about 5E13/cm3To 5E15/cm3Doping dense
Degree.Heavily doped region can have approximately more than 5E15/cm3Doping content.For example, heavily doped region can have about 5E15/cm3
To 9E15/cm3Doping content.It is also possible to use the different types of doped region with other concentration.P-type dopant may include
Boron（B）, aluminum（Al）, indium（In）Or a combination thereof, and n-type dopant may include phosphorus（P）, arsenic（As）, antimony（Sb）Or a combination thereof.
As illustrated, this device includes the device region 110 being defined on this substrate.Device area of isolation 190 can be set
With by this device region and the other device zone isolation on this substrate or separate.In one embodiment, this device isolation
Region is around this device region.For example, this area of isolation is isolated for shallow trench（shallow trench isolation；STI）
Region.It is also possible to use other types of area of isolation.For example, this area of isolation can be deep trench isolation（deep trench
isolation；DTI）Region.For example, for shallow plough groove isolation area, this area of isolation extends to about 4000 angstroms of depth.Also
The area of isolation extending to other depth can be set, such as deep trench isolation region, extend to 0.5 to 10 micron of depth
Degree.In one embodiment, the width of this area of isolation is about 0.3 micron.Also can arrange and there is different depth and width
Area of isolation.For example, the size of area of isolation may depend on insulation request.
This device region includes esd protection circuit 115.This esd protection circuit includes multiple horizontal proliferation of coupled in parallel
（lateral diffused；LD）Transistor.For example, this esd protection circuit includes n horizontal proliferation transistor.As illustrated,
This device region includes first and second（Such as n=2）Horizontal proliferation transistor 115a, 115b.The horizontal stroke of other numbers also can be set
To diffusion transistor.
First dopant well 160 is in this substrate in this device region.As illustrated, this first dopant well to surround this complete
Part device region.For example, this first dopant well serves as isolation well.This first dopant well includes the first polarity type alloy.?
In one specific embodiment, this first trap to be lightly doped with the first polarity type alloy.Also can arrange and there are other doping contents
The first trap.
Respectively this transistor includes grid 120, and it is on the surface of this substrate in this device region.Grid can be referred to as grid
Refer to.This grid includes the gate electrode 126 located at gate dielectric 124 top.In one embodiment, this gate electrode is
Polysilicon gate electrodes.It is also possible to use the gate electrode material of other appropriate types.This gate dielectric includes silicon oxide.Also may be used
Grid dielectric material using other appropriate types.In one embodiment, this grid is similarly used for the grid of high voltage device
Pole.For example, the thickness of this gate electrode and this gate dielectric can be similar to gate electrode and the gate dielectric of this high voltage device
The thickness of layer.It is also possible to use the grid of other configurations.
This grid can be grid conductor, and it constitutes the grid of multiple transistors.For example, this grid conductor can be across being isolated
Multiple device regions of region disconnecting.The plurality of transistor has the common grid being made up of this grid conductor.It is also possible to use
The grid conductor of other configurations.
This grid is located at first and second source/drain（S/D）Between region 130,140.Those source/drain region are located at this
The first polarity type doped region in substrate.For example, those source/drain region are the first polarity type heavily doped region.Example
As those source/drain region can have about 0.1 to 0.4 micron of depth.It is also possible to use other suitable depth.Those source/drain
Polar region domain can be similar to the source/drain region of other transistors of this device.In one embodiment, this first source/drain region
Domain 130 is the source region of this transistor, and this second source/drain region 140 is the drain region of this transistor.
This first source/drain region is positioned adjacent to the first side of this grid.In one embodiment, this grid with should
First source/drain region overlaps（overlap）.For example, this first side of this grid and this first source/drain region overlap.Weight
Repeatedly amount is to should be sufficient so that this first source/drain region and the raceway groove of this transistor below this grid connect.For example, overlapping amount
It is about 0.1 to 0.5 micron.Can also other quantity overlap with this first source/drain region.In one embodiment, this grid
Pole is lightly doped with this first source/drain region（lightly doped；LD）Region overlaps.This first source/drain region also may be used
There are other configurations.This second source/drain region 140 can be from the second side lateral displacement of this grid apart from DG.In certain situation
Under, this lateral displacement DGDrift distance can be corresponded to.For example, DGMay include any appropriately distance, it depends on each wafer foundry
（foundry）Be typically designed rule.
In one embodiment, drift isolation domain 192 is set between this grid and this second source/drain region.Example
As this drift isolation domain isolates for shallow trench.It is also possible to use other types of drift isolation domain.As illustrated, this grid
Overlap with this drift isolation domain.This drift isolation domain can be used for for Introgression distance increasing to greater than DG.For example, can be by
This drift distance increases to equal with the section in this drift isolation domain.Between this source region and drift isolation domain apart from L
Can to should transistor raceway groove.This Introgression distance begins at this second source/drain region, and bypasses this drift isolation
Domain and reach this raceway groove below this grid.
In one embodiment, this second side of this grid is provided with silicide resistor 128.This silicide block piece can
Stop the formation of silicide, to reduce the silicide contacts on this drain region（Not shown）With this grid short circuit and the wind of short circuit
Danger.This silicide block piece can be dielectric liner.For example, this dielectric liner can be silicon oxide side liner.In a specific embodiment
In, this silicide block piece can be on this second side of this grid, and with this grid with apart from DEOverlap.For example, this is apart from DE
Approximate 0.06 micron.For example, DEMay also include any appropriately distance, be typically designed rule depending on each wafer foundry
Then.The part of this silicide block piece is arranged to this grid with apart from DEOverlapping is beneficial, because it effectively stops
Form silicide in lower zone domain, and effectively stop electric current from flowing in the horizontal direction, thus leading to preferable ESD performance.Should
Silicide block piece can be along the top setting in this drift isolation domain.As illustrated, this silicide block piece can partly extend
Above this drain region.
As illustrated, this first and second horizontal proliferation transistor can be configured and includes the second common source/drain
Region or drain region.Those horizontal proliferation transistors also can have other configurations.
Second trap 165 can be set in this substrate.This second trap can be in this device region.For example, can by this second
Trap is in this first trap.And this second trap serves as the body trap of those transistors（body well）.This second device trap includes using
The second polarity type alloy in the first polarity type device.For example, this second device trap includes the p-type for N-shaped device
Alloy or the n-type dopant for p-type device.This second device trap can the first polarity type alloy being lightly doped（x-）
Or medium-doped（x）.This second device trap also can have other doping contents.
This body trap at least surrounds those the first source/drain region and the part of those grids.As illustrated, this body trap surrounds
This first and second source/drain region.This second trap also can have other configurations.The depth of this second trap can be shallower than this first
Trap.This second trap also can have other depth.
In one embodiment, this substrate and this first and second trap are respectively equipped with substrate contact 107, first and the
Two trap contacts 162,167, to bias this substrate and trap.The contact of those substrates and trap contact as heavily doped region, be similar to those sources/
Drain region.For example, the depth of the contact of this substrate or trap contact can be shallower than the depth of this device area of isolation, and those substrates connect
Touch trap contact to connect with respective substrate and trap.The doping content of the contact of those substrates and trap contact is about 5E15/cm3Extremely
9E15/cm3.It is also possible to use other suitable concentration ranges.The contact of those substrates and trap contact have and respective substrate and trap
Identical polarity type.For example, those first traps contact 162 is the first polarity type doped region, and the contact of those second traps
167 is the second polarity type doped region.
In one embodiment, area of isolation 194 can be set to separate those contact areas.Those area of isolation can be
Shallow plough groove isolation area.For example, those area of isolation can be similar to those device area of isolation.It is also possible to use other types or configuration
Area of isolation.
Metal-silicides Contact can be formed on this gate electrode and each contact area（Not shown）.For example, can be at those
Above source/drain region, trap contact and gate electrode, Metal-silicides Contact is set.For example, those silicide contacts can be
Ni-based contact.It is also possible to use other types of Metal-silicides Contact.For example, those silicide contacts can be cobalt silicide（CoSi）
Contact.The thickness of those silicide contacts is about 100 to 500 angstroms.It is also possible to use the silicide contacts with other thickness.Should
A little silicide contacts can be used for reducing contact resistance and promoting the contact with the metal interconnection of backend process.
In one embodiment, the 3rd trap 170 is set.Can be by the 3rd trap in this substrate in this second trap.
For example, the depth of the 3rd trap can be shallower than the depth of this second trap.3rd trap may act as the trap that drifts about.In a specific embodiment
In, the 3rd trap surrounds this second source/drain region, and is configured or shrinks so that the edge of this drift trap does not extend to this grid
Below pole and away from this channel region.
In one embodiment, the depth of the 3rd trap or bottom can be located at below those area of isolation.3rd trap
Depth be about 0.1 to 5 micron.It also can have other depth.For example, its depth may depend on the design electricity of this device
Pressure.For example, this drift trap can extend to the dress below second grid from the bottom of the device area of isolation 192 below first grid
Put the bottom of area of isolation 192.For example, the width of the 3rd trap can extend to the second side from first edge 170a of the 3rd trap
Edge 170b.For example, the width of the 3rd trap is about 8 microns.3rd trap may also include other suitable width dimensions.
This drift trap includes the first polarity type alloy.In one embodiment, the doping content of this drift trap is low
Doping content in this drain electrode pole.In one embodiment, this drift trap can the first polarity type alloy being lightly doped
（x-）Or medium-doped（x）.For example, the doping content of this drift trap is about 1E12/cm3To 1E14/cm3.It also can have other
Suitable doping content.For example, its doping content may depend on the maximum of this device or the requirement destroying voltage.
In one embodiment, this second trap, this first source/drain region and grid can be with the first of this ESD device
Terminal 134 couples jointly.This second source/drain region is coupled with the Second terminal 144 of this ESD device.For example, this first terminal
For source terminal, and this Second terminal is drain terminal.In one embodiment, this second trap contact 167 also with this first
Terminal or source terminal couple.For example, this source terminal can be with ground terminal, and this drain terminal and device running voltage
(Vdd) or I/O（Input/output）Weld pad couples.The terminal that ESD device also can have other configurations connects.
In one embodiment, the 4th trap 175 can be set.For example, the 4th trap serve as the second source/drain region trap or
Drain well.This drain well is in this substrate.In one embodiment, this drain well is in the 3rd trap and adjacent to this leakage
Polar region domain.For example, this drain well overlaps to this drain region.In one embodiment, the first edge of this drain well
175a be aligned in or be contacted with this first transistor of this grid away from this first transistor this drift isolation domain side
Edge 192a1.Similarly, the second side 175b of this drain well is aligned in or is contacted with being somebody's turn to do of this grid away from this transistor seconds
The edge 192a in this drift isolation domain of transistor seconds2.The depth of the 4th trap can be shallower than the depth of the 3rd trap.One
In specific embodiment, the width of this second diffusion zone or drain region 140 can be identical with the width of the 4th trap 175.Another
In one specific embodiment, the width of this second diffusion zone or drain region 140 can be narrower than the width of the 4th trap 175.Setting
It is beneficial that width is narrower than the 4th trap 175 or the second diffusion zone away from this drift isolation domain 192 or drain region 140
, because it increases electric current in the horizontal direction to the resistance of this channel region flowing.This makes this ESD device have leading evenly
Logical, thus leading to preferable ESD performance.This drain well includes the first polarity type alloy.In one embodiment, this leakage
The doping content of pole trap is between this second source/drain region and drift trap.In one embodiment, this drain well can
One polarity type alloy carrys out medium-doped（x）.It also can have other suitable doping contents.
As it was previously stated, this drift trap 170 surrounds this second source/drain region 140 and is configured or shrinks so that this drift
Edge 170a or 170b of trap does not extend to below this grid, and away from this channel region.In one embodiment, the 4th
Trap or drain well 175 can be narrower than the 3rd trap or drift trap 170.For example, this first edge 170a of this drift trap can be located at this
The central lower in this drift isolation domain 192 of the first transistor and substantially with this center alignment, and this second edge 170b can
Central lower positioned at another drift isolation domain of this transistor seconds and substantially with this center alignment.For example, at least neighbouring
The edge of the 3rd trap of this grid and the 4th trap is spaced a distance.As shown in figure 1, first edge 170a of the 3rd trap with
The first edge 175a standoff distance Do of the 4th trap.For example, second edge 170b of the 3rd trap and the second of the 4th trap
Edge 175b is separated by identical apart from Do.In another specific embodiment, first edge 170a of this drift trap aligns the 4th
First edge 175a of trap, simultaneously second edge 170b of this drift trap align second edge 175b of the 4th trap.For example, phase
Edge 175a or 175b to the 4th trap or drain well, apart from DoIt is about 1.0 microns or less.For example, the 4th trap relatively
175 edge 175a or 175b can adjust or change this apart from Do.DoAlso can have other appropriately distances, as long as the 3rd trap
Edge 170a or 170b be not too close to this channel region.This reduces or is avoided the negative effect of ESD performance to this device
Risk.For example, Do can have any appropriately distance, as long as the edge of the 3rd trap does not extend to the upper of this drift isolation domain
This channel region of Fang Bingxiang extends.
It was found that setting includes this drift trap of above-mentioned configuration and this drain well may result in some advantages.For example, such
Configuration increases the base stage of the parasitic bipolar transistor of this ESD circuit, and it increases the holding voltage of this ESD device（Vh）.Pass through
This drift trap contracted as described above, also inhibits the extension of base region, thus it is improved uniform to lead to this ESD device to have
Conducting.And, it has been found that described such configuration strengthen the plurality of grid refer between uniform conducting.So it was found that reference
The ESD performance of the such configuration described in Fig. 1 is directly to be directly proportional to the number that grid refer to.
Further it has been found that, below this drain region, setting drain well can be formed compared with low resistance path in vertical direction.As
This, can be by electric current guiding vertically non-horizontal directions flowing.Therefore, mitigate or suppression base region in commitment
Expansion.This leads to this ESD device to have improved conducting evenly.
Fig. 2 shows form and the TLP measurement result of the specific embodiment with this esd protection circuit that multiple grid refer to.Please
With reference to Fig. 2, Lg represents channel length, DoRepresent the standoff distance between the edge of the 4th trap and the edge of the 3rd trap, beam overall
Degree (total width) represents total grid width, and FW represents grid finger widths, and DCGS represents the distance draining to gate contact,
SCGS represents source contact to the distance of grid, and D_NW represents the width of this drain well.For example, those parameters are represented with micron.
As it was previously stated, thermal runaway electric current（It2）Related to the ESD performance of this LDMOS.As shown in Fig. 2 the LDMOS based on above-mentioned configuration
The It of device2Increase with overall width and increase.So, It2Substantially it is directly proportional to its overall width.This means that this ESD device has
Conducting evenly.So, this configuration is effectively increased this ESD It as above2Function so that its be proportional to this ESD dress
Grid index mesh in putting.The It associating with grid index mesh2Increase mean that this device can before disabling will be larger amount of
Current distributing.Therefore, superior ESD performance is presented based on this ESD device of above-mentioned configuration.
The spirit or essential attributes without departing from the present invention for the present invention can be implemented in other specific forms.Therefore, above-mentioned tool
Body embodiment is to be considered as illustrative in every respect rather than be considered as limiting the present invention.Therefore, the scope of the present invention is by appended power
Profit requires rather than described above is representing, and is intended to the had altered inclusion in the equivalent of this claim and scope
Including.
Claims (18)
1. a kind of semiconductor device, including：
Substrate, definition has device region, and this device region includes the esd protection circuit at least with first and second transistor,
It is characterized in that, respectively those transistors include：
Grid, has the first side and the second side；
First diffusion zone, in this device region of this first side of this grid neighbouring；
Second diffusion zone, in this device region of this second side being located remotely from this grid, and by this first transistor and is somebody's turn to do
Transistor seconds is common it is characterised in that this first and second diffusion zone includes the alloy of the first polarity type；And
Drift isolation domain, is arranged between this grid and this second diffusion zone；
First device trap, surrounds this device region；
Second device trap, is arranged in this first device trap；
Drift trap, surrounds this second diffusion zone it is characterised in that the edge of this drift trap does not extend to below this grid simultaneously far
From channel region；And
Drain well, has the alloy of this first polarity type, and is arranged at below this second diffusion zone and this first device
In trap.
2. semiconductor device as claimed in claim 1 is it is characterised in that this first device trap includes this first polarity type
Alloy, and this second device trap includes the alloy of the second polarity type.
3. semiconductor device as claimed in claim 2 is it is characterised in that this first polarity type includes N-shaped, and this second pole
Property type includes p-type.
4. semiconductor device as claimed in claim 1 is it is characterised in that this second device trap at least surrounds of this grid
Divide and this first diffusion zone.
5. semiconductor device as claimed in claim 4 it is characterised in that this second device trap surround this grid, this drift every
From region and this second diffusion zone.
6. semiconductor device as claimed in claim 1 it is characterised in that this first device trap and this drift trap include this first
The alloy of polarity type, and this second device trap includes the alloy of the second polarity type.
7. semiconductor device as claimed in claim 6 is it is characterised in that this first polarity type includes N-shaped, and this second pole
Property type includes p-type.
8. semiconductor device as claimed in claim 1 is it is characterised in that this drain well is narrower than this drift trap.
9. semiconductor device as claimed in claim 1 is it is characterised in that the first edge of this drift trap is in this first crystalline substance
The central lower in this drift isolation domain of body pipe, and the second edge of this drift trap is in this drift of this transistor seconds
The central lower of area of isolation.
10. semiconductor device as claimed in claim 9 is it is characterised in that this drain well is arranged in this drift trap and neighbouring
This second diffusion zone.
11. semiconductor devices as claimed in claim 10 are it is characterised in that the first edge of this drain well and this drift trap
Standoff distance between this second edge of the second edge of the standoff distance between this first edge and this drain well and this drift trap
Identical.
A kind of 12. semiconductor devices, including：
Substrate, definition has device region, and this device region includes the esd protection circuit at least with first and second transistor,
It is characterized in that, respectively those transistors include：
Grid, has the first side and the second side；
First diffusion zone, in this device region of this first side of this grid neighbouring；
Second diffusion zone, in this device region of this second side being located remotely from this grid, and by this first transistor and is somebody's turn to do
Transistor seconds is common；And
Drift isolation domain, is arranged between this grid and this second diffusion zone；
First device trap, surrounds this device region；
Second device trap, is arranged in this first device trap；
Drift trap, surround this second diffusion zone it is characterised in that the edge of this drift trap be do not extend to below this grid and
Away from channel region；And
Drain well, is arranged at below this second diffusion zone and in this drift trap.
13. semiconductor devices as claimed in claim 12 are it is characterised in that this first device trap includes the first polarity type
Alloy, and this second device trap includes the alloy of the second polarity type, and this first and second diffusion zone includes first
The alloy of polarity type.
14. semiconductor devices as claimed in claim 13 it is characterised in that this first polarity type includes N-shaped, and this second
Polarity type includes p-type.
15. semiconductor devices as claimed in claim 12 it is characterised in that the first edge of this drift trap be in this first
The central lower in this drift isolation domain of transistor, and the second edge of this drift trap is in this drift of this transistor seconds
Move the central lower of area of isolation.
16. semiconductor devices as claimed in claim 15 are it is characterised in that this drain well is arranged in this drift trap and neighbouring
This second diffusion zone.
17. semiconductor devices as claimed in claim 16 it is characterised in that the first edge (175a) of this drain well with away from
The justified margin in this drift isolation domain of this first transistor of this grid of this first transistor, and the second of this drain well
Edge (175b) with away from this transistor seconds this grid this transistor seconds this drift isolation domain justified margin.
18. semiconductor devices as claimed in claim 17 are it is characterised in that this first edge of this drain well and this drift trap
This first edge between standoff distance and this second edge of this drain well and this second edge of this drift trap between be separated by
Apart from identical.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13/669,409 US8853783B2 (en) | 2012-01-19 | 2012-11-05 | ESD protection circuit |
| US13/669,409 | 2012-11-05 | ||
| US13/803,091 US8847318B2 (en) | 2012-01-19 | 2013-03-14 | ESD protection circuit |
| US13/803,091 | 2013-03-14 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103811485A CN103811485A (en) | 2014-05-21 |
| CN103811485B true CN103811485B (en) | 2017-03-01 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310306060.1A Active CN103811485B (en) | 2012-11-05 | 2013-07-19 | Esd protection circuit |
Country Status (5)
| Country | Link |
|---|---|
| KR (1) | KR20140058323A (en) |
| CN (1) | CN103811485B (en) |
| DE (1) | DE102013214132B4 (en) |
| SG (1) | SG2013049408A (en) |
| TW (1) | TWI562331B (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9728531B2 (en) | 2013-03-13 | 2017-08-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Electrostatic discharge device |
| CN107564901B (en) * | 2016-06-30 | 2020-03-13 | 中芯国际集成电路制造（天津）有限公司 | LDMOS device with ESD protection function and layout thereof |
| DE102016118921B4 (en) * | 2016-09-12 | 2020-08-06 | Taiwan Semiconductor Manufacturing Co. Ltd. | Improved ESD device |
| CN110289257B (en) * | 2019-06-28 | 2021-09-14 | 湖南师范大学 | Bidirectional enhanced gate-controlled silicon controlled electrostatic protection device and manufacturing method thereof |
| US11302687B2 (en) * | 2019-10-30 | 2022-04-12 | Globalfoundries Singapore Pte. Ltd. | Semiconductor device and method of forming the same |
| US11476244B2 (en) | 2020-08-19 | 2022-10-18 | Globalfoundries Singapore Pte. Ltd. | Laterally-diffused metal-oxide-semiconductor devices for electrostatic discharge protection applications |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102034812A (en) * | 2009-09-25 | 2011-04-27 | 精工电子有限公司 | Semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6730962B2 (en) | 2001-12-07 | 2004-05-04 | Texas Instruments Incorporated | Method of manufacturing and structure of semiconductor device with field oxide structure |
| KR100624911B1 (en) * | 2004-06-29 | 2006-09-19 | 매그나칩 반도체 유한회사 | Device for protecting an electro static discharge |
| US20090072314A1 (en) * | 2007-09-19 | 2009-03-19 | Texas Instruments Incorporated | Depletion Mode Field Effect Transistor for ESD Protection |
| US7667241B1 (en) | 2006-09-26 | 2010-02-23 | Cypress Semiconductor Corporation | Electrostatic discharge protection device |
| US7786507B2 (en) * | 2009-01-06 | 2010-08-31 | Texas Instruments Incorporated | Symmetrical bi-directional semiconductor ESD protection device |
| US8536648B2 (en) | 2011-02-03 | 2013-09-17 | Infineon Technologies Ag | Drain extended field effect transistors and methods of formation thereof |
| US8853783B2 (en) | 2012-01-19 | 2014-10-07 | Globalfoundries Singapore Pte. Ltd. | ESD protection circuit |
-
2013
- 2013-06-26 SG SG2013049408A patent/SG2013049408A/en unknown
- 2013-06-26 TW TW102122659A patent/TWI562331B/en active
- 2013-07-18 KR KR1020130084837A patent/KR20140058323A/en not_active Application Discontinuation
- 2013-07-18 DE DE102013214132.7A patent/DE102013214132B4/en active Active
- 2013-07-19 CN CN201310306060.1A patent/CN103811485B/en active Active
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102034812A (en) * | 2009-09-25 | 2011-04-27 | 精工电子有限公司 | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| SG2013049408A (en) | 2014-06-27 |
| KR20140058323A (en) | 2014-05-14 |
| DE102013214132B4 (en) | 2022-03-10 |
| TW201419494A (en) | 2014-05-16 |
| CN103811485A (en) | 2014-05-21 |
| DE102013214132A1 (en) | 2014-05-08 |
| TWI562331B (en) | 2016-12-11 |
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