CA2193401A1 - Vertical mos-fet with improved breakdown voltages - Google Patents
Vertical mos-fet with improved breakdown voltagesInfo
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- CA2193401A1 CA2193401A1 CA002193401A CA2193401A CA2193401A1 CA 2193401 A1 CA2193401 A1 CA 2193401A1 CA 002193401 A CA002193401 A CA 002193401A CA 2193401 A CA2193401 A CA 2193401A CA 2193401 A1 CA2193401 A1 CA 2193401A1
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- 230000015556 catabolic process Effects 0.000 title claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 35
- 239000004065 semiconductor Substances 0.000 claims abstract description 31
- 239000004020 conductor Substances 0.000 claims abstract description 25
- 238000000034 method Methods 0.000 claims description 30
- 238000004519 manufacturing process Methods 0.000 claims description 27
- 239000012535 impurity Substances 0.000 claims description 7
- 230000003247 decreasing effect Effects 0.000 abstract description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- 239000000463 material Substances 0.000 description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 238000002161 passivation Methods 0.000 description 3
- 230000000903 blocking effect Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 101150022794 IDS2 gene Proteins 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000013021 overheating Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
In a vertical MOS-FET, the ON resistance is decreased and source-drain and gate-source breakdown voltages are increased. The vertical MOS-FET includes a first layer formed at a deep location in a semiconductor substrate, a second layer formed at a shallower location than the first layer, a third layer formed at a shallower location than the second layer and exposed on a surface of the substrate, a trench extending from the substrate surface through the third and second layers to the first layer, an insulating layer covering a side wall and a bottom of the trench, a conductor surrounded by the insulating layer and filling the trench, and a fourth layer located in the first layer to cover a boundary between the side wall and bottom of the trench and vicinities of the boundary with the insulating layer interposed between them. The first and third layers are of the same conduction type, whereas the second and fourth layers are of a reverse conduction type.
The conductor serves as a gate electrode such that a channel is formed in the second layer. A depletion layer is formed between the first and fourth layers such that the breakdown voltages are improved.
The conductor serves as a gate electrode such that a channel is formed in the second layer. A depletion layer is formed between the first and fourth layers such that the breakdown voltages are improved.
Description
"` 2193401 VERTICAL MOS-FET WITH IMPROVED BREAKDOWN VOLTAGES
BACKGROUND OF THE INVENTION
1.Field of the Invention This invention relates generally to semiconductor devices and a method of fabricating the same, and more particularly to a technique for improving breakdown voltages of a vertical MOS-FET.
BACKGROUND OF THE INVENTION
1.Field of the Invention This invention relates generally to semiconductor devices and a method of fabricating the same, and more particularly to a technique for improving breakdown voltages of a vertical MOS-FET.
2.Description of the Prior Art The prior art has proposed vertical MOS-FETs with a trench gate to reduce the ON resistance of the MOS-FETs. These vertical MOS-FETs are disclosed in articles entitled "Trench Structure 60 V
Breakdown Voltage Power MOSFET" (Mitsubishi Electromechanical Technique Vol. 69 No . 3 1995, pp. 63 to 66) and "A STUDY ON A
HIGH BLOCKING VOLTAGE UMOS-FET WITH A DOUBLE GATE
STRUCTURE" (Proceedings of 1992 International Symposium on Power Semiconductor Devices & ICs, Tokyo, pp. 300 to 302), and Japanese Laid-Open Utility Model Publication No. 63-124762.
FIG. 11 illustrates the structure of a conventional vertical MOS-FET with a shallow trench gate. The structure is described in the aforementioned article entitled " Trench Structure 60 V Breakdown Voltage Power MOSFET" and in the aforementioned Publication No. 63-124762 Reférring to FIG. 11, reference numeral 60 designates a semiconductor substrate which includes a lower first layer 61a formed at the deepest location thereof, an upper first layer 61b formed at a shallower location than the lower first layer 61 a, a second layer 62 formed at a shallower location than the upper first layer 61 b, and a third layer 63 formed at a shallower location than the second layer 62.
The third layer 63 is exposed on a surface 60a of the semiconductor substrate 60. The lower and upper first layers 61a and 61b are of the n-type. The lower first layer 61 a is formed of an n+-type silicon semiconductor material itself. The upper first layer 61b is formed as a part of an n~-type silicon layer 65 formed on the upper surface of the lower first layer 61 a by an epitaxial growth process. The lower and upper first layers 61a and 61b constitute an n-type first layer 61. The second layer 62 is of the p-type and is formed by diffusing p-type impurities into an upper half of the silicon layer 65 formed by the epitaxial growth process. The third layer 63 is of the n+-type and is formed by diffusing n-type impurities locally in the vicinity of the surface of the second layer 62. The first to third layers 61 to 63 are composed of the semiconductor material 61 a and the silicon layer 65 formed on the surface of the material 61 a by the epitaxial growth process, constituting the semiconductor substrate 60.
The semiconductor device of FIG. 11 has the first layer 61 formed at a deep location in the semiconductor substrate 60, the second layer 62 formed at a shallower location than the first layer 61, and the third layer 63 formed at a shallower location than the second layer 62 to be exposed on the surface 60a of the substrate 60. The first and third layers 61 and 63 are of the same conduction type, whereas the second layer 62 is of the reverse conduction type.
The semiconductor substrate 60 is formed with a trench 67 extending from the surface 60a of the semiconductor substrate 60 through the third and second layers 63 and 62, reaching the first layer 61. A side wall 67a and bottom 67b of the trench 67 are covered by an insulating layer 69. A conductor 68 is disposed to be surrounded by the insulating layer 69. The conductor 68 fills up the trench 67.
Reference numeral 73 designates a passivation layer, reference numeral 72 a source electrode, and reference numeral 71 a drain electrode.
The conductor 68 is connected to a gate electrode (not shown) and insulated from the source electrode 72 by the insulating layer 69.
The semiconductor device of FIG. 11 is used under the condition that voltage is applied between the source electrode 72 and the drain electrode 71. The conduction type of the p-type second layer 62 in the vicinity of the side wall 67a of the trench 67 is reversed when voltage is applied to the conductor 68, and thus the device is rendered conductive between the first and third layers 61 and 63. More specifically, the source and drain electrodes 72 and 71 are on-off controlled by the voltage applied to the gate electrode (not shown) or conductor 68. The semiconductor device of FIG. 11 is a vertical MOS-FET. Reference numeral 70 designates a depletion layer produced when voltage is applied to the gate electrode or conductor 68.
FIG. 20 illustrates the structure of another conventional vertical MOS-FET with a deep trench gate. The structure is described in the aforementioned article entitled "A STUDY ON A HIGH BLOCKING
VOLTAGE UMOS-FET WITH A DOUBLE GATE STRUCTURE".
FIGS. 12 to 19 illustrate a fabrication process for the vertical MOS-FET shown in FIG. 20. Referring first to FIG. 12, an n~-type silicon layer 85 is formed on a surface 81x of an n+-type silicon semiconductor material 81 a by the epitaxial growth process. P-type impurities are diffused into the silicon layer 85 so that a p-type diffused layer 82 is formed on an upper layer. An n+-type diffused layer 83 is formed locally on the surface of the diffused layer 82. A semiconductor substrate 80 is fabricated at this stage. The semiconductor substrate 80 is formed with an n-type first layer 81 at the deepest location thereof, a p-type second layer 82 at a shallower location than the first layer 81, an n-type third layer 83 at a shallower location than the second layer 82. An oxide film 95 is formed on the surface of the semiconductor substrate 80. The substrate 80 is then etched from an opening 95a formed in the oxide film 95 so that a trench 87 is formed which extends through the n+-type third layer 83, p-type second layer 82 and n~-type upper first layer 81b to the n+-type lower first layer 81a, as shown in FIG. 13. The trench 87 is deeper than that shown in FIG. 11. A thick insulating oxide film 89a is formed to cover a side wall 87a and a bottom 87b of the trench 87, as shown in FIG. 14. A
conductive polysilicon layer 88 fills up the trench 87, surrounded by the oxide film 89a, as shown in FIG. 15. An upper half of the thick oxide film 89a is removed with a lower half thereof remaining, as shown in FIG. 16. A thin oxide film 89d is formed instead of the removed portion of the thick oxide film 89a, as shown in FIG. 17. The trench 87 is again filled with a conductive polysilicon layer 88a, as shown in FIG. 18. The added polysilicon layer 88a is integrated with the `` 21939~1 original polysilicon layer 88. An insulating oxide film 89e is formed on the surface of the semiconductor substrate 80, as shown in FIG. 19.
Finally, a part of the oxide film 89e is removed, and a source electrode 92, a drain electrode 91 and a passivation film 93 are sequentially formed. Reference numeral 90 designates a depletion layer produced when voltage is applied to the conductor 88 serving as a gate electrode.
MOS-FET having a shallow trench gate as shown in FIG. 11 has a large ON resistance between the source and drain electrodes since a current flows through an n~-type epitaxial layer 61 b having a large resistance component or the upper first layer. The trench 67 is preferably deep in order that the ON resistance is rendered small, and in particular, it preferably reaches the n+-type lower first layer 61a having a small resistance. MOS-FET having a deep trench gate 88 as shown in FIG. 20 has a small ON resistance since a channel is formed in the upper first layer 81b having a large resistance.
As the trench 87 is rendered deep, however, a drain field tends to concentrate more in the vicinity of the bottom of the trench 87 and more particularly, near the boundary 87c between the side wall 87a and the bottom 87b, and thus the drain-source breakdown voltage and the drain-gate breakdown voltage are lowered. Particularly, when the trench 87 is deep so as to reach the n+-type lower first layer 81a through the n~-type upper first layer 81 b, the depletion layer 90 insufficiently extends to the lower first layer 81a side and consequently, the drain-source and drain-gate breakdown voltages are considerably lowered .
`~ 219~401 To avoid the electric field concentration on a corner 67c between the trench side wall 67a and bottom 67b, MOS-FET having a shallow trench gate 68 as shown in FIG. 11 is fabricated so that the trench bottom 67b is slightly deeper than and smoothly continuous to the bottom of the p-type second layer 62. However, since the current flows through the n~-type first layer 61 b having a relatively large resistance component in MOS-FET having a shallow trench gate, the ON
resistance cannot be reduced, as described above.
On the other hand, the ON resistance can be reduced in MOS-FET
having a deep trench gate as shown in FIG. 20 since a channel is formed in the upper first layer 81 b having a large resistance. However, the drain-source and drain-gate breakdown voltages are lowered, which raises a new problem.
In MOS-FET having a deep trench gate as shown in FIG. 20, the thickness in the lower half insulating film 89c of the trench 87 is rendered larger than that in the upper half insulating film 89d so that the lowering of breakdown voltages is prevented. However, the n~-type upper first layer 81 b cannot achieve a sufficient carrier storage effect when the thickness in the lower half insulating film 89c is increased, and thus the ON resistance cannot sufficiently be reduced.
Furthermore, concentration of stress due to the thick insulating film 89c tends to result in crystal defects in the boundary 87c between the trench side wall 87a and the bottom 87b. Furthermore, MOS-FET
shown in FIG. 20 necessitates complicated steps in the fabrication process as shown in FIGS. 12 to 19, which steps increase the fabrication cost 2193~01 thereof.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is to provide a vertical MOS-FET which can overcome the above-described drawbacks in the prior art and which has a small ON resistance and high source-drain and gate-drain breakdown voltages, and a method of fabricating the same.
The present invention provides a vertical MOS-FET with improved breakdown voltages, which comprises a first layer provided at a deep location in a semiconductor substrate, a second layer provided at a shallower location than the first layer, a third layer provided at a shallower location than the second layer and exposed on a surface of the substrate, a trench extending from the substrate surface through the third and second layers to the first layer, the trench having a side wall and a bottom, an insulating layer covering the side wall and the bottom of the trench, a conductor surrounded by the insulating layer and filling the trench, and a fourth layer located in the first layer to cover a boundary between the side wall and the bottom of the trench and vicinities thereof with the insulating layer interposed therebetween.
The first and third layers are of the same conduction type, whereas the second and fourth layers are of a reverse conduction type. The conductor serves as a gate electrode such that a channel is formed in the second layer.
When the first layer includes a lower first layer and an upper first layer, the trench preferably extends through the upper first layer to the lower first layer, and the fourth layer is preferably located in the lower first layer.
According to MOS-FET fabricated as described above, the fourth layer relaxes the concentration of electric field in the vicinity of a first layer side end of the conductor embedded in the trench. Consequently, the gate-drain and source-drain breakdown voltages can be ensured even when the thickness of the insulating film is redllce~l The present invention also provides a method of fabricating a vertical MOS-FET comprising the steps of forming a first layer at a deep location in a semiconductor substrate, forming a second layer at a shallower location than the first layer, forming a third layer at a shallower location than the second layér to be exposed on a surface of the substrate, forming a trench extending from the substrate surface through the third and second layers to the first layer, the trench having a side wall and a bottom, forming an insulating layer covering the side wall and the bottom of the trench, forming a fourth layer located in the first layer to cover a boundary between the side wall and the bottom of the trench and vicinities thereof with the insulating layer interposed therebetween, and forming a conductor surrounded by the insulating layer and filling the trench. In the method, the first and third layers are of the same conduction type, whereas the second and fourth layers are of a reverse conduction type, and the conductor serves as a gate electrode such that a channel is formed in the second layer.
According to the above-described method, the above-described MOS-FET with improved breakdown voltages can be fabricated through `" 219340I
relatively simple steps in the fabrication process.
This invention will be understood better upon a reading of the following detailed description of the preferred embodiments and claims with reference to the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a view showing a first state of a fabrication process in a first embodiment in accordance with the present invention;
FIG. 2 is a view showing a second state of the fabrication process in the first embodiment;
FIG. 3 is a view showing a third state of the fabrication process in the first embodiment;
FIG. 4 is a view showing a fourth state of the fabrication process in the first embodiment;
FIG. 5 is a view showing a fifth state of the fabrication process in the first embodiment;
FIG. 6 is a view showing a sixth state of the fabrication process in the first embodiment;
FIG. 7 is a view showing a seventh state of the fabrication process in the first embodiment and the structure of MOS-FET of the first embodiment;
FIG. 8 is a view showing the structure of MOS-FET of a second embodiment in accordance with the present invention;
FIG. 9 is a circuit diagram showing an electric circuit equivalent to MOS-FET of FIG. 8;
FIG. 10 is a graph showing electric characteristics of MOS-FET of FIG. 8;
FIG. 11 is a view showing the structure of a conventional MOS-FET having a shallow trench gate;
FIG. 12 is a view showing a first state of a fabrication process of another conventional MOS-FET with a deep trench gate;
FIG. 13 is a view showing a second state of the fabrication process of the conventional MOS-FET with the deep trench gate;
FIG. 14 is a view showing a third state of the fabrication process of the conventional MOS-FET with the deep trench gate;
FIG. 15 is a view showing a fourth state of the fabrication process of the conventional MOS-FET with the deep trench gate;
FIG. 16 is a view showing a fifth state of the fabrication process of the conventional MOS-FET with the deep trench gate;
FIG. 17 is a view showing a sixth state of the fabrication process of the conventional MOS-FET with the deep trench gate;
FIG. 18 is a view showing a seventh state of the fabrication process of the conventional MOS-FET with the deep trench gate;
FIG. 19 is a view showing an eighth state of the fabrication process of the conventional MOS-FET with the deep trench gate; and FIG. 20 is a view showing a ninth state of the fabrication process of the conventional MOS-FET with the deep trench gate and the structure thereof.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
A first preferred embodiment of the present invention will be described with reference to FIGS. 1 to 7. FIGS. 1 to 6 illustrate the ``` 2~93401 steps in the fabrication process with the progress of time and FIG. 7 shows the structure of a completed semiconductor device.
An n~-type silicon epitaxial layer 15 (hereinafter, "n~-type epitaxial layer") is first fabricated on an n+-type silicon material 1 la (hereinafter, "n+-type material"), as shown in FIG. 1. P-type impurities are diffused into the n~-type epitaxial layer 15 at its shallow location so that a second layer 12 is fabricated. N-type impurities are further diffused locally onto the surface of the second layer 12 so that a third layer 13 is fabricated. The n~-type epitaxial layer 15 includes an n-type region at its deep location, which n-type region forms an upper first layer 1 lb. A lower first layer 1 la fabricated from the n+-type material and the upper first layer 11b are of the same conduction type and constitute a first layer 11 together. The first layer 11 serves as an n-type drain region, the second layer 12 as a p-type base region, and the third layer 13 as an n+-type source region, as will be described later. The first layer 11 serving as the n-type drain region, the second layer 12 serving as the p-type base region, and the third layer 13 serving as the n+-type source region are fabricated in the semiconductor substrate 10 in the above-described steps in the order from the deepest location thereof. Subsequently, an oxide film 25 serving as an insulating film is formed on the surface 1 Oa of the substrate 10. The insulating film 25 is formed to cover the surfaces of the second and third layers 12 and 13.
An opening 25a is formed in a portion of the insulating film 25 where a gate electrode is to be formed, as shown in FIG. 2. A trench .
17 is formed in the portion where the gate electrode is to be formed, by means of anisotropic etching wherein the insulating film 25 serves as a mask. The trench 17 is formed to extend to the lower first layer 1 1a sequentially through the third layer 13 serving as an n+-type source region, the second layer 12 serving as a p-type base region and the upper first layer 11b.
An insulating oxide film 1 9a is formed to cover a side wall 1 7a and a bottom 1 7b of the trench 17, as shown in FIG. 3 . Reference symbol 17c designates corners formed in the boundary between the side wall 17a and the bottom 17b of the trench 17.
P-type impurities are injected via the insulating film 1 9a on the bottom 1 7b of the trench 1 7 into the n-type first layer 11 by ion implantation and then heat treated to be formed into a p-type fourth layer 14, as shown in FIG. 4. The corners 1 7c of the trench 17 are covered by the p-type fourth layer 14 with the insulating film 1 9a interposed therebetween.
The trench 17 is filled with a conductive polysilicon 18 serving as a gate electrode, as shown in FIG. 5. The conductor 18 fills up the trench 17 with the insulating film l9a surrounding the former.
An insulating oxide film 1 9b is formed to cover the conductor 18 in the trench 17, as shown in FIG. 6. The insulating film 1 9b is rendered continuous to the insulating film 1 9a to thereby form an insulating layer with the latter.
The insulating film 1 9b is removed with a portion 1 9c thereof covering the trench 17 remaining, so that a part of the surface of the `" 21 third layer 13 serving as the n+-type source region and the surface of the second layer 12 serving as the p-type base region are exposed, as shown in FIG. 7. A source electrode 22 is formed on the surfaces of the second and third layers 12 and 13. A passivation layer 23 is then formed to cover the surface of the source electrode 22. Finally, a drain electrode 21 is formed on the bottom surface of the substrate 10.
Reference numeral 20 designates a depletion layer produced when voltage is applied to the conductor 18 serving as a gate electrode.
In the structure as described above, the trench 17 preferably has such a depth that it reaches the n+-type material or the lower first layer 1 la. The fourth layer 14 as the p-type diffusion layer needs to be separated from the second layer 12 serving as the p-type base region in order for the above-described MOS-FET to operate as a transistor.
The depletion layer 20 is formed in a pn junction between the p-type fourth layer 14 and the n+-type lower first layer 1 la or the n~-type upper first layer 1 lb in the vicinity of the bottom of the trench 17 when a reverse-bias voltage is applied across the drain and source. Since the pn junction has a larger radius of curvature than each corner 17c of the trench bottom, the electric field is relaxed at each corner 1 7c.
Consequently, the drain-source breakdown voltage is not reduced even when the trench 17 is so deep as to reach the n+-type lower first layer 1 1 a.
On the other hand, the drain-gate breakdown voltage is maintained by increasing the thickness of the insulating film on the trench bottom in the prior art shown in FIG. 20 since the depletion layer 90 in the "-- 21g3~01 vicinity of the trench bottom does not extend sufficiently to the semiconductor substrate side. In the embodiment, however, the breakdown voltage is maintained by both of the depletion layer 20 in the pn junction and the insulating film l9a, and thus the same voltage as the drain-source voltage is not applied to the insulating film 1 9a.
Accordingly, the insulating film 1 9a need not be partially thickened since a voltage lower than the drain-source voltage is applied thereto.
Consequently, the carrier storage effect is higher in the upper first layer llb adjacent to the conductor 18 serving as the gate electrode in the embodiment as compared with the prior art, and accordingly, a power MOS-FET having a small ON resistance is obtained.
Furthermore, an occurrence of crystal defect caused by a thick insulating film is reduced. Furthermore, the reliability of the gate oxide film 1 9a is improved since a high voltage is not applied to the insulating film (gate oxide film). Additionally, the fabrication steps can be simplified and the fabrication cost can be reduced.
As obvious from the foregoing, the above-described vertical MOS-FET has the first layer 11 provided at a deep location in the semiconductor substrate 10, the second layer 12 provided at a shallower location than the first layer 11, the third layer 13 provided at a shallower location than the second layer 12 and exposed on a surface of the substrate 10, the trench 17 extending from the substrate surface through the third and second layers 13 and 12 to the first layer 11, the insulating layer 1 9a covering the side wall 1 7a and the bottom 1 7b of the trench 17, the conductor 18 surrounded by the insulating layer 19a and filling the trench 17, and the fourth layer 14 located in the first layer 11 to cover the boundary between the side wall 17a and the bottom 17b of the trench 17 and the vicinities of the boundary 17c with the insulating layer 19a interposed therebetween. The first and third layers 11 and 13 are of the same conduction type, whereas the second and fourth layers 12 and 14 are of a reverse conduction type, and the conductor 18 serves as a gate electrode such that a channel is formed in the second layer 12. The depletion layer 20 is formed between the first and fourth layers 11 and 14 such that the breakdown voltage is mproved .
FIG. 8 illustrates the structure of a second embodiment. In the shown structure, a pair of third layers 113r and 1131 are formed for a single first layer 111 and a single second layer 112. A pair of trenches 117r and 1171 are formed for the paired third layers 113r and 1131. A
pair of fourth layers 114r and 1141 are formed for the paired trenches 117r and 1171. Each trench has the same structure as the trench 17 in the first embodiment. Reference numeral 120 designates a depletion layer produced when voltage is applied to the paired conductors 118r and 1181. Reference numeral 124 designates a channel resistance (JFET resistance) of a parasitic vertical field effect transistor.
MOS-FET constituted as described above is operated in a similar manner to that in the first embodiment. Furthermore, a positive use of the JFET resistance 124 formed between the pair of p-type fourth layers 114r and 1141 limits the drain current in a saturation region, and thus a power MOS-FET with a high load short-circuit withstanding capability ~ 2193~01 can be obtained.
More specifically, the distance between the pair of trenches 117r and 1171 and the diffusion profile of the pair of p-type fourth layers 11 4r and 11 41 are suitably selected so that the depletion layer 1 20 can be adjusted in accordance with the drain-source voltage VDs where the depletion layer 120 is spread to thereby increase the JFET resistance.
Consequently, as in the VDS-IDs characteristics shown in FIG. 10, the characteristic that the drain current IDS is decreased in the saturation region can be attained. That is, the drain current IDS takes the maximum IDSl shown by a in FIG. 10 when VDs=Vs. When the voltage is raised to VDD in this state, the drain current IDS is decreased to the value IDS2 shown by _ in FIG. 10.
Furthermore, the JFET resistance formed between the p-type fourth layers 11 4r and 11 41 can be set at an optional value when a suitable distance between the pair of trenches 1 1 7r and 1 171 and a suitable diffusion profile of the pair of p-type fourth layers 11 4r and 1141 are selected. Accordingly, the JFET resistance can be set to be sufficiently small in an active region such that an increase in the ON
resistance is prevented, whereas the JFET resistance can be set to be sufficiently large by the spread of the depletion layer 120 in the saturation region. Consequently, a power MOS-FET with a high load short-circuit withstanding capability can be obtained by effectively using the above-described characteristics.
An excessively large amount of power is consumed in the conventional power MOS-FETs in the occurrence of a load short-circuit in a drive circuit of a load 52 as shown in FIG. 9. The power MOS-FET Sl would be damaged in the worst case. According to the present invention, however, when the occurrence of short circuit in the load 52 leads the power MOS-FET 52 to the saturation region, MOS-FET S l limits the drain current such that heat generation thereof is restrained.
Consequently, the power MOS-FET of the present invention has a higher load short-circuit withstanding capability than the conventional MO S -FET s .
The prior art has required a protecting circuit for protecting the power MOS-FET S l against overheating and overcurrent so that the power MOS-FET S l can be prevented from being damaged in the occurrence of short circuit in the load 52. However, MOS-FET of the second embodiment necessitates no such dedicated protecting circuit.
Consequently, the system can be rendered small in size and low in cost.
In each of the above-described embodiments, the conduction types in the semiconductor substrate may be changed between the p-type and the n-type.
According to the semiconductor device of the present invention, the ON resistance can be reduced and the source-drain and gate-drain breakdown voltages can be increased in the field effect semiconductor device .
According to the method of the present invention, the semiconductor device having the above-described features can easily be fabricated .
The foregoing description and drawings are merely illustrative of -the principles of the present invention and are not to be construed in a limiting sense. Various changes and modifications will become apparent to those of ordinary skill in the art. All such changes and modifications are seen to fall within the true spirit and scope of the invention as defined by the appended claims.
Breakdown Voltage Power MOSFET" (Mitsubishi Electromechanical Technique Vol. 69 No . 3 1995, pp. 63 to 66) and "A STUDY ON A
HIGH BLOCKING VOLTAGE UMOS-FET WITH A DOUBLE GATE
STRUCTURE" (Proceedings of 1992 International Symposium on Power Semiconductor Devices & ICs, Tokyo, pp. 300 to 302), and Japanese Laid-Open Utility Model Publication No. 63-124762.
FIG. 11 illustrates the structure of a conventional vertical MOS-FET with a shallow trench gate. The structure is described in the aforementioned article entitled " Trench Structure 60 V Breakdown Voltage Power MOSFET" and in the aforementioned Publication No. 63-124762 Reférring to FIG. 11, reference numeral 60 designates a semiconductor substrate which includes a lower first layer 61a formed at the deepest location thereof, an upper first layer 61b formed at a shallower location than the lower first layer 61 a, a second layer 62 formed at a shallower location than the upper first layer 61 b, and a third layer 63 formed at a shallower location than the second layer 62.
The third layer 63 is exposed on a surface 60a of the semiconductor substrate 60. The lower and upper first layers 61a and 61b are of the n-type. The lower first layer 61 a is formed of an n+-type silicon semiconductor material itself. The upper first layer 61b is formed as a part of an n~-type silicon layer 65 formed on the upper surface of the lower first layer 61 a by an epitaxial growth process. The lower and upper first layers 61a and 61b constitute an n-type first layer 61. The second layer 62 is of the p-type and is formed by diffusing p-type impurities into an upper half of the silicon layer 65 formed by the epitaxial growth process. The third layer 63 is of the n+-type and is formed by diffusing n-type impurities locally in the vicinity of the surface of the second layer 62. The first to third layers 61 to 63 are composed of the semiconductor material 61 a and the silicon layer 65 formed on the surface of the material 61 a by the epitaxial growth process, constituting the semiconductor substrate 60.
The semiconductor device of FIG. 11 has the first layer 61 formed at a deep location in the semiconductor substrate 60, the second layer 62 formed at a shallower location than the first layer 61, and the third layer 63 formed at a shallower location than the second layer 62 to be exposed on the surface 60a of the substrate 60. The first and third layers 61 and 63 are of the same conduction type, whereas the second layer 62 is of the reverse conduction type.
The semiconductor substrate 60 is formed with a trench 67 extending from the surface 60a of the semiconductor substrate 60 through the third and second layers 63 and 62, reaching the first layer 61. A side wall 67a and bottom 67b of the trench 67 are covered by an insulating layer 69. A conductor 68 is disposed to be surrounded by the insulating layer 69. The conductor 68 fills up the trench 67.
Reference numeral 73 designates a passivation layer, reference numeral 72 a source electrode, and reference numeral 71 a drain electrode.
The conductor 68 is connected to a gate electrode (not shown) and insulated from the source electrode 72 by the insulating layer 69.
The semiconductor device of FIG. 11 is used under the condition that voltage is applied between the source electrode 72 and the drain electrode 71. The conduction type of the p-type second layer 62 in the vicinity of the side wall 67a of the trench 67 is reversed when voltage is applied to the conductor 68, and thus the device is rendered conductive between the first and third layers 61 and 63. More specifically, the source and drain electrodes 72 and 71 are on-off controlled by the voltage applied to the gate electrode (not shown) or conductor 68. The semiconductor device of FIG. 11 is a vertical MOS-FET. Reference numeral 70 designates a depletion layer produced when voltage is applied to the gate electrode or conductor 68.
FIG. 20 illustrates the structure of another conventional vertical MOS-FET with a deep trench gate. The structure is described in the aforementioned article entitled "A STUDY ON A HIGH BLOCKING
VOLTAGE UMOS-FET WITH A DOUBLE GATE STRUCTURE".
FIGS. 12 to 19 illustrate a fabrication process for the vertical MOS-FET shown in FIG. 20. Referring first to FIG. 12, an n~-type silicon layer 85 is formed on a surface 81x of an n+-type silicon semiconductor material 81 a by the epitaxial growth process. P-type impurities are diffused into the silicon layer 85 so that a p-type diffused layer 82 is formed on an upper layer. An n+-type diffused layer 83 is formed locally on the surface of the diffused layer 82. A semiconductor substrate 80 is fabricated at this stage. The semiconductor substrate 80 is formed with an n-type first layer 81 at the deepest location thereof, a p-type second layer 82 at a shallower location than the first layer 81, an n-type third layer 83 at a shallower location than the second layer 82. An oxide film 95 is formed on the surface of the semiconductor substrate 80. The substrate 80 is then etched from an opening 95a formed in the oxide film 95 so that a trench 87 is formed which extends through the n+-type third layer 83, p-type second layer 82 and n~-type upper first layer 81b to the n+-type lower first layer 81a, as shown in FIG. 13. The trench 87 is deeper than that shown in FIG. 11. A thick insulating oxide film 89a is formed to cover a side wall 87a and a bottom 87b of the trench 87, as shown in FIG. 14. A
conductive polysilicon layer 88 fills up the trench 87, surrounded by the oxide film 89a, as shown in FIG. 15. An upper half of the thick oxide film 89a is removed with a lower half thereof remaining, as shown in FIG. 16. A thin oxide film 89d is formed instead of the removed portion of the thick oxide film 89a, as shown in FIG. 17. The trench 87 is again filled with a conductive polysilicon layer 88a, as shown in FIG. 18. The added polysilicon layer 88a is integrated with the `` 21939~1 original polysilicon layer 88. An insulating oxide film 89e is formed on the surface of the semiconductor substrate 80, as shown in FIG. 19.
Finally, a part of the oxide film 89e is removed, and a source electrode 92, a drain electrode 91 and a passivation film 93 are sequentially formed. Reference numeral 90 designates a depletion layer produced when voltage is applied to the conductor 88 serving as a gate electrode.
MOS-FET having a shallow trench gate as shown in FIG. 11 has a large ON resistance between the source and drain electrodes since a current flows through an n~-type epitaxial layer 61 b having a large resistance component or the upper first layer. The trench 67 is preferably deep in order that the ON resistance is rendered small, and in particular, it preferably reaches the n+-type lower first layer 61a having a small resistance. MOS-FET having a deep trench gate 88 as shown in FIG. 20 has a small ON resistance since a channel is formed in the upper first layer 81b having a large resistance.
As the trench 87 is rendered deep, however, a drain field tends to concentrate more in the vicinity of the bottom of the trench 87 and more particularly, near the boundary 87c between the side wall 87a and the bottom 87b, and thus the drain-source breakdown voltage and the drain-gate breakdown voltage are lowered. Particularly, when the trench 87 is deep so as to reach the n+-type lower first layer 81a through the n~-type upper first layer 81 b, the depletion layer 90 insufficiently extends to the lower first layer 81a side and consequently, the drain-source and drain-gate breakdown voltages are considerably lowered .
`~ 219~401 To avoid the electric field concentration on a corner 67c between the trench side wall 67a and bottom 67b, MOS-FET having a shallow trench gate 68 as shown in FIG. 11 is fabricated so that the trench bottom 67b is slightly deeper than and smoothly continuous to the bottom of the p-type second layer 62. However, since the current flows through the n~-type first layer 61 b having a relatively large resistance component in MOS-FET having a shallow trench gate, the ON
resistance cannot be reduced, as described above.
On the other hand, the ON resistance can be reduced in MOS-FET
having a deep trench gate as shown in FIG. 20 since a channel is formed in the upper first layer 81 b having a large resistance. However, the drain-source and drain-gate breakdown voltages are lowered, which raises a new problem.
In MOS-FET having a deep trench gate as shown in FIG. 20, the thickness in the lower half insulating film 89c of the trench 87 is rendered larger than that in the upper half insulating film 89d so that the lowering of breakdown voltages is prevented. However, the n~-type upper first layer 81 b cannot achieve a sufficient carrier storage effect when the thickness in the lower half insulating film 89c is increased, and thus the ON resistance cannot sufficiently be reduced.
Furthermore, concentration of stress due to the thick insulating film 89c tends to result in crystal defects in the boundary 87c between the trench side wall 87a and the bottom 87b. Furthermore, MOS-FET
shown in FIG. 20 necessitates complicated steps in the fabrication process as shown in FIGS. 12 to 19, which steps increase the fabrication cost 2193~01 thereof.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is to provide a vertical MOS-FET which can overcome the above-described drawbacks in the prior art and which has a small ON resistance and high source-drain and gate-drain breakdown voltages, and a method of fabricating the same.
The present invention provides a vertical MOS-FET with improved breakdown voltages, which comprises a first layer provided at a deep location in a semiconductor substrate, a second layer provided at a shallower location than the first layer, a third layer provided at a shallower location than the second layer and exposed on a surface of the substrate, a trench extending from the substrate surface through the third and second layers to the first layer, the trench having a side wall and a bottom, an insulating layer covering the side wall and the bottom of the trench, a conductor surrounded by the insulating layer and filling the trench, and a fourth layer located in the first layer to cover a boundary between the side wall and the bottom of the trench and vicinities thereof with the insulating layer interposed therebetween.
The first and third layers are of the same conduction type, whereas the second and fourth layers are of a reverse conduction type. The conductor serves as a gate electrode such that a channel is formed in the second layer.
When the first layer includes a lower first layer and an upper first layer, the trench preferably extends through the upper first layer to the lower first layer, and the fourth layer is preferably located in the lower first layer.
According to MOS-FET fabricated as described above, the fourth layer relaxes the concentration of electric field in the vicinity of a first layer side end of the conductor embedded in the trench. Consequently, the gate-drain and source-drain breakdown voltages can be ensured even when the thickness of the insulating film is redllce~l The present invention also provides a method of fabricating a vertical MOS-FET comprising the steps of forming a first layer at a deep location in a semiconductor substrate, forming a second layer at a shallower location than the first layer, forming a third layer at a shallower location than the second layér to be exposed on a surface of the substrate, forming a trench extending from the substrate surface through the third and second layers to the first layer, the trench having a side wall and a bottom, forming an insulating layer covering the side wall and the bottom of the trench, forming a fourth layer located in the first layer to cover a boundary between the side wall and the bottom of the trench and vicinities thereof with the insulating layer interposed therebetween, and forming a conductor surrounded by the insulating layer and filling the trench. In the method, the first and third layers are of the same conduction type, whereas the second and fourth layers are of a reverse conduction type, and the conductor serves as a gate electrode such that a channel is formed in the second layer.
According to the above-described method, the above-described MOS-FET with improved breakdown voltages can be fabricated through `" 219340I
relatively simple steps in the fabrication process.
This invention will be understood better upon a reading of the following detailed description of the preferred embodiments and claims with reference to the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a view showing a first state of a fabrication process in a first embodiment in accordance with the present invention;
FIG. 2 is a view showing a second state of the fabrication process in the first embodiment;
FIG. 3 is a view showing a third state of the fabrication process in the first embodiment;
FIG. 4 is a view showing a fourth state of the fabrication process in the first embodiment;
FIG. 5 is a view showing a fifth state of the fabrication process in the first embodiment;
FIG. 6 is a view showing a sixth state of the fabrication process in the first embodiment;
FIG. 7 is a view showing a seventh state of the fabrication process in the first embodiment and the structure of MOS-FET of the first embodiment;
FIG. 8 is a view showing the structure of MOS-FET of a second embodiment in accordance with the present invention;
FIG. 9 is a circuit diagram showing an electric circuit equivalent to MOS-FET of FIG. 8;
FIG. 10 is a graph showing electric characteristics of MOS-FET of FIG. 8;
FIG. 11 is a view showing the structure of a conventional MOS-FET having a shallow trench gate;
FIG. 12 is a view showing a first state of a fabrication process of another conventional MOS-FET with a deep trench gate;
FIG. 13 is a view showing a second state of the fabrication process of the conventional MOS-FET with the deep trench gate;
FIG. 14 is a view showing a third state of the fabrication process of the conventional MOS-FET with the deep trench gate;
FIG. 15 is a view showing a fourth state of the fabrication process of the conventional MOS-FET with the deep trench gate;
FIG. 16 is a view showing a fifth state of the fabrication process of the conventional MOS-FET with the deep trench gate;
FIG. 17 is a view showing a sixth state of the fabrication process of the conventional MOS-FET with the deep trench gate;
FIG. 18 is a view showing a seventh state of the fabrication process of the conventional MOS-FET with the deep trench gate;
FIG. 19 is a view showing an eighth state of the fabrication process of the conventional MOS-FET with the deep trench gate; and FIG. 20 is a view showing a ninth state of the fabrication process of the conventional MOS-FET with the deep trench gate and the structure thereof.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
A first preferred embodiment of the present invention will be described with reference to FIGS. 1 to 7. FIGS. 1 to 6 illustrate the ``` 2~93401 steps in the fabrication process with the progress of time and FIG. 7 shows the structure of a completed semiconductor device.
An n~-type silicon epitaxial layer 15 (hereinafter, "n~-type epitaxial layer") is first fabricated on an n+-type silicon material 1 la (hereinafter, "n+-type material"), as shown in FIG. 1. P-type impurities are diffused into the n~-type epitaxial layer 15 at its shallow location so that a second layer 12 is fabricated. N-type impurities are further diffused locally onto the surface of the second layer 12 so that a third layer 13 is fabricated. The n~-type epitaxial layer 15 includes an n-type region at its deep location, which n-type region forms an upper first layer 1 lb. A lower first layer 1 la fabricated from the n+-type material and the upper first layer 11b are of the same conduction type and constitute a first layer 11 together. The first layer 11 serves as an n-type drain region, the second layer 12 as a p-type base region, and the third layer 13 as an n+-type source region, as will be described later. The first layer 11 serving as the n-type drain region, the second layer 12 serving as the p-type base region, and the third layer 13 serving as the n+-type source region are fabricated in the semiconductor substrate 10 in the above-described steps in the order from the deepest location thereof. Subsequently, an oxide film 25 serving as an insulating film is formed on the surface 1 Oa of the substrate 10. The insulating film 25 is formed to cover the surfaces of the second and third layers 12 and 13.
An opening 25a is formed in a portion of the insulating film 25 where a gate electrode is to be formed, as shown in FIG. 2. A trench .
17 is formed in the portion where the gate electrode is to be formed, by means of anisotropic etching wherein the insulating film 25 serves as a mask. The trench 17 is formed to extend to the lower first layer 1 1a sequentially through the third layer 13 serving as an n+-type source region, the second layer 12 serving as a p-type base region and the upper first layer 11b.
An insulating oxide film 1 9a is formed to cover a side wall 1 7a and a bottom 1 7b of the trench 17, as shown in FIG. 3 . Reference symbol 17c designates corners formed in the boundary between the side wall 17a and the bottom 17b of the trench 17.
P-type impurities are injected via the insulating film 1 9a on the bottom 1 7b of the trench 1 7 into the n-type first layer 11 by ion implantation and then heat treated to be formed into a p-type fourth layer 14, as shown in FIG. 4. The corners 1 7c of the trench 17 are covered by the p-type fourth layer 14 with the insulating film 1 9a interposed therebetween.
The trench 17 is filled with a conductive polysilicon 18 serving as a gate electrode, as shown in FIG. 5. The conductor 18 fills up the trench 17 with the insulating film l9a surrounding the former.
An insulating oxide film 1 9b is formed to cover the conductor 18 in the trench 17, as shown in FIG. 6. The insulating film 1 9b is rendered continuous to the insulating film 1 9a to thereby form an insulating layer with the latter.
The insulating film 1 9b is removed with a portion 1 9c thereof covering the trench 17 remaining, so that a part of the surface of the `" 21 third layer 13 serving as the n+-type source region and the surface of the second layer 12 serving as the p-type base region are exposed, as shown in FIG. 7. A source electrode 22 is formed on the surfaces of the second and third layers 12 and 13. A passivation layer 23 is then formed to cover the surface of the source electrode 22. Finally, a drain electrode 21 is formed on the bottom surface of the substrate 10.
Reference numeral 20 designates a depletion layer produced when voltage is applied to the conductor 18 serving as a gate electrode.
In the structure as described above, the trench 17 preferably has such a depth that it reaches the n+-type material or the lower first layer 1 la. The fourth layer 14 as the p-type diffusion layer needs to be separated from the second layer 12 serving as the p-type base region in order for the above-described MOS-FET to operate as a transistor.
The depletion layer 20 is formed in a pn junction between the p-type fourth layer 14 and the n+-type lower first layer 1 la or the n~-type upper first layer 1 lb in the vicinity of the bottom of the trench 17 when a reverse-bias voltage is applied across the drain and source. Since the pn junction has a larger radius of curvature than each corner 17c of the trench bottom, the electric field is relaxed at each corner 1 7c.
Consequently, the drain-source breakdown voltage is not reduced even when the trench 17 is so deep as to reach the n+-type lower first layer 1 1 a.
On the other hand, the drain-gate breakdown voltage is maintained by increasing the thickness of the insulating film on the trench bottom in the prior art shown in FIG. 20 since the depletion layer 90 in the "-- 21g3~01 vicinity of the trench bottom does not extend sufficiently to the semiconductor substrate side. In the embodiment, however, the breakdown voltage is maintained by both of the depletion layer 20 in the pn junction and the insulating film l9a, and thus the same voltage as the drain-source voltage is not applied to the insulating film 1 9a.
Accordingly, the insulating film 1 9a need not be partially thickened since a voltage lower than the drain-source voltage is applied thereto.
Consequently, the carrier storage effect is higher in the upper first layer llb adjacent to the conductor 18 serving as the gate electrode in the embodiment as compared with the prior art, and accordingly, a power MOS-FET having a small ON resistance is obtained.
Furthermore, an occurrence of crystal defect caused by a thick insulating film is reduced. Furthermore, the reliability of the gate oxide film 1 9a is improved since a high voltage is not applied to the insulating film (gate oxide film). Additionally, the fabrication steps can be simplified and the fabrication cost can be reduced.
As obvious from the foregoing, the above-described vertical MOS-FET has the first layer 11 provided at a deep location in the semiconductor substrate 10, the second layer 12 provided at a shallower location than the first layer 11, the third layer 13 provided at a shallower location than the second layer 12 and exposed on a surface of the substrate 10, the trench 17 extending from the substrate surface through the third and second layers 13 and 12 to the first layer 11, the insulating layer 1 9a covering the side wall 1 7a and the bottom 1 7b of the trench 17, the conductor 18 surrounded by the insulating layer 19a and filling the trench 17, and the fourth layer 14 located in the first layer 11 to cover the boundary between the side wall 17a and the bottom 17b of the trench 17 and the vicinities of the boundary 17c with the insulating layer 19a interposed therebetween. The first and third layers 11 and 13 are of the same conduction type, whereas the second and fourth layers 12 and 14 are of a reverse conduction type, and the conductor 18 serves as a gate electrode such that a channel is formed in the second layer 12. The depletion layer 20 is formed between the first and fourth layers 11 and 14 such that the breakdown voltage is mproved .
FIG. 8 illustrates the structure of a second embodiment. In the shown structure, a pair of third layers 113r and 1131 are formed for a single first layer 111 and a single second layer 112. A pair of trenches 117r and 1171 are formed for the paired third layers 113r and 1131. A
pair of fourth layers 114r and 1141 are formed for the paired trenches 117r and 1171. Each trench has the same structure as the trench 17 in the first embodiment. Reference numeral 120 designates a depletion layer produced when voltage is applied to the paired conductors 118r and 1181. Reference numeral 124 designates a channel resistance (JFET resistance) of a parasitic vertical field effect transistor.
MOS-FET constituted as described above is operated in a similar manner to that in the first embodiment. Furthermore, a positive use of the JFET resistance 124 formed between the pair of p-type fourth layers 114r and 1141 limits the drain current in a saturation region, and thus a power MOS-FET with a high load short-circuit withstanding capability ~ 2193~01 can be obtained.
More specifically, the distance between the pair of trenches 117r and 1171 and the diffusion profile of the pair of p-type fourth layers 11 4r and 11 41 are suitably selected so that the depletion layer 1 20 can be adjusted in accordance with the drain-source voltage VDs where the depletion layer 120 is spread to thereby increase the JFET resistance.
Consequently, as in the VDS-IDs characteristics shown in FIG. 10, the characteristic that the drain current IDS is decreased in the saturation region can be attained. That is, the drain current IDS takes the maximum IDSl shown by a in FIG. 10 when VDs=Vs. When the voltage is raised to VDD in this state, the drain current IDS is decreased to the value IDS2 shown by _ in FIG. 10.
Furthermore, the JFET resistance formed between the p-type fourth layers 11 4r and 11 41 can be set at an optional value when a suitable distance between the pair of trenches 1 1 7r and 1 171 and a suitable diffusion profile of the pair of p-type fourth layers 11 4r and 1141 are selected. Accordingly, the JFET resistance can be set to be sufficiently small in an active region such that an increase in the ON
resistance is prevented, whereas the JFET resistance can be set to be sufficiently large by the spread of the depletion layer 120 in the saturation region. Consequently, a power MOS-FET with a high load short-circuit withstanding capability can be obtained by effectively using the above-described characteristics.
An excessively large amount of power is consumed in the conventional power MOS-FETs in the occurrence of a load short-circuit in a drive circuit of a load 52 as shown in FIG. 9. The power MOS-FET Sl would be damaged in the worst case. According to the present invention, however, when the occurrence of short circuit in the load 52 leads the power MOS-FET 52 to the saturation region, MOS-FET S l limits the drain current such that heat generation thereof is restrained.
Consequently, the power MOS-FET of the present invention has a higher load short-circuit withstanding capability than the conventional MO S -FET s .
The prior art has required a protecting circuit for protecting the power MOS-FET S l against overheating and overcurrent so that the power MOS-FET S l can be prevented from being damaged in the occurrence of short circuit in the load 52. However, MOS-FET of the second embodiment necessitates no such dedicated protecting circuit.
Consequently, the system can be rendered small in size and low in cost.
In each of the above-described embodiments, the conduction types in the semiconductor substrate may be changed between the p-type and the n-type.
According to the semiconductor device of the present invention, the ON resistance can be reduced and the source-drain and gate-drain breakdown voltages can be increased in the field effect semiconductor device .
According to the method of the present invention, the semiconductor device having the above-described features can easily be fabricated .
The foregoing description and drawings are merely illustrative of -the principles of the present invention and are not to be construed in a limiting sense. Various changes and modifications will become apparent to those of ordinary skill in the art. All such changes and modifications are seen to fall within the true spirit and scope of the invention as defined by the appended claims.
Claims (5)
1. A vertical MOS-FET with improved breakdown voltages, comprising:
a first layer provided at a deep location in a semiconductor substrate;
a second layer provided at a shallower location than the first layer;
a third layer provided at a shallower location than the second layer and exposed on a surface of the substrate;
a trench extending from the substrate surface through the third and second layers to the first layer, the trench having a side wall and a bottom;
an insulating layer covering the side wall and the bottom of the trench;
a conductor surrounded by the insulating layer and filling the trench; and a fourth layer located in the first layer to cover a boundary between the side wall and the bottom of the trench and vicinities thereof with the insulating layer interposed therebetween;
wherein the first and third layers are of the same conduction type, whereas the second and fourth layers are of a reverse conduction type, and wherein the conductor serves as a gate electrode such that a channel is formed in the second layer.
a first layer provided at a deep location in a semiconductor substrate;
a second layer provided at a shallower location than the first layer;
a third layer provided at a shallower location than the second layer and exposed on a surface of the substrate;
a trench extending from the substrate surface through the third and second layers to the first layer, the trench having a side wall and a bottom;
an insulating layer covering the side wall and the bottom of the trench;
a conductor surrounded by the insulating layer and filling the trench; and a fourth layer located in the first layer to cover a boundary between the side wall and the bottom of the trench and vicinities thereof with the insulating layer interposed therebetween;
wherein the first and third layers are of the same conduction type, whereas the second and fourth layers are of a reverse conduction type, and wherein the conductor serves as a gate electrode such that a channel is formed in the second layer.
2. A vertical MOS-FET according to claim 1, wherein the first layer includes a lower first layer and an upper first layer, wherein the trench extends through the upper first layer to the lower first layer, and wherein the fourth layer is located in the lower first layer.
3. A vertical MOS-FET according to claim 1, wherein a pair of the third layers, a pair of the trenches, and a pair of the fourth layers are formed for the single first layer and the single second layer.
4. A method of fabricating a vertical MOS-FET comprising the steps of:
forming a first layer at a deep location in a semiconductor substrate;
forming a second layer at a shallower location than the first layer;
forming a third layer at a shallower location than the second layer to be exposed on a surface of the substrate;
forming a trench extending from the substrate surface through the third and second layers to the first layer, the trench having a side wall and a bottom;
forming an insulating layer covering the side wall and the bottom of the trench;
forming a fourth layer located in the first layer to cover a boundary between the side wall and the bottom of the trench and vicinities thereof with the insulating layer interposed therebetween; and forming a conductor surrounded by the insulating layer and filling the trench;
wherein the first and third layers are of the same conduction type, whereas the second and fourth layers are of a reverse conduction type, and wherein the conductor serves as a gate electrode such that a channel is formed in the second layer.
forming a first layer at a deep location in a semiconductor substrate;
forming a second layer at a shallower location than the first layer;
forming a third layer at a shallower location than the second layer to be exposed on a surface of the substrate;
forming a trench extending from the substrate surface through the third and second layers to the first layer, the trench having a side wall and a bottom;
forming an insulating layer covering the side wall and the bottom of the trench;
forming a fourth layer located in the first layer to cover a boundary between the side wall and the bottom of the trench and vicinities thereof with the insulating layer interposed therebetween; and forming a conductor surrounded by the insulating layer and filling the trench;
wherein the first and third layers are of the same conduction type, whereas the second and fourth layers are of a reverse conduction type, and wherein the conductor serves as a gate electrode such that a channel is formed in the second layer.
5. The method according to claim 4, wherein the first layer forming step includes a step of forming a lower first layer and an upper first layer over the lower first layer, wherein the trench forming step includes a step of forming the trench so that the same extends through the upper first layer to the lower first layer, and wherein the fourth layer forming step includes a step of introducing impurities via the trench bottom into the lower first layer.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7333422A JPH09181304A (en) | 1995-12-21 | 1995-12-21 | Semiconductor device and its manufacture |
| JP7-333422 | 1995-12-21 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA2193401A1 true CA2193401A1 (en) | 1997-06-22 |
Family
ID=18265940
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002193401A Abandoned CA2193401A1 (en) | 1995-12-21 | 1996-12-18 | Vertical mos-fet with improved breakdown voltages |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPH09181304A (en) |
| CA (1) | CA2193401A1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7229872B2 (en) | 2000-04-04 | 2007-06-12 | International Rectifier Corporation | Low voltage power MOSFET device and process for its manufacture |
| CN117727776A (en) * | 2023-12-19 | 2024-03-19 | 深圳市创飞芯源半导体有限公司 | Groove type MOSFET device and preparation method thereof, electronic equipment and preparation method thereof |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6291298B1 (en) * | 1999-05-25 | 2001-09-18 | Advanced Analogic Technologies, Inc. | Process of manufacturing Trench gate semiconductor device having gate oxide layer with multiple thicknesses |
| US6380569B1 (en) * | 1999-08-10 | 2002-04-30 | Rockwell Science Center, Llc | High power unipolar FET switch |
| US6580123B2 (en) * | 2000-04-04 | 2003-06-17 | International Rectifier Corporation | Low voltage power MOSFET device and process for its manufacture |
| US6674124B2 (en) * | 2001-11-15 | 2004-01-06 | General Semiconductor, Inc. | Trench MOSFET having low gate charge |
| JP4500530B2 (en) * | 2003-11-05 | 2010-07-14 | トヨタ自動車株式会社 | Insulated gate semiconductor device and manufacturing method thereof |
| JP2006344760A (en) * | 2005-06-08 | 2006-12-21 | Sharp Corp | Trench type mosfet and its fabrication process |
| JP6964564B2 (en) * | 2018-07-20 | 2021-11-10 | 三菱電機株式会社 | Semiconductor device |
-
1995
- 1995-12-21 JP JP7333422A patent/JPH09181304A/en active Pending
-
1996
- 1996-12-18 CA CA002193401A patent/CA2193401A1/en not_active Abandoned
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7229872B2 (en) | 2000-04-04 | 2007-06-12 | International Rectifier Corporation | Low voltage power MOSFET device and process for its manufacture |
| US8487368B2 (en) | 2000-04-04 | 2013-07-16 | International Rectifier Corporation | Low voltage power MOSFET device and process for its manufacture |
| CN117727776A (en) * | 2023-12-19 | 2024-03-19 | 深圳市创飞芯源半导体有限公司 | Groove type MOSFET device and preparation method thereof, electronic equipment and preparation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH09181304A (en) | 1997-07-11 |
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