CN117727776A - Groove type MOSFET device and preparation method thereof, electronic equipment and preparation method thereof - Google Patents

Abstract

The invention provides a trench MOSFET device and a preparation method thereof, electronic equipment and a preparation method thereof, comprising the following steps: a first conductive body region disposed on the semiconductor substrate; a second conductive body region disposed on the first conductive body region, wherein the first and second conductive body regions have opposite conductivity types, the second conductive body region including adjacent source and drain regions; the grooves are arranged between the first conductive body region and the adjacent source electrode region at intervals and between the first conductive body region and the drain electrode region, and the depth of each groove is at least one time that of the first conductive body region; and a gate oxide layer formed in the trench; compared with the trench MOSFET in the prior art, the trench MOSFET structure has larger trench depth, can improve breakdown voltage, and is further suitable for low-frequency switch occasions.

Description

Groove type MOSFET device and preparation method thereof, electronic equipment and preparation method thereof

Technical Field

The invention belongs to the field of semiconductor power devices, and particularly relates to a trench MOSFET device, a manufacturing method, electronic equipment and a manufacturing method.

Background

MOS tube is a common semiconductor device, and is widely used in integrated circuits. The MOS transistor has the advantages of high input impedance, low noise, low power consumption and the like, so that the MOS transistor is widely applied to various electronic equipment, on-resistance is an important parameter, the on-resistance and the temperature rise and other performances of the MOS transistor are determined, and the larger the on-resistance is, the larger the loss is, the higher the temperature rise of the MOS transistor is, and therefore, the on-resistance and other parameters of the MOS transistor need to be comprehensively considered when the MOS transistor is selected so as to meet specific application requirements.

In the MOS tube, the on-resistance refers to the resistance encountered when the current passes through the MOS tube in the on state, and the magnitude of the resistance is influenced by various factors, such as the channel length, thickness and the like of the MOS tube, in general, the smaller the on-resistance is, the better the smaller the on-resistance is, because the smaller the on-resistance means smaller energy loss and higher efficiency.

SGT MOSFET power semiconductor devices shield gate trench MOSFET field effect transistors that have much lower on-resistance than trench MOSFETs, but are complex in process requiring high precision equipment and techniques, and therefore this application contemplates a method of reducing the resistance of the epitaxial region of a trench MOSFET.

Disclosure of Invention

Aiming at the problems in the prior art, the invention provides a groove type MOSFET device and a preparation method thereof, which are used for reducing the conduction voltage drop of the groove type MOSFET on the premise of not increasing the manufacturing cost.

In a first aspect, an embodiment of the present invention provides a trench MOSFET device, including:

a first conductive body region disposed on the semiconductor substrate;

a second conductive body region disposed on the first conductive body region, wherein the first and second conductive body regions have opposite conductivity types, the second conductive body region including adjacent source and drain regions;

the grooves are arranged between the first conductive body region and the adjacent source electrode region at intervals, and between the first conductive body region and the drain electrode region, and the distance between the adjacent grooves is at least one time that between the first conductive body region and the adjacent source electrode region; and

and the grid oxide layer is formed in the groove.

Further, the distance between adjacent grooves is 0.3um to 0.7um.

Further, the depth of the groove is 1.2-2 times that of the first conductive body region.

Further, the thickness of the gate oxide layer is 650A-1000A.

Further, the doping concentration of the first conductive body region is 2E15/cm ³ -15E16/cm ³ 。

Further, a first groove array which is arranged along a first direction is arranged between the first conductive body region and the adjacent source region, a second groove array which is arranged along a second direction is arranged between the first conductive body region and the drain region, the first groove array and the second groove array are mutually perpendicular along the first direction and the second direction, and the first groove array and the second groove array are arranged at intervals.

Further, a plurality of grooves which are arranged at intervals and an annular groove group which is arranged at intervals in a surrounding manner are arranged between the first conductive body region and the adjacent source electrode region and between the first conductive body region and the drain electrode region, and the annular groove group comprises a plurality of annular grooves with sequentially increasing inner diameters; the annular grooves comprise at least two groups of strip grooves which are parallel to each other and arc grooves connected to two ends of the adjacent strip grooves.

In a second aspect, the embodiment of the present invention provides a method for manufacturing a trench MOSFET device, including the steps of:

growing a first conductive body region and a second conductive body region on the semiconductor substrate, and etching to form a groove between the first conductive body region and an adjacent source region and between the first conductive body region and a drain region;

growing a gate oxide layer with a preset thickness on the groove;

POLY deposition and etching are carried out in the groove, so that the groove is filled with POLY;

performing Body injection and diffusion of preset concentration to the gate oxide layer;

and sequentially completing source injection and diffusion, depositing an isolation layer, contact etching and injection, and metal deposition and etching to complete the preparation of the trench MOSFET structure.

In a third aspect, an embodiment of the present invention provides an electronic device, including the trench MOSFET device described above.

In a fourth aspect, the present invention provides a method for manufacturing an electronic device, including the method for manufacturing a trench MOSFET described above.

Additional optional features and technical effects of embodiments of the invention are described in part below and in part will be apparent from reading the disclosure herein.

Compared with the prior art, the invention has the following beneficial technical effects:

the invention provides a groove type MOSFET device and a preparation method thereof, comprising the following steps: a first conductive body region disposed on the semiconductor substrate; a second conductive body region disposed on the first conductive body region, wherein the first and second conductive body regions have opposite conductivity types, the second conductive body region including adjacent source and drain regions; the grooves are arranged between the first conductive body region and the adjacent source electrode region at intervals and between the first conductive body region and the drain electrode region, and the depth of each groove is at least one time that of the first conductive body region; and a gate oxide layer formed in the trench; compared with the trench MOSFET in the prior art, the trench MOSFET structure has larger trench depth, can improve breakdown voltage, and further can be suitable for low-frequency switch occasions such as load switches, and larger input capacitance can also improve ESD tolerance of a device grid and improve the EMI level, so that the trench MOSFET structure provided by the application is suitable for application fields with high requirements on ESD tolerance and EMI.

Drawings

Embodiments of the present invention will hereinafter be described in conjunction with the appended drawings, wherein like or similar reference numerals denote like or similar elements, and wherein:

FIG. 1 shows a schematic diagram of trench etching in an embodiment of the invention;

FIG. 2 is a schematic diagram of a grown gate oxide in an embodiment of the invention;

FIG. 3 shows a schematic diagram of Poly deposition and etching in an embodiment of the present invention;

FIG. 4 shows a schematic diagram of Body implantation and diffusion in an embodiment of the invention;

FIG. 5 illustrates a schematic diagram of source implant and diffusion in an embodiment of the present invention;

FIG. 6 shows a schematic diagram of deposition of an isolation layer in an embodiment of the invention;

FIG. 7 shows a schematic view of contact etch and implant in an embodiment of the invention;

FIG. 8 is a schematic diagram of metal deposition and etching in an embodiment of the invention;

FIG. 9 is a schematic diagram of a trench arrangement in an embodiment of the invention;

FIG. 10 is a schematic diagram of another trench arrangement in an embodiment of the invention.

Detailed Description

The present invention will be described in further detail with reference to the following detailed description and the accompanying drawings, in order to make the objects, technical solutions and advantages of the present invention more apparent. The exemplary embodiments of the present invention and the descriptions thereof are used herein to explain the present invention, but are not intended to limit the invention.

The term "comprising" and variations thereof as used herein means open ended, i.e., "including but not limited to. The term "or" means "and/or" unless specifically stated otherwise. The term "based on" means "based at least in part on". The terms "one example embodiment" and "one embodiment" mean "at least one example embodiment. The term "another embodiment" means "at least one additional embodiment". The terms "first," "second," and the like, may refer to different or the same object. Other explicit and implicit definitions are also possible below.

The invention provides

Fig. 1 shows a trench MSOFET device according to an embodiment of the present invention, as shown in fig. 1, comprising:

a first conductive body region disposed on the semiconductor substrate;

a second conductive body region disposed on the first conductive body region, wherein the first and second conductive body regions have opposite conductivity types, the second conductive body region including adjacent source and drain regions;

the grooves are arranged between the first conductive body region and the adjacent source electrode region at intervals and between the first conductive body region and the drain electrode region, and the depth of each groove is at least one time that of the first conductive body region; and

and the grid oxide layer is formed in the groove.

It should be noted that the first conductive body region and the second conductive body region may be interchanged and form a P-channel mos tube and an N-channel mos tube; meanwhile, the gate oxide layer also covers the surfaces of the spacing layers between the grooves.

In this embodiment, the pitch between adjacent trenches is preferably 0.3um to 0.7um, and it should be noted that the typical trench pitch in the related art is 0.5um to 0.8um, and the trench pitch is smaller in this application, because a larger trench pitch will result in a decrease of the breakdown voltage BV, i.e. the magnitude of the trench pitch is inversely proportional to the breakdown voltage BV, but a too small trench pitch will result in a problem of higher cost and complex process.

It should be further noted that, in this embodiment, the trench MOSFET structure termination design in this application requires that the trench spacing of the termination region be equal to or less than 100% -50% of the trench spacing in the prior art.

In one embodiment, the trench has a depth 1.2-2 times the depth of the first conductive body region;

an embodiment is provided for the depth of the trench, wherein when the thickness of the gate oxide layer is 800A and the depth of the trench is 1.3um, the breakdown voltage BV is 25V; in the prior art, the thickness of the gate oxide layer is 800A, the depth of the trench is generally 1.0um-1.2um, and the breakdown voltage BV is generally 21V-23V;

an embodiment is provided for the depth of the trench, wherein when the thickness of the gate oxide layer is 850A and the depth of the trench is 1.5um, the breakdown voltage BV is 30V; in the prior art, the thickness of the gate oxide layer is 850A, the depth of the trench is generally 1.1um-1.3um, and the breakdown voltage BV is generally 22V-27V;

thus, it can be seen from the above embodiments that by varying the single variable trench depth, the breakdown voltage BV can be increased.

In one embodiment, the gate oxide layer has a thickness of 650A-1000A; the gate oxide layer is a very thin silicon oxide film, and the gate and the channel charge are separated by forming an insulating layer on the surface of the gate, so that the gate and the channel can be effectively isolated by the oxide layer, and the leakage of the charge and the leakage of current are prevented, thereby improving the insulating property and the switching speed of the MOSFET; in the prior art, the thickness of the gate oxide layer is typically between tens of nanometers and hundreds of nanometers, and the trench MOSFET structure in this embodiment has a higher breakdown voltage by increasing the thickness of the gate oxide layer.

In one embodiment, the doping concentration of the first conductive body region is 2E15/cm ³ -15E16/cm ³ 。

It should be noted that the doping concentration of the epitaxial layer can directly determine important electrical parameters such as specific on-resistance, blocking voltage, etc. of the subsequent devices, which are critical to the performance of the power device, for example, in power systems and power supply applications, the specific on-resistance and blocking voltage affect the efficiency and stable operation of the device.

In an embodiment, fig. 10 is a schematic diagram showing a trench arrangement manner in an embodiment of the present invention, as shown in the drawing, a first trench array arranged along a first direction is disposed between the first conductive body region and the adjacent source region, a second trench array arranged along a second direction is disposed between the first conductive body region and the drain region, the first and second directions are perpendicular to each other, and a space is provided between the first trench array and the second trench array.

It should be noted that, the wafer is very easy to generate warpage in the process of preparation, when we prepare the MOSFET with relatively deep trench depth or prepare the MOSFET with relatively high unit cell density in unit area, the warpage effect of the wafer is a very unfavorable factor and also easily causes the reduction of the yield of the product; therefore, the structure can further improve the preparation yield of the trench MOSFET.

It should be further noted that, in this embodiment, the adjacent trench edges have a smaller distance from the adjacent trench edges, and have deeper trenches, and meanwhile, the thicknesses of the gate oxide layers grown on the trench surfaces and the epitaxial layers are both larger, so as to improve the breakdown voltage of the trench MOSFET in this embodiment.

In one embodiment, fig. 10 is a schematic diagram showing another trench arrangement mode in the embodiment of the present invention, where a plurality of trenches arranged at intervals are disposed between the first conductive body region and the adjacent source region and between the first conductive body region and the drain region, and an annular trench group surrounding the plurality of trenches arranged at intervals is provided, and the annular trench group includes a plurality of annular trenches with sequentially increasing inner diameters; further, the annular groove comprises at least two groups of mutually parallel strip grooves and arc grooves connected to two ends of the adjacent strip grooves.

In this embodiment, the adjacent trench edges have a smaller distance from the adjacent trench edges, and have deeper trenches, and meanwhile, the thicknesses of the gate oxide layers grown on the trench surfaces and the epitaxial layers are larger, so as to improve the breakdown voltage of the trench MOSFET in this embodiment.

In another aspect, the present invention provides a method for fabricating a trench MOSFET device, comprising the steps of:

FIG. 1 is a schematic diagram of a trench etching process in an embodiment of the present invention, wherein an epitaxial layer is grown on a semiconductor substrate, and trenches are etched between a first conductive body region and an adjacent source region, and between the first conductive body region and a drain region, as shown in FIG. 1; it should be noted that, in this embodiment, any adjacent trench edge has a smaller distance from the adjacent trench edge, and has a deeper trench;

FIG. 2 is a schematic diagram showing the growth of a gate oxide layer according to an embodiment of the present invention, wherein a gate oxide layer of a predetermined thickness is grown on the trench as shown in FIG. 2; in this embodiment, the thickness of the gate oxide layer is preferably 650A-1000A;

FIG. 3 shows a schematic diagram of Poly deposition and etching in an embodiment of the present invention; POLY deposition and etching are carried out in the groove, so that POLY fills the groove; specifically, POLY deposition and etching are used to fabricate polysilicon gate electrodes in transistors, and this step includes two parts, namely deposition and etching, wherein POLY deposition is a process of depositing polysilicon on a silicon wafer, and polysilicon gate electrodes are commonly used in Field Effect Transistors (FETs) as devices, and after depositing polysilicon, a heat treatment is required to relieve stress and form a polysilicon film; POLY etching is a process of removing redundant polysilicon by dry or wet etching after polysilicon gate deposition is completed, wherein the etching aims to isolate a polysilicon gate from a source electrode and a drain electrode, and simultaneously keep the shape and the size of the gate, which is critical to the performance and the stability of a device; through the POLY deposition and etching process, the polysilicon gate with good performance can be manufactured, thereby realizing miniaturization and high efficiency of the semiconductor device.

Fig. 4 shows a schematic diagram of Body implantation and diffusion to the gate oxide layer in an embodiment of the present invention, as shown in fig. 4.

It should be further noted that Body implantation is a process of implanting impurity ions into a gate electrode of a semiconductor transistor, and this process is generally implemented using an ion implantation or dry deposition method, and main effects of Body implantation include: the threshold voltage is adjusted, the charge state of the semiconductor surface can be changed by injecting ions of different types (such as boron, phosphorus and the like), so that the threshold voltage of a device is controlled, the threshold voltage is a key parameter of the on and off states of a transistor, the threshold voltage can be effectively regulated and controlled by adjusting the dosage and the energy of Body injection, and meanwhile, the performance parameters of the transistor, such as switching speed, transconductance and the like, can be improved by optimizing the dosage and the energy of Body injection, for example, the driving capability of the transistor can be enhanced by properly increasing the dosage of Body injection, and the switching speed can be improved; and secondly, the Body injection can reduce the hot carrier effect and the secondary breakdown effect in the device, so that the reliability of the device is improved, the hot carrier effect can cause excessive heat generated by electrons in the transistor, the secondary breakdown effect can cause the failure of the transistor under the over-high voltage, and the occurrence of the problems can be reduced through the Body injection.

Body diffusion can form a PN junction: PN junctions (junction areas between positive and negative semiconductors) which are key structures for realizing voltage amplification and current control functions, such as diodes, transistors and the like, can be formed on a semiconductor chip through a diffusion process; the Body diffusion can optimize device performance, specifically, by controlling the concentration and depth of the diffusion, the performance of the PN junction can be optimized, for example, reducing the series resistance, improving the frequency response, etc., for example, in a transistor, a PN junction with a proper concentration profile can be formed by the diffusion process, thereby improving the device performance, while the reliability can be improved, specifically, the diffusion process can reduce the influence of mechanical stress and thermal stress on the device, thereby improving the device reliability. During semiconductor fabrication, mechanical and thermal stresses may lead to material defects and performance degradation. By the diffusion process, the occurrence of these problems can be alleviated.

Fig. 5 is a schematic diagram showing source implantation and diffusion in an embodiment of the present invention, as shown in fig. 5, the source implantation is used to form a source, and a PN junction may be formed on a semiconductor chip through a source diffusion process;

FIG. 6 shows a schematic diagram of depositing an isolation layer in the embodiment of the invention, as shown in FIG. 6, the deposition of the isolation layer mainly forms a layer of film on a wafer, and the layer of film can effectively protect circuit elements from external environments, such as mechanical damage, chemical corrosion and the like, and meanwhile, the deposition of the isolation layer can also be used as a dielectric material to effectively isolate the circuit elements so as to avoid the problems of circuit short circuit, mutual interference and the like; in the integrated circuit manufacturing process, the formation of the deposition isolation layer generally adopts Physical Vapor Deposition (PVD) or Chemical Vapor Deposition (CVD) and other methods; the PVD method mainly comprises the steps of depositing materials on the surface of a wafer through physical processes such as evaporation or sputtering under high vacuum; the CVD method forms a thin film on the wafer surface by chemical reaction.

FIG. 7 is a schematic diagram of Contact etching and implantation in an embodiment of the present invention, as shown in FIG. 7, contact etching is a key step for forming a Contact hole in semiconductor manufacturing, the Contact hole is an interface for connecting a transistor and an external circuit, and a chemical or physical method is used to remove material on the surface of the semiconductor during Contact etching to form a Contact hole with a specific shape and size, wherein the position and size of the Contact hole depend on the design and process parameters of a mask; while the purpose of the Contact implant is to form a highly doped region at the bottom of the Contact hole to establish good electrical Contact between the transistor and external circuitry, where the type and dosage of the implanted impurities depend on the process design and the target device characteristics.

FIG. 8 is a schematic diagram of Metal deposition and etching in an embodiment of the present invention, and as shown in FIG. 8, metal deposition is a key step for forming Metal lines in semiconductor manufacturing. The Metal wire is a conductive material for connecting the transistor and an external circuit, and the Metal material is deposited on the semiconductor surface by using a chemical or physical method in the Metal deposition process; metal etching is a key step in semiconductor fabrication for forming Metal connection points, which are conductive contact points for connecting transistors to external circuits, and chemical or physical methods are used to remove portions of Metal material on the semiconductor surface during Metal etching to form Metal connection points having a specific shape and size.

In another aspect, the present invention provides an electronic device comprising a trench MOSFET device as described above.

In another aspect, the present invention provides a method for manufacturing an electronic device, including the method for manufacturing a trench MOSFET described above.

Various embodiments of the invention are described herein, but for brevity, description of each embodiment is not exhaustive and features or parts of the same or similar between each embodiment may be omitted. Herein, "one embodiment," "some embodiments," "example," "specific example," or "some examples" means that it is applicable to at least one embodiment or example, but not all embodiments, according to the present invention. The above terms are not necessarily meant to refer to the same embodiment or example. Those skilled in the art may combine and combine the features of the different embodiments or examples described in this specification and of the different embodiments or examples without contradiction.

The exemplary systems and methods of the present invention have been particularly shown and described with reference to the foregoing embodiments, which are merely examples of the best modes for carrying out the systems and methods. It will be appreciated by those skilled in the art that various changes may be made to the embodiments of the systems and methods described herein in practicing the systems and/or methods without departing from the spirit and scope of the invention as defined in the following claims.

Claims (8)

1. A trench MOSFET device, comprising:

a first conductive body region disposed on the semiconductor substrate;

a second conductive body region disposed on the first conductive body region, wherein the first and second conductive body regions have opposite conductivity types, the second conductive body region including adjacent source and drain regions;

the grooves are arranged between the first conductive body region and the adjacent source electrode region at intervals and between the first conductive body region and the drain electrode region, and the depth of each groove is at least one time that of the first conductive body region; and

and the grid oxide layer is formed in the groove.

2. The trench MOSFET device of claim 1, wherein said gate oxide layer has a thickness of 650A-1000A.

3. The trench MOSFET device of claim 1, wherein said first conductive body region has an doping concentration of 2E15/cm ³ -15E16/cm ³ 。

4. The trench MOSFET device of claim 1, wherein a first trench array is disposed between said first conductive body region and adjacent source regions in a first direction, a second trench array is disposed between said first conductive body region and drain region in a second direction, and wherein said first and second directions are perpendicular to each other, and wherein said first trench array and second trench array are spaced apart.

5. The trench MOSFET device of claim 1, wherein a plurality of trenches are disposed between said first conductive body region and adjacent source regions and between said first conductive body region and drain regions in spaced relation, and an annular trench set surrounding said plurality of trenches in spaced relation, said annular trench set comprising a plurality of annular trenches having sequentially increasing inner diameters;

the annular grooves comprise at least two groups of strip grooves which are parallel to each other and arc grooves connected to two ends of the adjacent strip grooves.

6. A method for manufacturing a trench MOSFET device, characterized in that it is based on a trench MOSFET structure according to any of claims 1-5, comprising the steps of:

growing a first conductive body region and a second conductive body region on the semiconductor substrate, and etching to form a groove between the first conductive body region and an adjacent source region and between the first conductive body region and a drain region;

growing a gate oxide layer with a preset thickness on the groove;

POLY deposition and etching are carried out in the groove, so that the groove is filled with the POLY;

performing Body injection and diffusion of preset concentration to the gate oxide layer;

and sequentially completing source injection and diffusion, depositing an isolation layer, contact etching and injection, and metal deposition and etching to complete the preparation of the trench MOSFET structure.

7. An electronic device comprising the trench MOSFET device of any one of claims 1-5.

8. A method of manufacturing an electronic device comprising the method of manufacturing a trench MOSFET of claim 6.