CN116314249A - SGT power device - Google Patents

SGT power device Download PDF

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Publication number
CN116314249A
CN116314249A CN202111569970.XA CN202111569970A CN116314249A CN 116314249 A CN116314249 A CN 116314249A CN 202111569970 A CN202111569970 A CN 202111569970A CN 116314249 A CN116314249 A CN 116314249A
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China
Prior art keywords
groove
contact hole
trench
polysilicon
power device
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CN202111569970.XA
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Chinese (zh)
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曾大杰
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Nantong Shangyangtong Integrated Circuit Co ltd
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Nantong Shangyangtong Integrated Circuit Co ltd
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Priority to CN202111569970.XA priority Critical patent/CN116314249A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41741—Source or drain electrodes for field effect devices for vertical or pseudo-vertical devices

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

The invention discloses an SGT power device, shielding polysilicon is formed in a groove, the groove is divided into first to fourth grooves on a top view surface, and an arrangement structure comprises: a plurality of first grooves and second grooves which are mutually perpendicular are distributed in the active area, the third groove is of an annular structure, and the active area is located in an area surrounded by the inner side surface of the third groove; the fourth trench is surrounded in a terminal region outside the third trench; the top of the fourth groove is provided with a first contact hole for connecting the shielding polysilicon at the bottom to the drain electrode; the top of the third groove is provided with a second contact hole for connecting the shielding polysilicon at the bottom to the source electrode; a third contact hole connected to the drain electrode is formed on the surface of the semiconductor substrate outside the outer side face of the fourth groove, a first interval is arranged between the fourth groove and the third groove, and the first interval is more than half of the longitudinal thickness of the drift region of the SGT power device. The invention can reduce the stress of the device and thereby prevent the process problems caused by the stress of the device.

Description

SGT power device
Technical Field
The present invention relates to semiconductor integrated circuits, and more particularly to SGT power devices.
Background
SGT power devices, such as SGT MOSFETs, incorporate a source field plate, i.e., a shield polysilicon connected to the source, in the longitudinal direction of the device, as compared to Trench (Trench) MOSFETs. The source electrode field plate and the drift region are transversely exhausted, so that the doping concentration of the drift region can be greatly improved under the condition that the breakdown voltage of the device is not reduced, and extremely low specific on-resistance is realized. In addition, SGT MOSFETs switch faster than Trench MOSFETs because the gate-drain coupling capacitance (Cgd) is lower. Therefore, in more and more occasions, SGT MOSFETs are beginning to replace the Trench MOSFETs.
As shown in fig. 1, a schematic structure diagram of a device cell structure of a first prior art SGT MOSFET; a first prior art SGT MOSFET is formed from a plurality of device cell structures in a cell region in parallel, each of the device cell structures comprising:
a first gate structure formed in the first trench, comprising a shield polysilicon 103 and a polysilicon gate 108 stacked together; the first trench is formed in the first epitaxial layer 102 doped with the first conductivity type, a shielding dielectric layer 104 is isolated between the shielding polysilicon 103 and the first epitaxial layer 102, a gate dielectric layer 112 is isolated between the polysilicon gate 108 and the first epitaxial layer 102, and an inter-polysilicon dielectric layer 107 is isolated between the shielding polysilicon 103 and the polysilicon gate 108.
The shielding polysilicon 103 and the polysilicon gate 108 are in an upper-lower stacked structure.
A drift region 102, which is also denoted here by reference 2, is formed by said first epitaxial layer 102.
And a body region 105 composed of a second conductivity type doped region formed on the surface of the drift region 102.
A source region 109, which is formed on the surface of the body region 105 and is a heavily doped region of the first conductivity type.
And a drain region composed of a heavily doped region of the first conductivity type formed on the back surface of the drift region 102. The first epitaxial layer 102 is generally formed on the surface of the semiconductor substrate 101, and the drain region is formed after the back surface of the semiconductor substrate 101 is thinned, and the semiconductor substrate 101 can directly adopt a heavily doped structure of the first conductivity type, so that the drain region can be directly formed after the semiconductor substrate 101 is thinned; alternatively, the drain region is formed by ion implantation of the first conductivity type heavily doped after thinning the semiconductor substrate 101. The semiconductor substrate 101 is typically a silicon substrate, and the first epitaxial layer 102 is typically a silicon epitaxial layer.
The bottom of the first trench passes through the body region 105, the source region 109 is self-aligned to the surface of the body region 105 formed on the side of the polysilicon gate 108, the depth of the polysilicon gate 108 is greater than the depth of the body region 105 and the surface of the body region 105 laterally covered by the polysilicon gate 108 is used to form a channel.
The polysilicon gate 108 is connected to a gate electrode composed of a front metal layer 111 through a contact hole 106 penetrating an interlayer film 110.
The source region 109 and the body region 105 are connected to a source electrode composed of a front side metal layer 111 through a contact hole 106.
The back surface of the drain region is in contact with and is formed into a drain by the back surface metal layer.
An N-type trench MOSFET is illustrated. The first epitaxial layer 102 is typically formed on a heavily doped N-type semiconductor substrate 101, such as a silicon substrate, and the semiconductor substrate 101 forms a drain region after thinning. To reduce the back-diffusion of the semiconductor substrate 101, an arsenical substrate, i.e., an Arsenic doped semiconductor substrate 101, is typically selected. But because the lowest resistivity that can be achieved in the current technology of the Phosphorus substrate, i.e., the Phosphorus doped semiconductor substrate 101, is lower than that of the arsenical substrate. So that in low voltage devices where the substrate resistance ratio is high, such as 40V or less, a Phosphorus substrate is also often used. The thinner the substrate, the better the heat dissipation to the device, and the more significant the reduction of the substrate resistance.
The shielding polysilicon 103 can realize lateral depletion with the drift region 102 through the shielding dielectric layer 104, i.e. field oxide, so that the doping concentration of the drift region 102 can be significantly improved compared with the existing trench MOSFET without shielding gate.
The shield dielectric layer 104 needs to withstand the breakdown voltage of the device, so the higher the breakdown voltage required by the device, the thicker the thickness of the shield dielectric layer 104. In a practical process, the shield polysilicon 103 is typically composed of heavily doped polysilicon, as is the polysilicon gate 108.
FIG. 2 is a schematic diagram of a device cell structure of a second prior art SGT MOSFET; the device cell structure of the prior second SGT MOSFET differs from the device cell structure of the prior first SGT MOSFET in that:
the shielding polysilicon 103a and the polysilicon gate 108a are left and right stacked structures, and a is added to marks of corresponding structures in gate structures corresponding to the left and right stacked structures, for example, the gate dielectric layer is denoted by a mark 112a, the shielding dielectric layer is denoted by a mark 104a, and the inter-polysilicon dielectric layer is denoted by a mark 107 a.
The prior art first type SGT MOSFET and prior art second type SGT MOSFET are simply referred to as "up-down" structure and "side-to-side" structure, respectively, and the advantages and disadvantages of these two structures are as follows:
The process implementation of the "up and down" structure is more complex because the shield polysilicon cannot be directly connected to the contact hole, requiring additional photolithography tools and process steps.
The left-right structure process is simple to realize, and no special complex process steps are needed. All structures, including polysilicon gates and shield polysilicon, are on the surface of the semiconductor substrate 101, which may be conveniently and directly connected. The overlap area between the polysilicon gate and the shielding polysilicon is larger in the left-right structure than in the up-down structure, so that the input capacitance is also larger.
The SGT MOSFET is more difficult to implement than the Trench MOSFET, and more importantly, the higher the breakdown voltage that needs to be, the deeper the shield polysilicon is in the drift region, and the thicker the shield dielectric layer, e.g., oxide layer, that is isolated from the drift region. This not only makes the process very difficult to implement, but also, more importantly, fills the drift region with a large amount of oxide layers, which can also cause a large amount of stress due to mismatch of thermal expansion coefficients. This stress causes wafer warpage, affecting the alignment of lithography, resulting in reduced alignment accuracy; more serious, if the warpage is serious, the photolithography machine cannot work, so that the subsequent wafer flow cannot be performed.
Disclosure of Invention
The technical problem to be solved by the invention is to provide an SGT power device which can reduce the stress of the device and thereby prevent the technical problem caused by the stress of the device.
In order to solve the technical problems, the shielding polysilicon of the SGT power device is formed in a groove, the groove is formed in a semiconductor substrate, a shielding medium layer is arranged between the shielding polysilicon and the groove at intervals, and the mismatch of the depth of the groove and the thermal expansion coefficients of the shielding medium layer and the semiconductor substrate material can generate stress in the semiconductor substrate.
On a top view, the grooves are divided into a first groove, a second groove, a third groove and a fourth groove, and an arrangement structure formed by the grooves comprises:
the first trenches and the second trenches are distributed in the active region, each of the first trenches and the second trenches is in a strip-shaped structure, the first trenches are arranged in parallel, the second trenches are arranged in parallel, the first trenches and the second trenches are perpendicular to each other, and stress in the semiconductor substrate is prevented from being concentrated in one direction and reduced by the perpendicular arrangement of the first trenches and the second trenches.
The third groove is of an annular structure, the active region is located in a region surrounded by the inner side face of the third groove, and the outer side face of the third groove is a terminal region.
The fourth groove is located in the terminal area, is in an annular structure and surrounds the outer side of the third groove.
A first contact hole is arranged in a partial area of the annular structure of the fourth groove, the bottom of the first contact hole is connected with the shielding polycrystalline silicon in the fourth groove, and the top of the first contact hole is connected to the drain electrode.
A second contact hole is arranged in a partial area of the annular structure of the third groove, the bottom of the second contact hole is connected with the shielding polycrystalline silicon in the third groove, and the top of the second contact hole is connected to the source electrode.
A third contact hole is formed in the surface of the semiconductor substrate outside the outer side surface of the fourth trench, and the top of the third contact hole is connected to the drain electrode.
A first interval is arranged between the inner side surface of the fourth groove and the outer side surface of the third groove, and the first interval is more than half of the longitudinal thickness of the drift region of the SGT power device so as to realize pressure resistance between the third groove and the fourth groove.
The ratio of the occupied area of each first groove to the occupied area of each second groove in the active region is adjusted according to layout requirements under the condition that the stress in the semiconductor substrate is reduced below a required value.
In a further improvement, a ratio of a occupied area of each first trench to a occupied area of each second trench in the active region is 1:1.
in the active region, a plurality of adjacent first grooves are arranged in parallel to form a first splicing block, and a plurality of adjacent second grooves are arranged in parallel to form a second splicing block.
The number of the first splicing blocks is more than one; the number of the second splicing blocks is more than one.
The improvement is that the annular structure of the third groove is a closed ring, and the annular structure of the third groove is a rectangular ring with four rounded corners.
In a further improvement, each of the first trenches, each of the second trenches, and each of the third trenches are connected together such that each of the first trenches and each of the second trenches in the active area are in a closed loop structure as a whole, and the shield polysilicon in each of the first trenches and each of the second trenches and the shield polysilicon in the third trenches are connected to the source electrode through the second contact hole at the top of the third trench.
A fourth contact hole is formed at the top of the selected area of each first groove, the bottom of the fourth contact hole is connected with the shielding polysilicon in the first groove, and the top of the fourth contact hole is connected with the source electrode;
a fifth contact hole is formed at the top of the selected region of each second trench, the bottom of the fifth contact hole is connected with the shielding polysilicon in the second trench, and the top of the fifth contact hole is connected with the source electrode.
The further improvement is that two ends of each first groove are spaced from the adjacent third groove or second groove, and two ends of each second groove are spaced from the adjacent third groove or first groove, so that each first groove and each second groove in the active area are in an open-loop structure;
forming a fourth contact hole on the top of the selected area of each first groove, wherein the bottom of the fourth contact hole is connected with the shielding polysilicon in the first groove, and the top of the fourth contact hole is connected to the source electrode;
a fifth contact hole is formed at the top of the selected region of each second trench, the bottom of the fifth contact hole is connected with the shielding polysilicon in the second trench, and the top of the fifth contact hole is connected with the source electrode.
A further improvement is that a space is reserved between one end of each first groove and the adjacent third groove or the second groove, the other end of each first groove is communicated with the adjacent third groove or the second groove, a space is reserved between one end of each second groove and the adjacent third groove or the first groove, and the other end of each second groove is communicated with the adjacent third groove or the first groove, so that each first groove and each second groove in the active area are in a semi-open and semi-closed structure;
the shield polysilicon in each of the first trenches and each of the second trenches and the shield polysilicon in the third trenches are conductive and connected to the source electrode through the second contact hole at the top of the third trench.
A fourth contact hole is formed at the top of the selected area of each first groove, the bottom of the fourth contact hole is connected with the shielding polysilicon in the first groove, and the top of the fourth contact hole is connected with the source electrode;
a fifth contact hole is formed at the top of the selected region of each second trench, the bottom of the fifth contact hole is connected with the shielding polysilicon in the second trench, and the top of the fifth contact hole is connected with the source electrode.
The ring structure of the fourth groove is a closed ring; the annular structure of the fourth groove is a rectangular ring with four rounded corners.
A further improvement is that the fourth groove and the third groove comprise more than one fifth groove with annular structures; the annular structure of the fifth groove is a closed ring; the annular structure of the fifth groove is a rectangular ring with four rounded corners.
A further improvement is that each fifth groove is a floating structure; alternatively, a sixth contact hole is provided in a partial region of the annular structure of the fifth trench, a bottom of the sixth contact hole is connected to the shielding polysilicon in the fifth trench, and a top of the sixth contact hole is connected to the source electrode.
The third contact hole is in a strip line structure and is positioned outside more than one side of the rectangular ring of the fourth groove;
or, the third contact hole is in an annular structure surrounding the periphery of the fourth groove.
In a further improvement, a first epitaxial layer is formed on the semiconductor substrate, and each of the trenches is formed in the first epitaxial layer.
A further improvement wherein said SGT power device further includes a polysilicon gate in said active region;
the polysilicon gate is a planar gate, the polysilicon gate is positioned on the surface of the semiconductor substrate outside the first groove and the second groove, and a gate dielectric layer is arranged between the polysilicon gate and the semiconductor substrate at intervals;
or the polysilicon gate is a trench gate, the polysilicon gate is formed in a gate trench outside the first trench and the second trench, the depth of the gate trench is shallower than that of the trench, and a gate dielectric layer is arranged between the polysilicon gate and the side surface of the gate trench at intervals;
or the polysilicon gates are formed in the first grooves and the second grooves, a gate dielectric layer is arranged between the polysilicon gates and the side surfaces of the corresponding grooves at intervals, a polysilicon inter-dielectric layer is arranged between the polysilicon gates and the shielding polysilicon at intervals, a grid structure is formed by overlapping the shielding dielectric layer, the shielding polysilicon, the gate dielectric layer, the polysilicon inter-dielectric layer and the polysilicon gates, the grid structure is of an up-down structure, and the polysilicon gates are positioned at the top of the shielding polysilicon; or the grid structure is a left-right structure, and the polysilicon gate is positioned in the top areas at the left side and the right side of the shielding polysilicon.
The method is further improved in that the width of the third groove is larger than or equal to the width of the second contact hole plus the alignment precision of the second contact hole by 2 times, and the width of the fourth groove is larger than or equal to the width of the first contact hole plus the alignment precision of the first contact hole by 2 times.
In a further improvement, the widths of the first contact hole and the second contact hole are equal, and the width of the third groove is equal to the width of the fourth groove.
In a further improvement, the width of each first groove is equal to the width of each second groove and is smaller than or equal to the width of the third groove.
The top of each polysilicon gate is connected to a gate pad (pad) formed by patterning the front metal layer through a seventh contact hole;
an outer side surface of a section of the third trench surrounds the gate pad in a top view, so that the gate pad is located outside the active region.
The invention particularly sets the arrangement structure of the grooves provided with the shielding polysilicon, the third groove surrounds and defines an active area, the first groove and the second groove which are mutually perpendicular are arranged in the active area, and the stress in the semiconductor substrate is prevented from being concentrated in one direction and thus the stress in the semiconductor substrate is reduced through the vertical arrangement of the first groove and the second groove.
A fourth groove is formed on the outer side of the third groove, the shielding polysilicon in the fourth groove and the surface of the semiconductor substrate outside the fourth groove can form a drain electrode connected with the contact hole, and the shielding polysilicon in the third groove is connected with the source electrode through the corresponding contact hole, namely the second contact hole, so that the structure can well protect a terminal outside an active area; meanwhile, the third groove and the fourth groove are of annular structures, the annular structures are also beneficial to stress dispersion of the semiconductor substrate, and finally the stress of the semiconductor substrate can be further reduced.
Therefore, the trench arrangement of the active region and the termination region can well meet the performance requirements of devices, can reduce the stress of the semiconductor substrate, can prevent the production of technical problems caused by the stress of the devices, for example, can prevent wafers formed by the semiconductor substrate from warping in the technical process, can prevent the influence of wafer warping on the alignment process from improving the alignment precision, and can further prevent serious wafer warping which can not be subjected to photoetching by a photoetching machine.
Drawings
The invention is described in further detail below with reference to the attached drawings and detailed description:
FIG. 1 is a schematic diagram of a device cell structure of a prior art first SGT MOSFET;
FIG. 2 is a schematic diagram of a device cell structure of a second prior art SGT MOSFET;
FIG. 3 is a first trench layout of an SGT power device according to an embodiment of the present invention;
FIG. 4 is a second trench layout of an SGT power device according to an embodiment of the present invention;
FIG. 5 is a third trench layout of an SGT power device according to an embodiment of the present invention;
FIG. 6 is a fourth trench layout of an SGT power device according to an embodiment of the present invention;
FIG. 7 is a fifth trench layout of an SGT power device according to an embodiment of the present invention.
Detailed Description
As shown in FIG. 3, a first trench layout of an SGT power device according to an embodiment of the present invention; FIG. 4 shows a second trench layout of an SGT power device according to an embodiment of the present invention; FIG. 5 shows a third trench layout of an SGT power device according to an embodiment of the present invention; FIG. 6 shows a fourth trench layout of an SGT power device according to an embodiment of the present invention; FIG. 7 shows a fifth trench layout of an SGT power device according to an embodiment of the present invention; in the SGT power device of the embodiment of the present invention, the shielding polysilicon is formed in a trench, the trench is formed in a semiconductor substrate, a shielding dielectric layer is spaced between the shielding polysilicon and the trench, and a mismatch between the depth of the trench and the thermal expansion coefficients of the shielding dielectric layer and the semiconductor substrate material may generate stress in the semiconductor substrate. In the embodiment of the invention, the SGT power device is an SGT MOSFET.
In a top view, the grooves are divided into a first groove 1c, a second groove 1d, a third groove 1b and a fourth groove 1a, and an arrangement structure formed by the grooves comprises:
a plurality of first trenches 1c and a plurality of second trenches 1d are distributed in the active region, the first trenches 1c and the second trenches 1d are each in a stripe-shaped structure, the first trenches 1c are arranged in parallel with each other, the second trenches 1d are arranged in parallel with each other, the first trenches 1c and the second trenches 1d are perpendicular to each other, and stress concentration in the semiconductor substrate in one direction is avoided and stress in the semiconductor substrate is thereby reduced by the perpendicular arrangement of the first trenches 1c and the second trenches 1 d.
The third groove 1b is in an annular structure, the active region is located in a region surrounded by the inner side surface of the third groove 1b, and the outer side surface of the third groove 1b is a terminal region.
The fourth groove 1a is located in the terminal area, and the fourth groove 1a is in a ring-shaped structure and surrounds the outer side of the third groove 1 b.
A first contact hole 2a is provided in a partial region of the annular structure of the fourth trench 1a, a bottom of the first contact hole 2a is connected to the shielding polysilicon in the fourth trench 1a, and a top of the first contact hole 2a is connected to a drain.
A second contact hole 2b is provided in a partial region of the annular structure of the third trench 1b, a bottom of the second contact hole 2b is connected to the shield polysilicon in the third trench 1b, and a top of the second contact hole 2b is connected to a source.
A third contact hole 2c is formed in the surface of the semiconductor substrate outside the outer side surface of the fourth trench 1a, and the top of the third contact hole 2c is connected to the drain electrode.
A first distance, which is denoted by Space in fig. 3, is provided between the inner side of the fourth groove 1a and the outer side of the third groove 1 b. The first pitch is greater than half the longitudinal thickness of the drift region of the SGT power device to achieve withstand voltage between the third trench 1b and the fourth trench 1 a.
Typically, both the active region and the shielding polysilicon in the third trench 1b will be connected to the source, and so will also be referred to as source polysilicon field plate. But the shield polysilicon in the fourth trench 1a is no longer connected to the source but to the drain. Since a large potential difference occurs between the source and the drain, the third trench 1b and the fourth trench 1a cannot be too close, i.e. the first pitch cannot be too small, which is at least greater than half the longitudinal thickness of the drift region; in actual selection, the first interval can also be directly selected as the longitudinal thickness of the drift region; in a typical layout, this first pitch is at least 6 μm larger. In the embodiment of the invention, a first epitaxial layer is formed on the semiconductor substrate, and each groove is formed in the first epitaxial layer. The drift region is composed of the first epitaxial layer at the bottom of the body region, so that the first interval is at least greater than half of the thickness of the first epitaxial layer; in a practical option, the first spacing can also be selected directly as the thickness of the first epitaxial layer.
In the embodiment of the present invention, the ratio of the area occupied by each first trench 1c to the area occupied by each second trench 1d in the active region is adjusted according to layout requirements under the condition that the stress in the semiconductor substrate is reduced below a required value. Preferably, the ratio of the area occupied by each of the first trenches 1c to the area occupied by the second trench 1d in the active region is 1:1.
in the prior art method, the stripe arrangement of the trenches in the active region, i.e. the cell region, has only one direction, either the lateral direction shown by the first trench 1c or the longitudinal direction shown by the second trench 1 d. However, in the embodiment of the present invention, the active region has two trenches in different directions, i.e., the first trench 1c in the transverse direction and the second trench 1d in the longitudinal direction, and the trenches in different directions change the stress from the original single direction to the two directions. Thus, warpage of the chip is greatly relieved. When the process is performed according to the existing method, the strip-shaped arrangement of the grooves of the active region is the transverse direction shown by the first groove 1c, and when the grooves are etched, and the polysilicon Gate (Gate Poly) is manufactured, the wafer corresponding to the semiconductor substrate is too serious in warpage, and the subsequent process cannot be performed. The layout structure of the embodiment of the invention can smoothly complete all process flows in the process and realize mass production. Therefore, the embodiment of the invention can well solve the stress. In the embodiment of the invention, the trench of the active region is divided into two parts, one part is a first transverse trench 1c and the other part is a second longitudinal trench 1d; the optimal ratio of the first trench 1c and the second trench 1d is 50% each. Or approximately 50%, and the proportion can be adjusted according to the requirement of the layout.
In the active region, a plurality of adjacent first trenches 1c are arranged in parallel to form a first splice block, and a plurality of adjacent second trenches 1d are arranged in parallel to form a second splice block. The number of the first splicing blocks is more than one; the number of the second splicing blocks is more than one. In a preferred embodiment, the total area of each of the first tiles and the total area of each of the second tiles in the active region are approximately equal, so that stress is best addressed. In the first structure shown in fig. 3, the number of the first splice pieces and the second splice pieces is one. In the second structure shown in fig. 4, the number of the first splice pieces and the second splice pieces is one. In the third structure shown in fig. 5, the number of the first splice pieces and the second splice pieces is one. In the fourth structure shown in fig. 6, the number of the first splice blocks is 2, and the number of the second splice blocks is one. In the fifth structure shown in fig. 7, the number of the first and second tiles is one, wherein the second tile is interrupted by the gate pad 3.
In the embodiment of the present invention, the annular structure of the third groove 1b is a closed ring, and the annular structure of the third groove 1b is a rectangular ring with four rounded corners.
In some embodiments, a first structure as shown in fig. 3 may be adopted, where each of the first trenches 1c, each of the second trenches 1d, and each of the third trenches 1b are connected together, so that each of the first trenches 1c and each of the second trenches 1d in the active area is in a closed loop structure as a whole, and the shielding polysilicon in each of the first trenches 1c and each of the second trenches 1d and the shielding polysilicon in the third trenches 1b are conducted and connected to the source electrode through the second contact hole 2b on top of the third trenches 1 b. Since the shield polysilicon in the first trench 1c and the second trench 1d is connected to the source electrode through the second contact hole 2b on top of the third trench 1b, it is generally not necessary to provide a contact hole connecting the shield polysilicon to the source electrode in the first trench 1c and the second trench 1 d. In some embodiments, in order to reduce the extraction resistance of the shielding polysilicon in the first trench 1c and the second trench 1d, that is, the source resistance, can also be set as follows: a fourth contact hole is formed at the top of the selected region of each first trench 1c, the bottom of the fourth contact hole is connected to the shielding polysilicon in the first trench 1c, and the top of the fourth contact hole is connected to the source electrode. A fifth contact hole is formed at the top of the selected region of each of the second trenches 1d, the bottom of the fifth contact hole is connected to the shielding polysilicon in the second trench 1d, and the top of the fifth contact hole is connected to the source electrode.
In fig. 3, the first trench 1c and the second trench 1d are connected to the third trench 1b, that is, a closed loop structure, and the normally closed loop structure has a risk of over-depletion at the junction between the third trench 1b and the first trench 1c or between the third trench 1b and the second trench 1d, resulting in a lower breakdown voltage of the device.
In some embodiments, a second structure as shown in fig. 4 may be adopted, where two ends of each first trench 1c are spaced from the adjacent third trench 1b or the second trench 1d, and two ends of each second trench 1d are spaced from the adjacent third trench 1b or the first trench 1c, so that each first trench 1c and each second trench 1d in the active area have an open loop structure. The second structure needs to be set as follows: forming a fourth contact hole on the top of the selected area of each first trench 1c, wherein the bottom of the fourth contact hole is connected with the shielding polysilicon in the first trench 1c, and the top of the fourth contact hole is connected with the source electrode; a fifth contact hole is formed at the top of the selected region of each of the second trenches 1d, the bottom of the fifth contact hole is connected to the shielding polysilicon in the second trench 1d, and the top of the fifth contact hole is connected to the source electrode. The choice of the distance between the trenches is critical for the open loop structure shown in fig. 4. If too small and too large are chosen, they result in a lower Breakdown Voltage (BV). Further, for the open loop structure, the first trench 1c and the second trench 1d are not connected to the third trench 1b, and thus the first trench 1c and the second trench 1d need to be separately formed with a contact hole at the top for connection to the source electrode.
In some embodiments, the following structure may also be employed: a space is formed between one end of each first trench 1c and the adjacent third trench 1b or the second trench 1d, and the other end of each first trench 1c is communicated with the adjacent third trench 1b or the second trench 1d, a space is formed between one end of each second trench 1d and the adjacent third trench 1b or the first trench 1c, and the other end of each second trench 1d is communicated with the adjacent third trench 1b or the first trench 1c, so that each first trench 1c and each second trench 1d in the active region are in a half-open half-closed structure; the shield polysilicon in each of the first trenches 1c and each of the second trenches 1d and the shield polysilicon in the third trench 1b are conductive and connected to the source electrode through the second contact hole 2b at the top of the third trench 1 b. In the half-open and half-close structure, it is generally not necessary to provide contact holes connecting the shield polysilicon to the source in the first trench 1c and the second trench 1d, similarly to the first structure. In some embodiments, in order to reduce the extraction resistance of the shielding polysilicon in the first trench 1c and the second trench 1d, that is, the source resistance, the half-open and half-closed structure can also be set as follows: forming a fourth contact hole on the top of the selected area of each first trench 1c, wherein the bottom of the fourth contact hole is connected with the shielding polysilicon in the first trench 1c, and the top of the fourth contact hole is connected with the source electrode; a fifth contact hole is formed at the top of the selected region of each of the second trenches 1d, the bottom of the fifth contact hole is connected to the shielding polysilicon in the second trench 1d, and the top of the fifth contact hole is connected to the source electrode.
As shown in fig. 3, the annular structure of the fourth groove 1a is a closed ring; the annular structure of the fourth groove 1a is a rectangular ring with four rounded corners.
In the first structure shown in fig. 3, no other trench is provided between the fourth trench 1a and the third trench 1 b.
In some embodiments can also be: the fourth groove 1a and the third groove 1b comprise more than one fifth groove 1e with annular structures; the annular structure of the fifth groove 1e is a closed ring; the annular structure of the fifth groove 1e is a rectangular ring with four rounded corners. In the second structure shown in fig. 5, one of the fifth grooves 1e is provided in the fourth groove 1a and the third groove 1b, and the first pitch shown as Space is provided between the fifth groove 1e and the fourth groove 1a in fig. 5.
In some embodiments, each of the fifth trenches 1e is a floating structure, and does not receive any potential. In other embodiments can also be: a sixth contact hole is provided in a partial region of the annular structure of the fifth trench 1e, a bottom of the sixth contact hole is connected to the shield polysilicon in the fifth trench 1e, and a top of the sixth contact hole is connected to the source electrode. One fifth groove 1e is used in fig. 5, and in other embodiments, more than 2 or 3 fifth grooves 1e can be used.
In some embodiments, the third contact hole 2c is in a stripe structure and is located outside one or more sides of the rectangular ring of the fourth trench 1 a. As shown in fig. 3, the third contact hole 2c is located outside one side of the rectangular ring of the fourth trench 1 a; as shown in fig. 4, the third contact hole 2c is located outside one side of the rectangular ring of the fourth trench 1 a; as shown in fig. 5, the third contact hole 2c is located outside one side of the rectangular ring of the fourth trench 1 a; as shown in fig. 6, the third contact hole 2c is located outside two sides of the rectangular ring of the fourth trench 1 a; as shown in fig. 7, the third contact hole 2c is located outside one side of the rectangular ring of the fourth trench 1 a. In other embodiments can also be: the third contact hole 2c has a ring-shaped structure surrounding the outer periphery of the fourth trench 1 a.
In the active region, the SGT power device further includes a polysilicon gate.
In some embodiments, the polysilicon gate is a planar gate, the polysilicon gate is located on the surface of the semiconductor substrate outside the first trench 1c and the second trench 1d, and a gate dielectric layer is spaced between the polysilicon gate and the semiconductor substrate.
In some embodiments can also be: the polysilicon gate is a trench gate, the polysilicon gate is formed in a gate trench located outside the first trench 1c and the second trench 1d, the depth of the gate trench is shallower than that of the trench, and a gate dielectric layer is spaced between the polysilicon gate and the side surface of the gate trench;
in some embodiments can also be: the polysilicon gates are formed in the first trenches 1c and the second trenches 1d, a gate dielectric layer is arranged between the polysilicon gates and the side surfaces of the corresponding trenches at intervals, a polysilicon inter-dielectric layer is arranged between the polysilicon gates and the shielding polysilicon at intervals, a gate structure is formed by overlapping the shielding dielectric layer, the shielding polysilicon, the gate dielectric layer, the polysilicon inter-dielectric layer and the polysilicon gates, the gate structure is an up-down structure, and the polysilicon gates are positioned at the top of the shielding polysilicon; or the grid structure is a left-right structure, and the polysilicon gate is positioned in the top areas at the left side and the right side of the shielding polysilicon.
In the embodiment of the present invention, the width of the third trench 1b is greater than or equal to the width of the second contact hole 2b plus 2 times the alignment accuracy of the second contact hole 2b, and the width of the fourth trench 1a is greater than or equal to the width of the first contact hole 2a plus 2 times the alignment accuracy of the first contact hole 2 a. Preferably, the widths of the first contact hole 2a and the second contact hole 2b are equal, and the width of the third trench 1b is equal to the width of the fourth trench 1 a.
The width of each first groove 1c is equal to the width of each second groove 1d and is equal to or smaller than the width of the third groove 1 b.
The widths of the grooves can all be set to be the same. In actual process, however, the third trench 1b and the fourth trench 1a are connected with shielding polysilicon due to the fact that a through hole, i.e. a contact hole, is to be drilled in the trenches. The width of the shield polysilicon at this time needs to be greater than the width of the via +2 x the alignment accuracy of the via. In some embodiments, the width of the via is 0.3 μm and the alignment accuracy of the via is 0.1 μm; this time requires the width of the shield polysilicon to be greater than 0.5 μm. In order to satisfy the width of the shield polysilicon, the widths of the third trench 1b and the fourth trench 1a may be widened, for example, the widths of the third trench 1b and the fourth trench 1a may be set to be increased by 0.1 to 0.2 μm in the widths of the first trench 1c and the second trench 1 d. Preferably 0.1 μm.
In some embodiments, as shown in fig. 7, the top of each polysilicon gate is connected to the gate pad 3 patterned with the front side metal layer through a seventh contact hole. The outer side surface of a section of the third trench 1b surrounds the gate pad 3 in a plan view, so that the gate pad 3 is located outside the active region. In practice, the MOSFET, the polysilicon gate, needs to be led out through one of said gate pads 3. Under the gate pad 3 there is no active region and the trench under the gate pad 3 increases the capacitance of the device, causing additional loss. For this case, a trench may not be provided under the gate pad 3, in which case the trench structure layout can employ the layout shown in fig. 7.
The embodiment of the invention particularly sets the arrangement structure of the grooves provided with the shielding polysilicon, the third groove 1b surrounds and defines an active area, the first groove 1c and the second groove 1d which are mutually perpendicular are arranged in the active area, and the stress in the semiconductor substrate is prevented from being concentrated in one direction and thus reduced by the vertical arrangement of the first groove 1c and the second groove 1 d.
A fourth groove 1a is formed on the outer side of the third groove 1b, a drain electrode connected with a contact hole is formed on the shielding polycrystalline silicon in the fourth groove 1a and the surface of the semiconductor substrate outside the fourth groove 1a, and the shielding polycrystalline silicon in the third groove 1b is connected with a source electrode through a corresponding contact hole, namely a second contact hole 2b, so that the structure can well protect a terminal in an active area; meanwhile, the third groove 1b and the fourth groove 1a are of annular structures, and the annular structures are also beneficial to stress dispersion of the semiconductor substrate, and finally the stress of the semiconductor substrate can be further reduced.
As can be seen from the above, the trench arrangement of the active region and the termination region according to the embodiments of the present invention not only can well meet the performance requirements of the device, but also can reduce the stress of the semiconductor substrate, and can prevent the process problem caused by the stress of the device, for example, can prevent the wafer formed by the semiconductor substrate from warping during the process, and can prevent the wafer from warping from affecting the alignment process, thereby improving the alignment precision, and can further prevent the occurrence of serious wafer warping that makes the photolithography machine incapable of performing photolithography.
The present invention has been described in detail by way of specific examples, but these should not be construed as limiting the invention. Many variations and modifications may be made by one skilled in the art without departing from the principles of the invention, which is also considered to be within the scope of the invention.

Claims (20)

1. An SGT power device, wherein a shield polysilicon is formed in a trench formed in a semiconductor substrate, a shield dielectric layer is spaced between the shield polysilicon and the trench, and a mismatch in the depth of the trench and the coefficient of thermal expansion of the shield dielectric layer and the semiconductor substrate material creates stress in the semiconductor substrate;
on a top view, the grooves are divided into a first groove, a second groove, a third groove and a fourth groove, and an arrangement structure formed by the grooves comprises:
a plurality of first grooves and a plurality of second grooves are distributed in the active region, the first grooves and the second grooves are in a strip-shaped structure, the first grooves are arranged in parallel, the second grooves are arranged in parallel, the first grooves and the second grooves are perpendicular to each other, and stress in the semiconductor substrate is prevented from being concentrated in one direction and reduced through the perpendicular arrangement of the first grooves and the second grooves;
The third groove is of an annular structure, the active region is located in a region surrounded by the inner side surface of the third groove, and the outer side surface of the third groove is a terminal region;
the fourth groove is located in the terminal area, is of an annular structure and surrounds the outer side of the third groove;
a first contact hole is formed in a part area of the annular structure of the fourth groove, the bottom of the first contact hole is connected with the shielding polycrystalline silicon in the fourth groove, and the top of the first contact hole is connected to the drain electrode;
a second contact hole is formed in a part area of the annular structure of the third groove, the bottom of the second contact hole is connected with the shielding polycrystalline silicon in the third groove, and the top of the second contact hole is connected to the source electrode;
forming a third contact hole on the surface of the semiconductor substrate outside the outer side surface of the fourth groove, wherein the top of the third contact hole is connected to the drain electrode;
a first interval is arranged between the inner side surface of the fourth groove and the outer side surface of the third groove, and the first interval is more than half of the longitudinal thickness of the drift region of the SGT power device so as to realize pressure resistance between the third groove and the fourth groove.
2. The SGT power device of claim 1, wherein: the ratio of the occupied area of each first groove to the occupied area of each second groove in the active region is adjusted according to layout requirements under the condition that the stress in the semiconductor substrate is reduced below a required value.
3. The SGT power device of claim 2, wherein: the ratio of the area occupied by each first groove to the area occupied by each second groove in the active region is 1:1.
4. the SGT power device of claim 1 or 2 or 3, wherein: in the active region, a plurality of adjacent first grooves are arranged in parallel to form a first splicing block, and a plurality of adjacent second grooves are arranged in parallel to form a second splicing block;
the number of the first splicing blocks is more than one; the number of the second splicing blocks is more than one.
5. The SGT power device of claim 4, wherein: the annular structure of the third groove is a closed ring, and the annular structure of the third groove is a rectangular ring with four rounded corners.
6. The SGT power device of claim 5, wherein: each of the first trenches, each of the second trenches, and each of the third trenches are connected together such that each of the first trenches and each of the second trenches in the active region are in a closed loop structure as a whole, and the shield polysilicon in each of the first trenches and each of the second trenches and the shield polysilicon in the third trenches are connected to the source electrode through the second contact hole at the top of the third trench.
7. The SGT power device of claim 6, wherein: forming a fourth contact hole on the top of the selected area of each first groove, wherein the bottom of the fourth contact hole is connected with the shielding polysilicon in the first groove, and the top of the fourth contact hole is connected to the source electrode;
a fifth contact hole is formed at the top of the selected region of each second trench, the bottom of the fifth contact hole is connected with the shielding polysilicon in the second trench, and the top of the fifth contact hole is connected with the source electrode.
8. The SGT power device of claim 5, wherein: the two ends of each first groove are spaced from the adjacent third grooves or second grooves, and the two ends of each second groove are spaced from the adjacent third grooves or first grooves, so that each first groove and each second groove in the active region are in an open-loop structure;
forming a fourth contact hole on the top of the selected area of each first groove, wherein the bottom of the fourth contact hole is connected with the shielding polysilicon in the first groove, and the top of the fourth contact hole is connected to the source electrode;
A fifth contact hole is formed at the top of the selected region of each second trench, the bottom of the fifth contact hole is connected with the shielding polysilicon in the second trench, and the top of the fifth contact hole is connected with the source electrode.
9. The SGT power device of claim 5, wherein: a space is reserved between one end of each first groove and the adjacent third groove or the second groove, the other end of each first groove is communicated with the adjacent third groove or the second groove, a space is reserved between one end of each second groove and the adjacent third groove or the first groove, and the other end of each second groove is communicated with the adjacent third groove or the first groove, so that each first groove and each second groove in the active area are in a half-open and half-closed structure;
the shield polysilicon in each of the first trenches and each of the second trenches and the shield polysilicon in the third trenches are conductive and connected to the source electrode through the second contact hole at the top of the third trench.
10. The SGT power device of claim 9, wherein: forming a fourth contact hole on the top of the selected area of each first groove, wherein the bottom of the fourth contact hole is connected with the shielding polysilicon in the first groove, and the top of the fourth contact hole is connected to the source electrode;
A fifth contact hole is formed at the top of the selected region of each second trench, the bottom of the fifth contact hole is connected with the shielding polysilicon in the second trench, and the top of the fifth contact hole is connected with the source electrode.
11. The SGT power device of claim 5, wherein: the annular structure of the fourth groove is a closed ring; the annular structure of the fourth groove is a rectangular ring with four rounded corners.
12. The SGT power device of claim 11, wherein: the fourth groove and the third groove comprise more than one fifth groove with annular structures; the annular structure of the fifth groove is a closed ring; the annular structure of the fifth groove is a rectangular ring with four rounded corners.
13. The SGT power device of claim 12, wherein: each fifth groove is a floating structure; alternatively, a sixth contact hole is provided in a partial region of the annular structure of the fifth trench, a bottom of the sixth contact hole is connected to the shielding polysilicon in the fifth trench, and a top of the sixth contact hole is connected to the source electrode.
14. The SGT power device of claim 1, wherein: the third contact hole is in a strip line structure and is positioned outside more than one edge of the rectangular ring of the fourth groove;
Or, the third contact hole is in an annular structure surrounding the periphery of the fourth groove.
15. The SGT power device of claim 1, wherein: a first epitaxial layer is formed on the semiconductor substrate, and each groove is formed in the first epitaxial layer.
16. The SGT power device of claim 15, wherein: in the active region, the SGT power device further includes a polysilicon gate;
the polysilicon gate is a planar gate, the polysilicon gate is positioned on the surface of the semiconductor substrate outside the first groove and the second groove, and a gate dielectric layer is arranged between the polysilicon gate and the semiconductor substrate at intervals;
or the polysilicon gate is a trench gate, the polysilicon gate is formed in a gate trench outside the first trench and the second trench, the depth of the gate trench is shallower than that of the trench, and a gate dielectric layer is arranged between the polysilicon gate and the side surface of the gate trench at intervals;
or the polysilicon gates are formed in the first grooves and the second grooves, a gate dielectric layer is arranged between the polysilicon gates and the side surfaces of the corresponding grooves at intervals, a polysilicon inter-dielectric layer is arranged between the polysilicon gates and the shielding polysilicon at intervals, a grid structure is formed by overlapping the shielding dielectric layer, the shielding polysilicon, the gate dielectric layer, the polysilicon inter-dielectric layer and the polysilicon gates, the grid structure is of an up-down structure, and the polysilicon gates are positioned at the top of the shielding polysilicon; or the grid structure is a left-right structure, and the polysilicon gate is positioned in the top areas at the left side and the right side of the shielding polysilicon.
17. The SGT power device of claim 1, wherein: the width of the third groove is larger than or equal to the width of the second contact hole plus the alignment precision of the second contact hole by 2 times, and the width of the fourth groove is larger than or equal to the width of the first contact hole plus the alignment precision of the first contact hole by 2 times.
18. The SGT power device of claim 17, wherein: the widths of the first contact hole and the second contact hole are equal, and the width of the third groove is equal to the width of the fourth groove.
19. The SGT power device of claim 18, wherein: the width of each first groove is equal to the width of each second groove and is smaller than or equal to the width of the third groove.
20. The SGT power device of claim 16, wherein: the top of each polysilicon gate is connected to a gate pad formed by patterning the front metal layer through a seventh contact hole;
an outer side surface of a section of the third trench surrounds the gate pad in a top view, so that the gate pad is located outside the active region.
CN202111569970.XA 2021-12-21 2021-12-21 SGT power device Pending CN116314249A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117727776A (en) * 2023-12-19 2024-03-19 深圳市创飞芯源半导体有限公司 Groove type MOSFET device and preparation method thereof, electronic equipment and preparation method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117727776A (en) * 2023-12-19 2024-03-19 深圳市创飞芯源半导体有限公司 Groove type MOSFET device and preparation method thereof, electronic equipment and preparation method thereof

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