JP4500530B2 - Insulated gate semiconductor device and manufacturing method thereof - Google Patents

Insulated gate semiconductor device and manufacturing method thereof Download PDF

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JP4500530B2
JP4500530B2 JP2003375098A JP2003375098A JP4500530B2 JP 4500530 B2 JP4500530 B2 JP 4500530B2 JP 2003375098 A JP2003375098 A JP 2003375098A JP 2003375098 A JP2003375098 A JP 2003375098A JP 4500530 B2 JP4500530 B2 JP 4500530B2
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semiconductor device
trench
floating region
floating
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JP2005142243A (en
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康嗣 大倉
規仁 戸倉
公守 濱田
秀史 高谷
晃 黒柳
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トヨタ自動車株式会社
株式会社デンソー
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  The present invention relates to an insulated gate semiconductor device having a trench gate structure and a method for manufacturing the same. More specifically, the present invention relates to an insulated gate semiconductor device that achieves both high breakdown voltage and low on-resistance by relaxing an electric field applied to a semiconductor layer, and a method for manufacturing the same.

  Conventionally, a trench gate type semiconductor device having a trench gate structure has been proposed as an insulated gate type semiconductor device for power devices. In this trench gate type semiconductor device, a high breakdown voltage and a low on-resistance are generally in a trade-off relationship.

As a trench gate type semiconductor device paying attention to this point, for example, there is one disclosed in Patent Document 1. This trench gate type semiconductor device is schematically configured as shown in FIG. That is, the N + source region 31 is provided on the upper surface side in FIG. 26, and the N + drain region 11 is provided on the lower side. Between them, a P body region 41 and an N drift region 12 are provided from the upper surface side. Further, a trench 21 formed by digging a part of the upper surface side of the semiconductor device is provided. In addition, a gate electrode 22 is built in the trench 21. A P floating region 50 is provided immediately below the trench 21. The gate electrode 22 is insulated from the P body region 41 by a gate insulating film 24 formed on the wall surface of the trench 21.

In this trench gate type semiconductor device, when the gate voltage is switched off, a depletion layer spreads from the PN junction between the P body region 41 and the N drift region 12 toward the N + drain region 11 and P floating A depletion layer also spreads from the lower end of the region 50 toward the N + drain region 11. That is, the P floating region 50 promotes depletion of the N drift region 12. As a result, the breakdown voltage between the drain and the source can be increased.

  As another trench gate type semiconductor device, for example, there is one described in Patent Document 2. In this trench gate type semiconductor device, a P floating region 59 is provided at a position away from the trench 21 as shown in FIG. The P floating region 59 is also capable of increasing the breakdown voltage between the drain and source as in the insulated gate semiconductor device of FIG.

The semiconductor device shown in FIG. 27 is manufactured by the following procedure. First, an N type silicon layer to be an N type drift region 12 is formed on an N + substrate to be an N + drain region 11 by epitaxial growth. At this time, the N type silicon layer is formed up to the position Z in FIG. Next, a P floating region 59 is formed by ion implantation or the like. Next, epitaxial growth is performed again to form the remaining N type silicon layer. As a result, a semiconductor device in which the P floating region 59 is completely surrounded by the N drift region 12 is formed. By repeating these steps, a number of P floating regions 59 can be formed at different depths.

In addition, the termination area of these trench gate type semiconductor devices generally has a structure as shown in FIG. That is, a P termination diffusion region 61 having a depth equal to or greater than the depth of the trench 21 is formed in the termination area. Thereby, a depletion layer is also formed around the P termination diffusion region 61 when the gate voltage is switched off. This alleviates the concentration of the electric field at the terminal end.
Japanese Patent Laid-Open No. 10-98188 JP-A-9-191109

  However, the semiconductor device shown in FIG. 26 has the following problems. That is, the P floating region 50 is formed by ion implantation from the bottom of the trench 21. For this reason, the bottom of the trench 21 is not a little damaged. Therefore, if the gate insulating film 24 is formed as it is, problems such as deterioration of element characteristics and reliability are caused. Further, the gate electrode 22 faces the P floating region 50. For this reason, at the time of turning on, charges are dispersed in the portion facing the P body region 41 and the portion facing the P floating region 50 in the gate electrode 22. For this reason, the on-resistance increases.

On the other hand, in the semiconductor device of FIG. 27, since the P floating region 59 is formed away from the trench 21, the above problem can be avoided and a high breakdown voltage can be achieved. However, when forming the P floating region 54 completely surrounded by the N drift region 12, at least two N type silicon layer forming steps (epitaxial growth steps) are required. It takes time and effort.

Further, in order to alleviate the concentration of the electric field in the termination area, it is necessary to form a P termination diffusion region 61 having a thickness different from that of each P floating region formed in the cell area. For this reason, the number of processes is large, and it takes time and effort to manufacture. Further, since the thermal load is large, impurities in the N type drift region 12 (epitaxial layer) diffuse and the concentration varies. Then, in order to make up for it N - need to increase the thickness of the type drift region 12, as a result on-resistance is increased.

  The present invention has been made to solve at least one of the problems of the conventional trench gate type semiconductor device. That is, an object of the present invention is to provide an insulated gate semiconductor device and a method for manufacturing the same that can be easily manufactured while achieving both high breakdown voltage and low on-resistance.

An insulated gate semiconductor device for solving this problem includes a body region which is a first conductivity type semiconductor located on the upper surface side in a semiconductor substrate, and a drift which is a second conductivity type semiconductor in contact with the lower surface of the body region. An insulated gate semiconductor device having a region and a trench portion penetrating the body region from the upper surface of the semiconductor substrate and having a bottom portion located below the lower surface of the body region, and is surrounded by a drift region and is a first conductivity type semiconductor The bottom of the trench is located in the floating region, and in the trench is a deposited insulating layer formed by depositing an insulator, and is located on the deposited insulating layer and faces the body region. a gate electrode is formed, the upper end of the deposited insulating layer is located above the upper end of the floating region, the lower surface of the body region and the floating The distance between the lower end of the deposited insulating layer and the lower end of the floating region is larger than the distance between the lower end of the gate electrode and the lower end of the deposited insulating layer. The thickness of the deposited insulating layer is wider than the interval of (2), and the thickness is such that the electric field peaks are formed in at least two places in the thickness direction .

  That is, the insulated gate semiconductor device of the present invention has a floating region surrounded by a drift region. This floating region can promote depletion of the drift region at the off time. In addition, electric field peaks can be formed at a plurality of locations, and the maximum peak value can be reduced. In addition, a deposited insulating layer is provided in the trench portion. As a result, the gate insulating film and the gate electrode are not affected by the damage of the trench portion. Therefore, deterioration of element characteristics and deterioration of reliability are suppressed. The upper end of the deposited insulating layer is located above the upper end of the floating region. As a result, the facing of the gate electrode and the floating region is suppressed, and an increase in on-resistance is prevented.

  The insulated gate semiconductor device of the present invention is located above the upper end of the floating region, is surrounded by the drift region and has an intermediate floating region which is the first conductivity type semiconductor, and the trench portion has the intermediate floating region. It is better that the upper end of the deposited insulating layer is located above the upper end of the intermediate floating region.

  That is, an intermediate floating region having the same action as the floating region is provided between the body region and the floating region. As a result, electric field peaks can be formed in at least three locations, and the maximum peak value can be further reduced. Therefore, higher breakdown voltage and lower on-resistance can be achieved. Note that the number of intermediate floating regions is not limited to one, and a plurality of intermediate floating regions may be provided. The more intermediate floating regions, the more electric field peaks can be formed and the maximum peak value can be further reduced.

  The insulated gate semiconductor device according to the present invention includes an auxiliary trench portion penetrating the body region from the upper surface of the semiconductor substrate and having a bottom portion located below the lower surface of the body region and filled with an insulator inside, and a drift region. It is better to have an auxiliary floating region that is surrounded by the first conductive type semiconductor and that the bottom of the auxiliary trench portion is located within the auxiliary floating region. That is, a plurality of auxiliary floating regions having the same action as the floating region are formed. Thereby, since the density of the floating region including the auxiliary floating region is high, the manufacturing margin such as the size of the floating region is large.

  In the insulated gate semiconductor device of the present invention, it is better that the depth of the trench portion and the depth of the auxiliary trench portion are different. Thereby, the floating region and the auxiliary floating region are provided at different positions in the thickness direction. Therefore, electric field peaks can be formed at three locations, and the maximum peak value can be further reduced.

  On the other hand, in the insulated gate semiconductor device of the present invention, the depth of the trench portion and the depth of the auxiliary trench portion may be the same. Since the trench part and the auxiliary trench part have the same depth, the trench part and the auxiliary trench part can be formed in the same process. Therefore, the number of processes can be reduced. Moreover, even if the distance between adjacent floating regions is short and the concentration of the drift region is high, the depletion layer can be connected reliably. Therefore, a low on-resistance can be achieved. Also, the size of each floating area can be small. In addition, since the thermal diffusion process can be performed in the same process, the diffusion of impurities is small and a decrease in on-resistance due to the thermal diffusion process can be suppressed. Note that the “same” depth here does not mean that it must match exactly. That is, a slight shift in the depth that occurs during trench formation is within the same range.

The insulated gate semiconductor device according to the present invention includes an auxiliary trench portion penetrating the body region from the upper surface of the semiconductor substrate and having a bottom portion located below the lower surface of the body region and filled with an insulator inside, and a drift region. an auxiliary floating region is a first conductive type semiconductor with surrounded by the bottom of the auxiliary trench portion may be I der those located in the auxiliary floating region.

  That is, the insulated gate semiconductor device of the present invention has an auxiliary floating region surrounded by a drift region. This auxiliary floating region can promote the depletion of the drift region at the off time. The auxiliary floating region is provided below an auxiliary trench portion formed for the auxiliary floating region. For this reason, the design flexibility of the auxiliary floating region is high. On the other hand, the trench portion containing the gate electrode can be formed by the same manufacturing method as in the prior art. Therefore, there is no ion implantation from the bottom, and problems such as deterioration of device characteristics and deterioration of reliability do not occur.

  The insulated gate semiconductor device of the present invention is located above the upper end of the auxiliary floating region, and is surrounded by the drift region and has an auxiliary intermediate floating region that is the first conductivity type semiconductor. It is better if the intermediate auxiliary floating region is penetrated and the upper end of the deposited insulating layer is located above the upper end of the intermediate auxiliary floating region. As a result, electric field peaks can be formed in at least three locations, and the maximum peak value can be further reduced. Therefore, higher breakdown voltage and lower on-resistance can be achieved.

  Further, the insulated gate semiconductor device of the present invention is opposed to the auxiliary trench portion with the gate electrode interposed therebetween, penetrates the body region from the upper surface of the semiconductor substrate, the bottom portion is located below the lower surface of the body region, and the inner side is A second auxiliary trench portion filled with an insulator and a second auxiliary floating region which is surrounded by the drift region and is a first conductivity type semiconductor are provided, and the auxiliary trench portion and the second auxiliary trench portion are deep with respect to each other. It is better if they are different.

  That is, since the auxiliary trench portion and the second auxiliary trench portion have different depths, the auxiliary floating region and the second floating region have different positions in the thickness direction. Therefore, electric field peaks can be formed at three locations, and the maximum peak value can be reduced. Further, since the auxiliary floating region and the second floating region can be formed by the same thermal diffusion process, the thermal load is small.

  Further, it is better that the auxiliary trench portion of the insulated gate semiconductor device of the present invention is configured in a dot shape when viewed from above the semiconductor substrate. As a result, the current path is wide and low on-resistance can be achieved.

  In addition, the insulated gate semiconductor device of the present invention is located in the peripheral region of the cell region, and is surrounded by a termination trench portion filled with an insulator, and a termination floating region that is surrounded by a drift region and is a first conductivity type semiconductor. More preferably, the bottom of the termination trench is located in the termination floating region.

  That is, a termination floating region having the same action as the floating region is provided also in the termination area. As a result, a high breakdown voltage is also achieved in the termination area. The terminal floating area is the same size as the floating area in the cell area. Therefore, it is compact and has good controllability of size. Further, since the terminal floating region can be formed in the same process as the floating region, the formation thereof is easy. Furthermore, since it is formed in the same process, the thermal load is small compared with the conventional semiconductor device.

The method of manufacturing an insulated gate semiconductor device according to the present invention includes a body region that is located on the upper surface side of the semiconductor substrate and is a first conductivity type semiconductor, and a drift that is in contact with the lower surface of the body region and is a second conductivity type semiconductor. a region, a trench portion located floating region and the floating region, the bottom through the body region from the upper surface of the semiconductor substrate is a lower than the body region a first conductivity type semiconductor with surrounded by the drift region, located inside the trench portion, the floating area and contact, and the deposited insulating layer formed by depositing an insulating material, located inside the trench portion have a gate electrode facing the body region, the upper end of the deposited insulating layer , Located above the upper end of the floating region. The distance between the lower surface of the body region and the upper end of the floating region is The distance between the lower end of the gate region and the lower end of the deposited insulating layer is wider than the distance between the lower surface of the body region and the upper end of the floating region, and the thickness of the deposited insulating layer is A method of manufacturing an insulated gate semiconductor device having a thickness in which at least two electric field peaks are formed in the thickness direction, wherein a trench portion is formed in a semiconductor substrate in which a drift region and a body region are formed. A trench portion forming step, an impurity implantation step for injecting impurities from the bottom of the trench portion formed in the trench portion formation step, and an insulator for depositing an insulator in the trench portion after the impurities are implanted in the impurity implantation step. Floating region forming process that forms a floating region by performing thermal diffusion treatment after depositing an insulator in the material deposition step and the insulator deposition step It includes the door.

  In this manufacturing method, a drift region is formed by epitaxial growth or the like, and then a semiconductor substrate in which a body region is formed by impurity introduction technology such as ion implantation and thermal diffusion is used as a starting material. And the trench part which penetrates the body region is formed in the trench part forming step. In the floating region forming step, the floating region is formed by implanting impurities from the trench portion. That is, since the floating region is formed after the formation of the drift region and the body region, it is not necessary to form a single crystal silicon layer again by epitaxial growth after the formation of the floating region. Therefore, an insulated gate semiconductor device having a floating region can be easily manufactured.

  In addition, the method of manufacturing an insulated gate semiconductor device according to the present invention includes a trench portion deepening step for further deepening the bottom of the trench portion after the impurity is implanted in the impurity implantation step, and a trench portion deepened in the trench portion deepening step. It is better to include an impurity reinjection step of injecting impurities again from the bottom of the substrate. Thereby, a plurality of floating regions can be provided in the thickness direction of a wafer formed by one epitaxial growth. Therefore, it is possible to easily achieve both high breakdown voltage and low on-resistance.

  According to the present invention, both a high breakdown voltage and a low on-resistance can be achieved by the floating region surrounded by the drift region. In addition, the deposited insulating layer can avoid the influence of impurity implantation. In addition, the floating region can be formed without repeating the formation of the silicon layer by epitaxial growth. Therefore, an insulated gate semiconductor device and a method for manufacturing the same that can be easily manufactured while achieving both high breakdown voltage and low on-resistance are provided.

  DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments embodying the present invention will be described below in detail with reference to the accompanying drawings. In the present embodiment, the present invention is applied to a power MOS that controls conduction between a drain and a source (hereinafter referred to as “between DS”) by applying a voltage to an insulated gate.

[First embodiment]
An insulated gate semiconductor device 100 according to the first embodiment (hereinafter referred to as “semiconductor device 100”) has a structure shown in a sectional view of FIG. In FIG. 1, components having the same symbols as those of the conventional semiconductor device shown in FIG. 26 have the same functions as those components. In this specification, the whole of the starting substrate and the single crystal silicon portion formed by epitaxial growth on the starting substrate is referred to as a semiconductor substrate.

In the semiconductor device 100, an N + source region 31 and a P + source region 32 formed at a high concentration for reducing contact resistance are provided on the upper surface side in FIG. On the other hand, an N + drain region 11 is provided on the lower surface side. Between them, a P body region 41 and an N drift region 12 are provided from the upper surface side. The total thickness of the P body region 41 and the N drift region 12 (hereinafter referred to as “epitaxial layer”) is approximately 5.5 μm (of which the thickness of the P body region 41 is approximately 1.2 μm).

Further, a trench 21 is formed by digging a part of the upper surface side of the semiconductor substrate. The depth of trench 21 is approximately 3.2 μm and penetrates P body region 41. A deposited insulating layer 23 is formed at the bottom of the trench 21 by depositing an insulator. Specifically, the deposited insulating layer 23 is formed by depositing silicon oxide from the bottom of the trench 21 to a height of about 1.7 μm. Further, a gate electrode 22 is formed on the deposited insulating layer 23 by depositing a conductor (for example, polysilicon). The lower end of gate electrode 22 is located below the lower surface of P body region 41. The gate electrode 22 faces the N + source region 31 and the P body region 41 of the semiconductor substrate via the gate insulating film 24 formed on the wall surface of the trench 21. That is, the gate electrode 22 is insulated from the N + source region 31 and the P body region 41 by the gate insulating film 24. In the semiconductor device 100 having such a structure, a channel effect is generated in the P body region 41 by applying a voltage to the gate electrode 22, thereby controlling conduction between the N + source region 31 and the N + drain region 11. is doing.

Further, a P floating region 51 surrounded by the N drift region 12 is formed in the semiconductor substrate. The cross section of the P floating region 51 has a substantially circular shape with a radius of 0.6 μm centered on the bottom of the trench 21 as shown in the cross sectional view of FIG. The trenches 21 are formed with a pitch of about 3.0 μm. Therefore, there is a sufficient space between the adjacent P floating regions 51 and 51. Therefore, in the ON state, the presence of the P floating region 51 does not hinder the drain current. The radius (approximately 0.6 μm) of the P floating region 51 is ½ or less of the thickness (approximately 1.7 μm) of the deposited insulating layer 23. Therefore, the upper end of the deposited insulating layer 23 is located above the upper end of the P floating region 51. Therefore, the gate electrode 22 deposited on the deposited insulating layer 23 and the P floating region 51 do not face each other.

The semiconductor device 100 according to the present embodiment is provided with a P floating region 51 below the trench 21 in which the gate electrode 22 is built, and therefore has the following characteristics as compared with an insulated gate semiconductor device having no P gate region 22. Have That is, when the gate voltage is switched off, a depletion layer is formed in the N drift region 12 from the PN junction with the P body region 41 due to the voltage between DS. And the vicinity of the PN junction location becomes a peak of electric field strength. When the tip of the depletion layer reaches the P floating region 51, the P floating region 51 enters a punch-through state and its potential is fixed. In addition, when the applied voltage between the DSs is high, a depletion layer is also formed from the lower end of the P floating region 51. In addition to the PN junction between the P body region 41 and the vicinity of the lower end of the P floating region 51, the electric field strength peaks. That is, electric field peaks can be formed at two locations, and the maximum peak value can be reduced. Therefore, high breakdown voltage can be achieved. Further, since the withstand voltage is high, the on-resistance can be lowered by increasing the impurity concentration of the N drift region 12.

In addition, the semiconductor device 100 has the following characteristics because the deposited insulating layer 23 is provided in the trench 21. That is, since the P floating region 51 is formed by ion implantation or the like from the bottom of the trench 21 as will be described later, the bottom of the trench 21 is damaged to some extent. However, the presence of the deposited insulating layer 23 avoids the influence of damage to the bottom of the trench 21 and prevents inconveniences such as deterioration of device characteristics and deterioration of reliability. Further, the deposited insulating layer 23 alleviates the influence of the facing of the gate electrode 22 and the P floating region 51, and the on-resistance in the P body region 41 is reduced. In addition, since the gate electrode 22 is small compared to the case where the deposited insulating layer 23 is not provided, the gate-drain capacitance Cgd is small and the switching speed is fast.

A plurality of the P floating regions described above may be provided in the thickness direction of the semiconductor device. For example, as shown in FIG. 2, a structure in which two P floating regions are provided may be employed. In the semiconductor device 101 shown in FIG. 2, an epitaxial layer and a trench 21 having a deeper depth (about 8.5 μm) than the semiconductor device 100 shown in FIG. 1 are provided. A P floating region 51 centered on the bottom of the trench 21 and a P floating region 52 located between the P floating region 51 and the P body region 41 are provided. As a result, the depletion layer formed from the PN junction with the P body region 41 reaches the P floating region 51 after reaching the P floating region 52 once. Therefore, apart from the PN junction with the P body region 41, the electric field strength peaks at the lower end of the P floating region 52 and the lower end of the P floating region 51. Therefore, electric field peaks can be formed at three locations, and the maximum peak value can be further reduced. The number of electric field peak points can be increased as the number of P floating regions 52 positioned between the P floating region 51 and the P body region 41 is increased. Therefore, the higher the number of P floating regions 52, the higher the breakdown voltage and the lower on-resistance can be achieved.

Further, the P floating region may be provided in the terminal area of the semiconductor device. For example, as shown in FIG. 3, a structure in which a trench 62 and a P floating region 52 are provided in the termination area may be employed. In the semiconductor device 102 shown in FIG. 3, the trench 62 is filled with an insulator (such as silicon oxide). Further, a P floating region 53 having the same action as the P floating region 51 is formed. In the semiconductor device 102, the breakdown voltage is increased by the trench 62 and the P floating region 53 corresponding to the trench 62 as in the cell area. Further, the size of the P floating region 53 is smaller than that of the conventional P termination diffusion region 61. Therefore, the controllability of the size is good and the semiconductor device itself can be made compact. The P floating region 53 has a smaller thermal load than the P termination diffusion region 61 of the conventional semiconductor device (see FIG. 28). Therefore, the thickness of the N drift region 12 (epitaxial layer) can be reduced and the on-resistance can be reduced.

Next, a manufacturing process of the semiconductor device 100 shown in FIG. 1 will be described with reference to FIG. First, an N type silicon layer is formed on the N + substrate to be the N + drain region 11 by epitaxial growth. This N -type silicon layer (epitaxial layer) is a portion that becomes each of the N drift region 12, the P body region 41, and the N + source region 31. Then, a P body region 41 and an N + source region 31 are formed by subsequent ion implantation or the like. Thus, a semiconductor substrate having an epitaxial layer on the N + drain region 11 as shown in FIG. 4 (a) is produced.

Next, as shown in FIG. 4B, a trench 21 that penetrates the P body region 41 and reaches the bottom of the N drift region 12 is formed. Thereafter, a thermal oxidation process is performed to form an oxide film 95 having a thickness of about 50 nm on the wall surface of the trench 21. Next, ion implantation is performed from the bottom surface of the trench 21 as shown in FIG. The reason why the ion implantation is performed after the oxide film 95 is formed is to prevent the ion implantation from being performed on the sidewall of the trench 21. After the ion implantation, the oxide film 95 in the trench 21 is removed. If there is a problem of interface reference when embedding an oxide film, or if a thin oxide film is formed on the silicon surface and the embedding property of the insulator is better, a thin thermal oxide film of about 50 nm is used. It is preferable to embed an insulator after the formation. This is not necessary if the insulator surface is better embedded if the silicon surface is exposed.

  Next, as shown in FIG. 4D, an insulator (silicon oxide or the like) 23 is deposited in the trench 21 by CVD. Thereafter, a thermal diffusion process is performed for both the baking of the insulator and the formation of the P floating region 51. Thereby, the P floating region 51 is formed. Note that the size of the P floating region 51 is determined by the size of the bottom of the trench 21. Further, the position of the P floating region 51 in the thickness direction is determined by the depth of the trench. That is, since the P floating region 51 is formed based on the trench 21 having high dimensional accuracy, the dimensional accuracy is high. Next, as shown in FIG. 4E, a part of the insulator is removed by etching the semiconductor substrate on which the insulator is deposited. Thereby, a space for forming the gate electrode 22 is secured.

  Next, an oxide film 24 is formed on the upper surface of the semiconductor substrate and the wall surface of the trench 21 by thermal oxidation. This becomes the gate oxide film 24. Then, by depositing a conductor (polysilicon or the like) in the space secured in the previous step, the gate electrode 22 as shown in FIG. 4F is formed. Finally, by forming the source electrode and the drain electrode, an insulated gate semiconductor device as shown in FIG. 4G, that is, the semiconductor device 100 is manufactured.

  The semiconductor device 101 shown in FIG. 2 is manufactured by a manufacturing process as shown in FIG. The process until the ion implantation is performed after the trench 21 is formed (corresponding to FIG. 4C) is the same as the manufacturing process of the semiconductor device 100 shown in FIG. Thermal diffusion treatment is performed on the semiconductor substrate at that stage without depositing an insulator. As a result, a P floating region 52 is formed as shown in FIG.

  Next, the trench 21 is dug down by performing etching again as shown in FIG. Next, as shown in FIG. 5F, an oxide film 95 is formed on the wall surface of the trench 21 by performing a thermal oxidation process. Thereafter, ion implantation is performed again from the bottom surface of the trench 21. After the ion implantation, the oxide film 95 in the trench 21 is removed. If there is a problem of interface reference when embedding an oxide film, or if a thin oxide film is formed on the silicon surface and the embedding property of the insulator is better, a thin thermal oxide film of about 50 nm is used. It is preferable to embed an insulator after the formation. This is not necessary if the insulator surface is better embedded if the silicon surface is exposed.

  Next, as shown in FIG. 5G, an insulator (silicon oxide or the like) 23 is deposited in the trench 21 by CVD. Thereafter, a thermal diffusion process is performed for both the baking of the insulator and the formation of the P floating region 51. Thereby, the P floating region 51 is formed.

  Next, the gate electrode 22 built in the trench 21 as shown in FIG. 5 (h) is formed by performing the same work as the steps shown in FIG. 4 (e) and thereafter. Finally, by forming a source electrode and a drain electrode, an insulated gate semiconductor device as shown in FIG. 5I, that is, the semiconductor device 101 is manufactured. Note that the number of P floating regions 52 can be increased in the thickness direction by repeating the steps from FIG. 5D to FIG. 5F.

  Also, the P floating region 53 in the termination area shown in FIG. 3 can be produced in the same process as the P floating region 51 in the cell area. Therefore, the semiconductor device 102 with a high withstand voltage in the termination area can be easily manufactured with a small number of steps.

Next, with respect to the semiconductor device 100 shown in FIG. 1, measurement results of the withstand voltage between DS and the on-resistance will be described. FIG. 6 is a graph showing the relationship between the voltage Vds and the current Ids between DS when the gate voltage Vg is fixed at 0V. As shown in FIG. 6, it can be seen that the value of the current Ids is substantially constant when the voltage Vds is between 10V and 70V. When the voltage Vds exceeds 72V, the current Ids increases rapidly. That is, it can be seen that breakdown occurred at about 72V. FIG. 7 is a graph when the relationship between the voltage Vds and the current value Ids between DS is simulated by changing the gate voltage Vg. The slope of this graph corresponds to the on-resistance between DS. In general, the silicon limit (unipolar limit) is represented by an on-resistance (Ron) calculated by the following equation (1). In addition, Vb in Formula (1) shows a proof pressure.
Ron = 8.33 × 10 −9 (Vb) 2.5 (1)
For example, in the case of a withstand voltage of 72 V, the on-resistance of 36.6 mΩ · mm 2 is a unipolar limit. Here, for example, the on-resistance when the gate voltage Vg = 15 V in this embodiment is 34.0 mΩ · mm 2 from the slope of the graph of Vg = 15 V in FIG. Therefore, it can be seen that the insulated gate semiconductor device of this embodiment has a lower on-resistance than the unipolar limit.

[Second form]
An insulated gate semiconductor device 200 (hereinafter referred to as “semiconductor device 200”) according to the second embodiment has a structure shown in the sectional view of FIG. A feature of the semiconductor device 200 of this embodiment is that a trench for a P floating region is provided, and the bottom of the trench is located in the P floating region. This is different from the semiconductor device 100 (see FIG. 1) in which the bottom of the trench in which the gate electrode is built is located in the P floating region. In FIG. 8, components having the same symbols as those of the semiconductor device 100 shown in FIG. 1 have the same functions as those components.

The semiconductor device 200 is provided with an N + source region 31, an N + drain region 11, a P body region 41, and an N drift region 12, similarly to the semiconductor device 100 of the first embodiment. Further, a trench 21 formed by digging a part on the upper surface side of the semiconductor device 200 is provided. In addition, a gate electrode 22 is built in the trench 21. Gate electrode 22 is insulated from P body region 41 by gate insulating film 24 formed on the wall surface of trench 21. In the semiconductor device 200, a channel effect is generated in the P body region 41 by applying a voltage to the gate electrode 22, thereby controlling conduction between the N + source region 31 and the N + drain region 11.

In addition to the trench 21 in which the gate electrode 22 is incorporated, the semiconductor substrate is provided with trenches 25 and 25 on both sides of the trench 21. Each trench 25 is filled with an insulator. Further, a P floating region 54 which is in contact with the bottom of the trench 25 and is surrounded by the N drift region 12 is formed. The cross section of the P floating region 54 has a substantially circular shape centering on the bottom of the trench 25 as shown in the cross sectional view of FIG. In this specification, the trench for the gate electrode 22 is referred to as “trench 21”, and the trench for the P floating region 54 is referred to as “trench 25”.

  In the semiconductor device 200 of the present embodiment, similarly to the semiconductor device 100 of the first embodiment, by providing the P floating region 54, electric field peaks can be formed at two locations, and the maximum peak value can be reduced. Further, it has the following characteristics as compared with the semiconductor device 100 of the first embodiment. That is, since the structure of the gate electrode 22 is the same as the conventional one, its formation is easy. Further, the distance between the gate electrode 22 and the P floating region 54 is longer than that of the first semiconductor device 100. Therefore, it is easy to secure a current path and a low on-resistance can be achieved. Further, since the P floating region facing the gate electrode 22 is not provided, problems such as the influence of ion implantation and increase in on-resistance do not occur.

As with the semiconductor device 100 of the first embodiment, a plurality of P floating regions may be provided in the thickness direction of the semiconductor device. For example, as shown in FIG. 9, a two-stage P floating region may be used. In the semiconductor device 201 shown in FIG. 9, a trench 25 having a deeper depth than the semiconductor device 200 shown in FIG. 8 is provided. The trench 21 for the gate electrode 22 has the same depth as that of the semiconductor device 200 shown in FIG. In the semiconductor device 201, a P floating region 54 centering on the bottom of the trench 25 and a P floating region 55 located between the P floating region 54 and the P body region 41 are provided. As a result, electric field peaks can be formed at three locations, and higher breakdown voltage and lower on-resistance can be achieved.

  Further, as shown in FIG. 10, a trench 26 having a depth different from that of the trench 25 may be provided with the gate electrode 22 interposed therebetween. The inside of the trench 26 is also filled with an insulating material, and its bottom is located in the P floating region 56. That is, the P floating region 56 is provided at a position different from the P floating region 54 in the thickness direction. Therefore, similarly to the semiconductor device 201 illustrated in FIG. 9, a structure in which electric field peaks are provided at three positions can be obtained. Therefore, high breakdown voltage and low on-resistance can be achieved. In the semiconductor device 202, the pitch between the trenches is designed to be slightly narrower than that of the semiconductor device 201 in order to ensure that the depletion layers are connected in the width direction. In the semiconductor device 202, since there is one P floating region in contact with each trench, ion implantation and thermal diffusion treatment for forming each P floating region may be performed once. Therefore, characteristic degradation due to thermal diffusion treatment can be minimized. Moreover, since the filling process in each trench can be performed at a time, there are few manufacturing processes.

  The shape of each trench may be a mesh shape or a dot shape in addition to a stripe shape that is long in the depth direction of the drawing. In order to increase the breakdown voltage, a stripe shape as shown in FIG. 11 or a mesh shape as shown in FIG. 12 is effective.

Next, a manufacturing process of the semiconductor device 201 shown in FIG. 9 will be described with reference to FIG. The gate electrode 22 and the trench 21 in the semiconductor device 201 have a general structure and are formed by a known manufacturing method. First, as shown in FIG. 13A, a trench 25 that penetrates the P body region and reaches the bottom of the N drift region 12 is formed. Thereafter, ion implantation is performed from the bottom surface of the trench 25, and then thermal diffusion treatment is performed. As a result, a P floating region 55 is formed. Note that the semiconductor device 200 shown in FIG. 8 is manufactured by depositing an insulator in the trench 25 based on the semiconductor substrate in this state to form the source electrode and the drain electrode.

  Next, as shown in FIG. 13B, the trench 25 is dug down by performing etching again. Thereafter, ion implantation is performed again from the bottom surface of the trench 25. Next, as shown in FIG. 13C, an insulator 23 is deposited in the trench 21 by CVD. Thereafter, a thermal diffusion process is performed for both the baking of the insulator and the formation of the P floating region 54. Thereby, the P floating region 54 is formed. Finally, by forming the source electrode and the drain electrode, an insulated gate semiconductor device as shown in FIG. 13D, that is, the semiconductor device 201 is manufactured.

[Third embodiment]
An insulated gate semiconductor device 300 according to the third embodiment (hereinafter referred to as “semiconductor device 300”) has a structure shown in a sectional view of FIG. The feature of the semiconductor device 300 of this embodiment is that the P floating region is formed below the trench for the gate electrode and the trench for the P floating region. In this regard, the semiconductor device 100 (see FIG. 1) in which the P floating region is formed only under the gate electrode trench 21 (see FIG. 1), or the semiconductor device 200 in which the P floating region is formed only under the trench 25 for the P floating region (see FIG. 1). Different from FIG. In FIG. 14, components having the same symbols as those of the semiconductor device 100 shown in FIG. 1 and the semiconductor device 200 shown in FIG. 8 have the same functions as those components.

In the semiconductor device 300, the N + source region 31, the N + drain region 11, the P body region 41 and the N drift region 12 are provided in the same manner as the semiconductor device 100 of the first form and the semiconductor device 200 of the second form. Is provided. Further, a trench 21 formed by digging a part of the upper surface side of the semiconductor device 300 is provided. A deposited insulating layer 23 is formed at the bottom of the trench 21 by depositing an insulator. Further, on the deposited insulating layer 23, a gate electrode 22 is formed by conductor deposition. Gate electrode 22 is insulated from P body region 41 by gate insulating film 24 formed on the wall surface of trench 21. In the semiconductor device 200, a channel effect is generated in the P body region 41 by applying a voltage to the gate electrode 22, thereby controlling conduction between the N + source region 31 and the N + drain region 11.

In addition to the trench 21 in which the gate electrode 22 is built, the semiconductor substrate is provided with trenches 25 and 25 having a depth deeper than the trench 21 on both sides of the trench 21. The trench 25 is filled with an insulator. Further, P floating regions 51 and 54 surrounded by the N drift region 12 are formed. The cross sections of the P floating regions 51 and 54 have a substantially circular shape with the bottom of the trench 21 or the trench 25 as the center, as shown in the cross sectional view of FIG. In this specification, the P floating region where the bottom of the gate electrode trench 21 is located is referred to as “P floating region 51”, and the P floating region where the bottom of the P floating region trench 25 is located is referred to as “P floating region”. 54 ”.

Adjacent P floating regions 51 and 54 are arranged so as not to contact each other. This is because if the adjacent P floating regions are in contact with each other, the current path at the time of ON is narrowed and the ON resistance is increased. In addition, the P floating region 51 is located at a marginal position where a depletion layer extending downward from the PN junction between the P body region 41 and the N drift region 12 reaches the P floating region 51 before breakdown occurs at the time of OFF. Has been placed. This is because, since the breakdown voltage is proportional to the depth of the depletion layer, the breakdown voltage is lowered when the distance between the P body region 41 and the P floating region 51 is short. In addition, the P floating region 54 is disposed at a position where a depletion layer extending downward from the P floating region 51 reaches the P floating region 54 before breakdown occurs. This is also in order to achieve an optimum high breakdown voltage.

  In the semiconductor device 300 of this embodiment, P floating regions 51 and 54 are provided at the bottom of the trench 21 for the gate electrode and the bottom of the trench 25 for the P floating region, respectively, and the depths of the trench 21 and the trench 25 are increased. By making the difference, the structure is such that the electric field peaks are provided at three places, similar to the semiconductor device 201 shown in FIG. 9 and the semiconductor device 202 shown in FIG. Therefore, high breakdown voltage and low on-resistance are achieved.

  The P floating regions 51 and 54 are not necessarily limited to the arrangement in which the P floating region 51 is on the upper side and the P floating region 54 is on the lower side as in the semiconductor device 300 shown in FIG. For example, as shown in FIG. 15, the P floating region 51 may be disposed downward and the P floating region 54 may be disposed upward. Even in the semiconductor device 301 arranged in this way, electric field peaks can be formed at three locations, and the maximum peak value can be reduced.

14 and 15, unlike the semiconductor device 302 shown in FIG. 16, the depth of the gate electrode trench 21 and the depth of the P floating region trench 25 may be the same. Such a semiconductor device 302 has the following advantages. That is, both trenches can be formed in the same process. Therefore, the number of processes can be reduced. Furthermore, short distance between the adjacent P floating, N - even with a high concentration of the drift region 12 can connect reliably depletion. Therefore, a low on-resistance can be achieved. In addition, in order to increase the breakdown voltage in many P floating regions 51 and 54, the size of each P floating region 51 and 54 can be small. Therefore, the acceleration voltage at the time of ion implantation can be lowered, and damage due to ion implantation can be suppressed. In addition, the thickness of the epitaxial layer can be reduced as compared with semiconductor devices having different trench depths. Further, since the number of thermal diffusion processes is small, it is possible to suppress the diffusion of impurities more than necessary, and to suppress an increase in on-resistance due to the thermal diffusion process.

  Further, the shape of each trench of the semiconductor device 302 shown in FIG. 16 may be any of a stripe shape (see FIG. 11), a mesh shape (see FIG. 12), a dot shape, etc., as in the other semiconductor devices. . Since the density of each P floating region is high in the semiconductor device 302, the manufacturing margin such as size is larger than that of other structures. As an arrangement utilizing this advantage, it is better to form the trench 25 in a dot shape as shown in FIG. In this arrangement, since the P floating region 54 is partially cut, the current path is wide and the on-resistance can be reduced. In order to make the spread of the depletion layer uniform, the distance between the trenches is made uniform. Also, as shown in FIG. 18, by providing the trench 21 at the cut of the trench 25 to have a mesh shape, the area of the gate electrode 22 can be increased and the on-resistance can be reduced. Note that the AA cross section in FIG. 17 or the BB cross section in FIG. 18 corresponds to the semiconductor device 302 shown in FIG.

  Next, a manufacturing process of the semiconductor device 300 shown in FIG. 14 will be described with reference to FIG. Note that the gate electrode 22 and the trench 21 in the semiconductor device 300 have the same structure as that of the semiconductor device 100 of FIG. 1, and are formed by the manufacturing method shown in FIG. First, etching is performed again as shown in FIG. 19A to form a trench 25 having a depth deeper than that of the trench 21. Thereafter, a thermal oxidation process is performed to form an oxide film 95 on the wall surface of the trench 25. Next, ion implantation is performed again from the bottom surface of the trench 25. After the ion implantation, the oxide film 95 in the trench 25 is removed. If there is a problem of interface reference when embedding an oxide film, or if a thin oxide film is formed on the silicon surface and the embedding property of the insulator is better, a thin thermal oxide film of about 50 nm is used. It is preferable to embed an insulator after the formation. This is not necessary if the insulator surface is better embedded if the silicon surface is exposed.

  Next, an insulator is deposited in the trench 25. Thereafter, a thermal diffusion process is performed for both the baking of the insulator and the formation of the P floating region 54. As a result, a P floating region 54 having a different position in the thickness direction with respect to the P floating region 51 is formed. As a result, a deposited insulating layer 23 is formed in the trench 25 as shown in FIG. Finally, by forming a source electrode and a drain electrode, an insulated gate semiconductor device as shown in FIG. 19C, that is, a semiconductor device 300 is manufactured. Note that the semiconductor device 301 shown in FIG. 15 can be manufactured by the same process only by changing the depth of each trench.

  The trench 21 is formed first in the trench 21 for the gate electrode and the trench 25 for the P floating region. This is to reduce the thermal load. However, the trench 25 can be formed first by lowering the gate oxidation temperature or the like.

Next, a manufacturing process of the semiconductor device 302 shown in FIG. 16 will be described with reference to FIG. First, as shown in FIG. 20A, a trench 21 and a trench 25 are formed, which penetrate the P body region 41 and reach the bottom of the N drift region 12. Since each trench is formed at the same time, its depth is the same. Thereafter, a thermal oxidation process is performed to form an oxide film 95 on the wall surface of each trench. Thereafter, ion implantation is performed from the bottom of each trench. After the ion implantation, the oxide film 95 in each trench is removed. If there is a problem of interface reference when embedding an oxide film, or if a thin oxide film is formed on the silicon surface and the embedding property of the insulator is better, a thin thermal oxide film of about 50 nm is used. It is preferable to embed an insulator after the formation. This is not necessary if the insulator surface is better embedded if the silicon surface is exposed.

  Next, an insulator is deposited in each trench. Thereby, the deposited insulating layer 23 is formed in each trench. Thereafter, a thermal diffusion process is performed in combination with the baking of the insulator and the formation of the P floating region 51 and the P floating region 54. That is, the P floating region 51 and the P floating region 54 are formed together by a single thermal diffusion process. As a result, a P floating region 51 is formed below the trench 21 and a P floating region 54 is formed below the trench 25 as shown in FIG.

  Next, by etching the deposited insulating layer 23 in the trench 21, a part of the deposited insulating layer 23 is removed. Further, an oxide film 24 is formed on the wall surface of the trench 21 by thermal oxidation. This becomes the gate oxide film 24. Then, by depositing a conductor inside the trench 21, a gate electrode 22 built in the trench 21 as shown in FIG. 20C is formed. Finally, by forming a source electrode and a drain electrode, an insulated gate semiconductor device as shown in FIG. 20D, that is, a semiconductor device 302 is manufactured.

As described in detail above, in the semiconductor device 100 of the first embodiment (FIG. 1), the epitaxial layer (N drift region 12) is formed by one epitaxial growth process, and the epitaxial layer is further formed by ion implantation, thermal diffusion, and the like. The P body region 41 is formed in the layer. Then, the trench 21 is formed in the semiconductor substrate having the epitaxial layer, and the P floating region 51 is formed by performing ion implantation from the bottom of the trench. That is, when the P floating region 51 is formed, the epitaxial growth process may be performed only once. This is because a plurality of P floating regions 52 are formed in the thickness direction as in the semiconductor device 101 (FIG. 2), or a P floating region 53 is formed in the termination area as in the semiconductor device 102 (FIG. 3). The same applies to cases. Then, N when the gate voltage of the switch-off by the P floating region 51 - have been able to alleviate the concentration of the electric field as well as facilitate the depletion of the drift region 12. As a result, an insulated gate semiconductor device and a method for manufacturing the same that can be easily manufactured while achieving both high breakdown voltage and low on-resistance have been realized.

  Further, the deposited insulating layer 23 is formed in the trench 21. Thereby, the gate insulating film 24 and the gate electrode 22 can be formed without being affected by ion implantation. Thereby, deterioration of element characteristics and deterioration of reliability can be suppressed. Further, the upper end of the deposited insulating layer 23 is located above the upper end of the P floating region 51. Therefore, the facing of the gate electrode 22 and the P floating region 51 is suppressed. As a result, an increase in on-resistance can be prevented.

In the semiconductor device 101 (FIG. 2), the P floating region 52 is provided between the P body region 41 and the P floating region 51. Thereby, the peak of an electric field can be formed in three places, and the maximum peak value can be reduced more. Therefore, by providing the P floating region 52, higher breakdown voltage and lower on-resistance can be achieved.

  In the semiconductor device 102 (FIG. 3), the P floating region 53 is also provided in the termination area. As a result, a high breakdown voltage can be achieved in the terminal area as well as in the cell area. The P floating region 53 is formed in the same process as the P floating region 51 in the cell area. Further, the P floating region 53 requires less space than the conventional semiconductor device. Therefore, the size controllability is good and the semiconductor device itself is compact.

  In the semiconductor device 200 of the second embodiment (FIG. 8), the trench 25 for the P floating region is provided. A P floating region is not provided below the trench 21 in which the gate electrode 22 is built. Therefore, problems such as the influence of ion implantation and increase in on-resistance do not occur. The P floating region 54 is provided below the trench 25 formed for the P floating region. Therefore, there is no need to consider the position and size of the gate electrode 22, and the degree of freedom in design is high. Further, the distance between the gate electrode 22 and the P floating region 54 is longer than that of the first semiconductor device 100. As a result, it is possible to increase the breakdown voltage as in the case of the semiconductor device 100 of the first embodiment, to easily secure a current path, and to reduce the on-resistance.

In the semiconductor device 201 (FIG. 9), a P floating region 55 is provided at a position between the P body region 41 and the P floating region 54. As a result, electric field peaks can be formed at three locations, and the maximum peak value can be further reduced. In the semiconductor device 202 (FIG. 10), the trenches 25 having different depths are provided, and one P floating region 54 is provided below each trench. As a result, it is possible to minimize the deterioration of characteristics due to the thermal diffusion treatment, and to achieve a high breakdown voltage and a low on-resistance.

  Further, in the semiconductor device 300 of the third embodiment (FIG. 14), the trench 21 for the gate electrode and the trench 25 for the P floating region are provided, and the P floating regions 51 and 54 are respectively provided below both trenches. It is said. Further, the depth of the trench 21 and the depth of the trench 25 are made different. As a result, electric field peaks can be formed at a plurality of locations, and the maximum peak value can be further reduced.

  In the semiconductor device 302 (FIG. 16), the depth of the trench 21 and the depth of the trench 25 are made the same. In the semiconductor device 302, the trench 21 and the trench 25 can be formed in the same process. Therefore, the number of processes can be reduced. In addition, since the number of thermal diffusion processes is small, the diffusion of impurities is small, and the decrease in on-resistance due to the thermal diffusion process can be suppressed.

  Note that this embodiment is merely an example, and does not limit the present invention. Therefore, the present invention can naturally be improved and modified in various ways without departing from the gist thereof. For example, for each semiconductor region, P-type and N-type may be interchanged. Further, the gate insulating film 24 is not limited to an oxide film, and may be another type of insulating film such as a nitride film or a composite film. Also, the semiconductor is not limited to silicon, but may be other types of semiconductors (SiC, GaN, GaAs, etc.).

  Further, in the semiconductor device 102 shown in FIG. 3, the trench 62 in the termination area is completely filled with an insulator. However, like the trench 21 in the cell area, a part of the insulator is removed and the conductor is removed. May be deposited. In this case, the conductor in the trench 62 is not electrically connected to the gate wiring. Even in such a semiconductor device, it is possible to increase the breakdown voltage of the termination area with a small number of processes.

  The insulated gate semiconductor device of the embodiment can also be applied to a conductivity-modulated power MOS using a P-type substrate 13 as shown in FIG.

In addition to the characteristics described so far, the insulated gate semiconductor device of the embodiment has the following characteristics. That is, since holes accumulate in the P floating region 51, the P floating region 51 becomes a hole supply source. As a result, the concentration of holes in the surface region of the N drift region 12, specifically, the region located above the P floating region 51 can be increased. Therefore, the loss can be reduced. Further, since the deposited insulating layer 23 is formed below the gate electrode 22, the gate-drain capacitance (Cgd) is small. Therefore, transmission prevention and driving loss can be reduced.

Further, since a depletion layer is formed also from the P floating region 51, the breakdown voltage at the time of load short-circuiting is improved. In other words, in a conventional insulated gate semiconductor device having no P floating region 51, a depletion from the PN junction between the P body region 41 and the N drift region 12 to the drain side occurs as shown in FIG. A layer 15 is formed, and current flows in a region below the trench 21 (see the arrow in FIG. 22). On the other hand, in the insulated gate semiconductor device 100 of this embodiment, the deposited insulating layer 23 is formed under the gate electrode 22, and a current flows along the trench 21 as shown in FIG. A depletion layer 15 is also formed from the P floating region 51. Therefore, the current path when the load is short-circuited is very narrow (see the arrow in FIG. 23). As a result, the short-circuit current is reduced and the withstand voltage when the load is short-circuited is improved.

Further, the present invention can also be applied to a power MOS in which an N hole barrier region 18 acting as a hole barrier is formed between the P body region 41 and the N drift region 12 as shown in FIG. is there. In the case of the power MOS in which the N hole barrier region 18 is formed, the depletion layer spreads narrowly in the N hole barrier region 18. As a result, the breakdown voltage may be reduced. However, in the power MOS provided with the P floating region 51 as in this embodiment, in addition to the depletion layer formed from the PN junction between the P body region 41 and the N drift region 12, However, since a depletion layer is formed, a decrease in breakdown voltage is suppressed.

It is sectional drawing which shows the structure of the insulated gate semiconductor device which concerns on a 1st form. It is sectional drawing which shows the structure of the insulated gate semiconductor device (two-stage P floating area | region) which concerns on a 1st form. It is sectional drawing which shows the structure of the termination | terminus part of the insulated gate semiconductor device which concerns on a 1st form. It is a figure which shows the manufacturing process of the insulated gate semiconductor device of FIG. FIG. 3 is a diagram showing a manufacturing process of the insulated gate semiconductor device of FIG. 2. It is a graph which shows the relationship between the voltage between drain-source, and an electric current (a gate voltage is constant). It is a graph which shows the relationship between the voltage between drain-sources for every gate voltage, and an electric current. It is sectional drawing which shows the structure of the insulated gate semiconductor device which concerns on a 2nd form. It is sectional drawing which shows the structure of the insulated gate semiconductor device (two-stage P floating area | region) which concerns on a 2nd form. It is sectional drawing which shows the structure of the insulated gate semiconductor device (P floating area | region from which the position of thickness direction differs) which concerns on a 2nd form. It is a top view which shows the arrangement | sequence of the insulated gate semiconductor device provided with the stripe-shaped trench. It is a top view which shows the arrangement | sequence of the insulated gate semiconductor device provided with the mesh-shaped trench. FIG. 10 is a diagram showing a manufacturing process of the insulated gate semiconductor device of FIG. 9. It is sectional drawing which shows the structure of the insulated gate semiconductor device which concerns on a 3rd form. It is sectional drawing which shows the structure (P floating area | region from which the position of a thickness direction differs) of the insulated gate semiconductor device which concerns on a 3rd form. It is sectional drawing which shows the structure (P floating region where the position of the thickness direction is the same) of the insulated gate semiconductor device which concerns on a 3rd form. It is a top view which shows the arrangement | sequence (the 1) of the insulated gate semiconductor device provided with the dot-shaped trench. It is a top view which shows the array (the 2) of the insulated gate semiconductor device provided with the dot-shaped trench. It is a figure which shows the manufacturing process of the insulated gate semiconductor device of FIG. FIG. 17 is a diagram showing a manufacturing process of the insulated gate semiconductor device of FIG. 16. It is sectional drawing which shows the structure of a conductivity modulation type semiconductor device. It is a figure which shows the electric current path at the time of the load short circuit in the conventional insulated gate semiconductor device. It is a figure which shows the electric current path at the time of the load short circuit in the insulated gate semiconductor device of embodiment. It is sectional drawing which shows the structure (the 1) of the insulated gate semiconductor device in which the hole barrier layer was formed. It is sectional drawing which shows the structure (the 2) of the insulated gate semiconductor device in which the hole barrier layer was formed. It is sectional drawing which shows the structure of the conventional insulated gate semiconductor device (the 1). It is sectional drawing which shows the structure of the conventional insulated gate semiconductor device (the 2). It is sectional drawing which shows the termination | terminus structure of the conventional insulated gate semiconductor device.

Explanation of symbols

11 N + drain region 12 N drift region (drift region)
21 trench (trench part)
22 Gate electrode 23 Deposited insulating layer 24 Gate insulating film 25 Trench (auxiliary trench portion)
26 trench (second auxiliary trench part)
31 N + source region 41 P - body region (body region)
51 P floating area (floating area)
52 P floating area (intermediate floating area)
53 P floating area (terminal floating area)
54 P floating area (auxiliary floating area)
55 P floating area (intermediate auxiliary floating area)
56 P floating area (second auxiliary floating area)
62 Trench (Terminal Trench)

Claims (12)

  1. A body region that is a first conductivity type semiconductor located on the upper surface side in the semiconductor substrate, a drift region that is in contact with the lower surface of the body region and is a second conductivity type semiconductor, and penetrates the body region from the upper surface of the semiconductor substrate; In an insulated gate semiconductor device having a trench portion whose bottom is located below the lower surface of the body region,
    A floating region surrounded by the drift region and being a first conductivity type semiconductor;
    The bottom of the trench is located in the floating region;
    In the trench part,
    A deposited insulating layer formed by depositing an insulator;
    A gate electrode located on the deposited insulating layer and facing the body region is formed;
    The upper end of the deposited insulating layer is located above the upper end of the floating region ,
    The interval between the lower surface of the body region and the upper end of the floating region is wider than the interval between the lower end of the deposited insulating layer and the lower end of the floating region,
    The gap between the lower end of the gate electrode and the lower end of the deposited insulating layer is wider than the gap between the lower surface of the body region and the upper end of the floating region,
    2. The insulated gate semiconductor device according to claim 1, wherein the thickness of the deposited insulating layer is such that electric field peaks are formed in at least two places in the thickness direction.
  2. The insulated gate semiconductor device according to claim 1,
    An intermediate floating region that is located above the upper end of the floating region, is surrounded by the drift region and is a first conductivity type semiconductor,
    The trench portion passes through the intermediate floating region,
    An insulated gate semiconductor device, wherein an upper end of the deposited insulating layer is located above an upper end of the intermediate floating region.
  3. The insulated gate semiconductor device according to claim 1,
    An auxiliary trench portion penetrating the body region from the upper surface of the semiconductor substrate, the bottom portion thereof being located below the lower surface of the body region, and the inside being filled with an insulator;
    An auxiliary floating region that is surrounded by the drift region and is a first conductivity type semiconductor;
    2. The insulated gate semiconductor device according to claim 1, wherein a bottom portion of the auxiliary trench portion is located in the auxiliary floating region.
  4. In the insulated gate semiconductor device according to claim 3,
    2. The insulated gate semiconductor device according to claim 1, wherein a depth of the trench portion is different from a depth of the auxiliary trench portion.
  5. In the insulated gate semiconductor device according to claim 3,
    2. The insulated gate semiconductor device according to claim 1, wherein a depth of the trench portion and a depth of the auxiliary trench portion are the same.
  6. In the insulated gate semiconductor device according to any one of claims 1 to 5 ,
    An auxiliary trench portion penetrating the body region from the upper surface of the semiconductor substrate, the bottom portion thereof being located below the lower surface of the body region, and the inside being filled with an insulator;
    An auxiliary floating region that is surrounded by the drift region and is a first conductivity type semiconductor;
    2. The insulated gate semiconductor device according to claim 1, wherein a bottom portion of the auxiliary trench portion is located in the auxiliary floating region.
  7. In the insulated gate semiconductor device according to claim 6,
    The auxiliary floating region is located above the upper end of the auxiliary floating region, and is surrounded by the drift region and has an auxiliary intermediate floating region that is a first conductivity type semiconductor,
    The auxiliary trench portion passes through the intermediate auxiliary floating region,
    An insulated gate semiconductor device, wherein an upper end of the deposited insulating layer is located above an upper end of the intermediate auxiliary floating region.
  8. In the insulated gate semiconductor device according to claim 6,
    A second auxiliary which is opposed to the auxiliary trench portion with the gate electrode interposed therebetween, penetrates the body region from the upper surface of the semiconductor substrate, has a bottom portion located below the lower surface of the body region, and is filled with an insulator inside. A trench,
    A second auxiliary floating region that is surrounded by the drift region and is a first conductivity type semiconductor;
    2. The insulated gate semiconductor device according to claim 1, wherein the auxiliary trench part and the second auxiliary trench part have different depths.
  9. In the insulated gate semiconductor device according to claim 3 or 6,
    2. The insulated gate semiconductor device according to claim 1, wherein the auxiliary trench portion is formed in a dot shape when viewed from above the semiconductor substrate.
  10. In the insulated gate semiconductor device according to any one of claims 1 to 9,
    A termination trench located in the peripheral region of the cell region and filled with an insulator inside;
    A terminal floating region that is surrounded by the drift region and is a first conductivity type semiconductor;
    2. The insulated gate semiconductor device according to claim 1, wherein a bottom portion of the termination trench portion is located in the termination floating region.
  11. A body region which is located on the upper surface side of the semiconductor substrate and is a first conductivity type semiconductor, a drift region which is in contact with the lower surface of the body region and is a second conductivity type semiconductor, and is surrounded by the drift region and the first conductivity type semiconductor a floating region is a trench portion positioned in the floating region its bottom through the body region from the upper surface of the semiconductor substrate is a lower than the body region, located on the inside of the trench portion, the floating region and in contact with, an insulating material and formed by depositing deposited insulating layer, located on the inside of the trench portion have a gate electrode that faces the body region, the upper end of the deposited insulating layer, an upper end of the floating region The distance between the lower surface of the body region and the upper end of the floating region is higher than the lower end of the deposited insulating layer and the floating region. A gap between the lower end of the gate region and the lower end of the deposited insulating layer is wider than an interval between the lower surface of the body region and the upper end of the floating region; thickness, in the thickness direction, in the manufacturing method of the thickness of the insulated gate semiconductor device in which the peak of the electric field is formed in at least two positions,
    A trench part forming step of forming the trench part in the semiconductor substrate in which the drift region and the body region are formed;
    An impurity implantation step of implanting impurities from the bottom of the trench portion formed in the trench portion formation step;
    An insulator deposition step of depositing an insulator in the trench portion after implanting impurities in the impurity implantation step;
    And a floating region forming step of forming a floating region by performing a thermal diffusion process after depositing the insulator in the insulator depositing step.
  12. In the manufacturing method of the insulated gate semiconductor device according to claim 11,
    A trench deep-drilling step of further digging the bottom of the trench after injecting impurities in the impurity implantation step;
    A method of manufacturing an insulated gate semiconductor device, comprising: an impurity re-injection step of injecting impurities again from the bottom of the trench portion dug down in the trench portion deep-drilling step.
JP2003375098A 2003-11-05 2003-11-05 Insulated gate semiconductor device and manufacturing method thereof Active JP4500530B2 (en)

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JP2003375098A JP4500530B2 (en) 2003-11-05 2003-11-05 Insulated gate semiconductor device and manufacturing method thereof
PCT/JP2004/015179 WO2005036650A2 (en) 2003-10-08 2004-10-06 Insulated gate type semiconductor device and manufacturing method thereof
US10/573,793 US7470953B2 (en) 2003-10-08 2004-10-06 Insulated gate type semiconductor device and manufacturing method thereof
EP04792407.1A EP1671374B1 (en) 2003-10-08 2004-10-06 Insulated gate type semiconductor device and manufacturing method thereof
KR1020067006685A KR100767078B1 (en) 2003-10-08 2004-10-06 Insulated gate type semiconductor device and manufacturing method thereof

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