CN102117799B - Buried multi-chip semiconductor package structure and manufacturing method thereof - Google Patents

Buried multi-chip semiconductor package structure and manufacturing method thereof Download PDF

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Publication number
CN102117799B
CN102117799B CN2010105760525A CN201010576052A CN102117799B CN 102117799 B CN102117799 B CN 102117799B CN 2010105760525 A CN2010105760525 A CN 2010105760525A CN 201010576052 A CN201010576052 A CN 201010576052A CN 102117799 B CN102117799 B CN 102117799B
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chip
electric connection
connection pads
line layer
semiconductor package
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CN102117799A (en
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府玠辰
欧英德
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

The invention relates to a buried multi-chip semiconductor package structure and a manufacturing method thereof. The buried multi-chip semiconductor package structure comprises a first chip, at least one second chip, a first circuit layer and a second circuit layer, wherein the first chip is provided with a first surface, a second surface and at least one groove; the at least one groove is formed on the second surface; and the at least one second chip is provided with an active surface and a plurality of second electrical connecting pads and is arranged in the at least one groove. Since the at least one second chip is arranged in the at least one groove of the first chip, the height and the area of the buried multi-chip semiconductor package structure are not increased, and the miniaturization of a product can be facilitated.

Description

Baried type multi-chip semiconductor package structure and manufacture method thereof
Technical field
The present invention is about a kind of semiconductor package and manufacture method thereof, in detail, and about a kind of baried type multi-chip semiconductor package structure and manufacture method thereof.
Background technology
Known baried type multi-chip semiconductor package structure is imbedded in this substrate in several chip buried substrates these chip by chip, therefore, so that the area change of the x-y in-plane of known baried type multi-chip semiconductor package structure.
Another kind of stacked-type semiconductor package is with several chip stacks, for example: micro electronmechanical semiconductor chip (MEMS) storehouse to drives on the chip (ASIC), and connects with wire.Yet stack chip causes the height of semiconductor package to increase, and is unfavorable for the microminiaturization of product.
Therefore, be necessary to provide a kind of baried type multi-chip semiconductor package structure and manufacture method thereof, to address the above problem.
Summary of the invention
The invention provides a kind of baried type multi-chip semiconductor package structure, comprising: one first chip, at least one the second chip, one first line layer and one second line layer.This first chip has a first surface, a second surface, at least one groove and several the first electric connection pads, this second surface is with respect to this first surface, this at least one groove is arranged at this second surface, and these first electric connection pads are arranged at this first surface.At least one the second chip has an active surface and several the second electric connection pads, and these second electric connection pads are arranged at this active surface, and this at least one second chip is arranged in this at least one groove, appears this active surface and these the second electric connection pads.This first line layer is in order to be electrically connected these the first electric connection pads.This second line layer is in order to be electrically connected these the second electric connection pads.
The present invention provides a kind of manufacture method of baried type multi-chip semiconductor package structure in addition, comprise: (a) form at least one groove in a second surface of one first chip, this first chip comprises a first surface and several the first electric connection pads in addition, and these first electric connection pads are arranged at this first surface; (b) at least one the second chip is set in this at least one groove, this at least one second chip has an active surface and several the second electric connection pads, and these second electric connection pads are arranged at this active surface; Reach and (c) form one first line layer and one second line layer, in order to be electrically connected respectively these first electric connection pads and these the second electric connection pads.
Because this at least one second chip of the present invention is arranged in this at least one groove of this first chip, so can not increase height and the area of baried type multi-chip semiconductor package structure of the present invention, can be conducive to the microminiaturization of product.
Description of drawings
Fig. 1 to 11 shows the schematic diagram of the manufacture method of first embodiment of the invention baried type multi-chip semiconductor package structure, and wherein Figure 11 shows the schematic diagram of first embodiment of the invention baried type multi-chip semiconductor package structure;
Figure 12 shows the schematic diagram of second embodiment of the invention baried type multi-chip semiconductor package structure;
Figure 13 to 22 shows the schematic diagram of the manufacture method of third embodiment of the invention baried type multi-chip semiconductor package structure, and wherein Figure 22 shows the schematic diagram of third embodiment of the invention baried type multi-chip semiconductor package structure.
Embodiment
Referring to figs. 1 to 11, it shows the schematic diagram of the manufacture method of first embodiment of the invention baried type multi-chip semiconductor package structure.At first with reference to figure 1, one first chip 11 is set in one first carrier 15, in the present embodiment, this first chip 11 attaches on this first carrier 15 with viscose 14.This first chip 11 has a first surface 111, a second surface 112 and several the first electric connection pads 113, and this second surface 112 is with respect to this first surface 111, and these first electric connection pads 113 are arranged at this first surface 111.In the present embodiment, this first surface 111 is an active surface.Then, define a patterning photoresist layer 12 in this second surface 112.
With reference to figure 2, according to this this first chip 11 of patterning photoresist layer 12 etchings to form at least one perforation 114 to these the first electric connection pads 113.With reference to figure 3, electroplate a bronze medal layer 16 in this second surface 112 of this first chip 11 and the periphery of at least one perforation 114.With reference to figure 4, remove the copper layer 16 at this second surface 112 of this first chip 11, in the present embodiment, in the cmp mode, remove the copper layer 16 at this second surface 112 of this first chip 11.Insert again the first insulating material 17 in the space of 16 on the copper layer of the periphery of at least one perforation 114.In the present embodiment, the first insulating material 17 is polymer (polymer).
With reference to figure 5, form at least one groove 115 in this second surface 112 of this first chip 11, and form at least one annular groove 116 in copper layer 16 periphery of the periphery of at least one perforation 114, in the present embodiment, form at least one groove 115 and at least one annular groove 116 with etching.
With reference to figure 6, at least one the second chip 21 is set in this at least one groove 115, this at least one second chip 21 has an active surface 211 and several the second electric connection pads 212, these second electric connection pads 212 are arranged at this active surface 211, and appear these second electric connection pads 212 and this active surface 211.In the present embodiment, stick at least one the second chip 21 in this at least one groove 115 with viscose 13.
With reference to figure 7, insert the second insulating material 18 at least one annular groove 116, make this copper layer 16 and these the first chip 11 isolation, to form a perforating holes 19.This perforating holes 19 comprises this copper layer 16, this first insulating material 17 and this second insulating material 18.In addition, this second insulating material 18 is inserted at least one groove 115 interior these second chips 21 spaces in addition.
With reference to figure 8, form one second line layer 22, comprise one second insulating barrier 23 and one second metal level 221, in order to be electrically connected these second electric connection pads 212 and at least one perforating holes 19.Wherein, this this second metal level 221 of the second insulating barrier 23 covered sections, and expose portion the second metal level 221 are with as outside connection gasket.
With reference to figure 9, viscose 14 and the first carrier 15 with Fig. 8 removes first, is inverted this first chip 11 again, makes this first surface 111 of this first chip 11 up, and utilizes viscose 24 to be arranged on the Second support 25.With reference to Figure 10, form one first line layer 26, comprise one first insulating barrier 27 and a first metal layer 261, in order to be electrically connected these first electric connection pads 113 and at least one perforating holes 19.Wherein, this first metal layer 261 of the first insulating barrier 27 covered sections, and this first metal layer 261 of expose portion are with as outside connection gasket.
With reference to Figure 11, several soldered balls 28 are set to be electrically connected the first line layer 26.First embodiment of the invention baried type multi-chip semiconductor package structure 10 comprises this first chip 11, this second chip 21, this first line layer 26, this second line layer 22 and several soldered balls 28.
This first chip 11 has this first surface 111, this second surface 112, at least one groove 115 and several the first electric connection pads 113, this second surface 112 is with respect to this first surface 111, this at least one groove 115 is arranged at this second surface 112, and these first electric connection pads 113 are arranged at this first surface 111.
This second chip 21 has this active surface 211 and several the second electric connection pads 212.These second electric connection pads 212 are arranged at this active surface 211, and this second chip 21 is arranged in this groove 115.This first line layer 26 is in order to be electrically connected these the first electric connection pads 113.This second line layer 22 is in order to be electrically connected these the second electric connection pads 212.These soldered balls 28 are in order to be electrically connected this first line layer 26.
In the present embodiment, this first chip 11 has at least one perforating holes 19, runs through this first chip 11, and is electrically connected these the first electric connection pads 113.This first line layer 26 is electrically connected this at least one perforating holes 19, and this second line layer 22 is electrically connected this at least one perforating holes 19, in order to do so that this first chip 11 and 21 electric connections of this second chip.
Because this second surface 112 at this first chip 11 forms this groove 115, this second chip 21 can be arranged in this groove 115 of this first chip 11, so it is all identical with this first chip 11 to imbed rear whole height or area, can not increase height and the area of baried type multi-chip semiconductor package structure 10 of the present invention, can be conducive to the microminiaturization of product.
With reference to Figure 12, it shows the schematic diagram of second embodiment of the invention baried type multi-chip semiconductor package structure.Second embodiment of the invention baried type multi-chip semiconductor package structure 30 comprises this first chip 31, this second chip 32, this first line layer 33, this second line layer 34 and several soldered balls 37.Second embodiment of the invention baried type multi-chip semiconductor package structure 30 is with first embodiment of the invention baried type multi-chip semiconductor package structure 10 differences, this second line layer 34, comprise several wires 341 and an encapsulating material 342, be electrically connected this at least one perforating holes 311 and these the second electric connection pads 321.
With reference to figures 13 to 22, it shows the schematic diagram of the manufacture method of third embodiment of the invention baried type multi-chip semiconductor package structure.At first with reference to Figure 13, it shows a wafer 50, this wafer 50 has several the first chips 51, each first chip 51 has a first surface 511, a second surface 512 and several the first electric connection pads 513, this second surface 512 is with respect to this first surface 511, and these first electric connection pads 513 are arranged at this first surface 511.In the present embodiment, this first surface 511 is an active surface.
With reference to Figure 14, form at least one groove 515 in this second surface 512 of this first chip 51.With reference to Figure 15, coating viscose 53 is in these grooves 515.With reference to Figure 16, at least one the second chip 52 is set in this at least one groove 515, each second chip 52 has an active surface 521 and several the second electric connection pads 522, these second electric connection pads 522 are arranged at this active surface 521, and appear these second electric connection pads 522 and this active surface 521 in this second surface 512.Cut this wafer 50 again, make into independent chipset 54, wherein this chipset 54 comprises one first chip 51 and one second chip 52.
With reference to Figure 17, it shows that a substrate 71 utilizes viscose 72 to be arranged on one first carrier 73.This substrate 71 has at least one spatial accommodation 711 and at least one perforating holes 712.This perforating holes 712 runs through this substrate 71, and each perforating holes 712 has one first insulating material 713, one second insulating material 714 and a conductive layer 715.Wherein, this conductive layer 715 is arranged between this first insulating material 713 and this second insulating material 714, and these the second insulating material 714 usefulness are so that this conductive layer 715 and these substrate 71 electrical isolation.
With reference to Figure 18, this chipset 54 is set in this spatial accommodation 711 of this substrate 71.Wherein this first surface 511 of this first chip 51 up, and this second surface 512 of this first chip 51 is down.In the present embodiment, first this second chip 52 is arranged at this first chip 51, after forming a chipset 54, again this first chip 51 of this chipset 54 is arranged at the spatial accommodation 711 of this substrate 71.At other embodiment, can first this first chip 51 be arranged at the spatial accommodation 711 of this substrate 71, this second surface 512 in this first chip forms groove again, the second chip 52 is arranged in this groove again.At other embodiment, also can be first this second surface 512 of this first chip 51 be formed grooves, and be arranged at the spatial accommodation 711 of this substrate 71 in this first chip 51 after, again the second chip 52 is arranged in this groove.
With reference to Figure 19, form one first line layer 81, comprise one first insulating barrier 83 and a first metal layer 811, in order to be electrically connected these first electric connection pads 513 and at least one perforating holes 712.Wherein, this this first metal layer 811 of the first insulating barrier 83 covered sections and expose portion the first metal layer 811.Form again several the first outside connection gaskets 85, be electrically connected the part the first metal layer 811 of this exposure.
With reference to Figure 20, viscose 72 and this first carrier 73 with Figure 19 removes first, is inverted this substrate 71 again, utilizes viscose 74 this substrate 71 to be set on a Second support 75.Form one second line layer 82, comprise one second insulating barrier 84 and one second metal level 821, in order to be electrically connected these second electric connection pads 522 and at least one perforating holes 712.Wherein, this this second metal level 821 of the second insulating barrier 84 covered sections and expose portion the second metal level 821.Form again several the second outside connection gaskets 86, be electrically connected part second metal level 821 of this exposure.
With reference to Figure 21, several second soldered balls 88 are set on these second outside connection gaskets 86.Afterwards viscose 74 and this Second support 75 are removed and arrange several first soldered balls 87 on these first outside connection gaskets 85.
With reference to Figure 22, behind cutting step, finish third embodiment of the invention baried type multi-chip semiconductor package structure 80.In the present embodiment, after being set, several second soldered balls 88 and several the first soldered balls 87 carry out cutting step; At other embodiment, also can carry out first cutting step, and after cutting, those second soldered balls 88 and those the first soldered balls 87 are set again.Third embodiment of the invention baried type multi-chip semiconductor package structure 80 comprises this first chip 51, this second chip 52, this substrate 71, this first line layer 81, this second line layer 82, several first soldered balls 87 and several the second soldered balls 88.
This first chip 51 has this first surface 511, this second surface 512, at least one groove 515 and several the first electric connection pads 513, this second surface 512 is with respect to this first surface 511, this at least one groove 515 is arranged at this second surface 512, and these first electric connection pads 513 are arranged at this first surface 511.
This second chip 52 has this active surface 521 and several the second electric connection pads 522.These second electric connection pads 522 are arranged at this active surface 521, and this second chip 52 is arranged in this groove 515 to form a chipset 54.
This substrate 71 has at least one perforating holes 712 and a spatial accommodation 711, and this chipset 54 is arranged at this spatial accommodation 711 of this substrate 71.This first line layer 81 is in order to be electrically connected these first electric connection pads 513 and at least one perforating holes 712, this second line layer 82 is in order to be electrically connected these second electric connection pads 522 and at least one perforating holes 712, in order to do so that this first chip 51 can be electrically connected with this substrate 71 respectively with this second chip 52, perhaps this first chip 51 can be electrically connected with this second chip 52.
Because this second surface 512 at this first chip 51 forms this groove 515, this second chip 52 can be arranged in this groove 515 of this first chip 51, to form a chipset 54, again this chipset 54 is arranged at this spatial accommodation 711 of this substrate 71, after so this chipset 54 is imbedded this substrate 71, whole height or area are all identical with this substrate 71, can not increase height and the area of baried type multi-chip semiconductor package structure 80 of the present invention, can be conducive to the microminiaturization of product.
Only above-described embodiment only is explanation principle of the present invention and effect thereof, but not in order to limit the present invention.Therefore, practise above-described embodiment being made amendment and changing in the personage of this technology and still do not take off spirit of the present invention.Interest field of the present invention should be listed such as claims.

Claims (7)

1. baried type multi-chip semiconductor package structure comprises:
One first chip, have a first surface, a second surface, at least one groove and several the first electric connection pads, this second surface is with respect to this first surface, and this at least one groove is arranged at this second surface, and these first electric connection pads are arranged at this first surface;
At least one the second chip has an active surface and several the second electric connection pads, and these second electric connection pads are arranged at this active surface, and this at least one second chip is arranged in this at least one groove, appears this active surface and these the second electric connection pads;
One first line layer is in order to be electrically connected these the first electric connection pads; And
One second line layer is in order to be electrically connected these the second electric connection pads;
Wherein this first chip has at least one perforating holes, run through this first chip, this first line layer is electrically connected this at least one perforating holes, and this second line layer is electrically connected this at least one perforating holes, and this at least one perforating holes comprises a bronze medal layer, one first insulating material and one second insulating material.
2. baried type multi-chip semiconductor package structure as claimed in claim 1, other comprises a substrate, this first chip is arranged at this substrate.
3. baried type multi-chip semiconductor package structure as claimed in claim 2, wherein this substrate comprises at least one perforating holes, runs through this substrate.
4. baried type multi-chip semiconductor package structure as claimed in claim 3, wherein this first line layer is electrically connected this at least one perforating holes, this this at least one perforating holes of second line layer electric connection.
5. the manufacture method of a baried type multi-chip semiconductor package structure comprises:
(a) form at least one groove in a second surface of one first chip, this first chip comprises a first surface and several the first electric connection pads in addition, and these first electric connection pads are arranged at this first surface;
(b) at least one the second chip is set in this at least one groove, this at least one second chip has an active surface and several the second electric connection pads, and these second electric connection pads are arranged at this active surface; And
(c) form one first line layer and one second line layer, in order to be electrically connected respectively these first electric connection pads and these the second electric connection pads;
Wherein this step (a) is front comprises that in addition one forms at least one perforating holes in the step of this first chip, and this at least one perforating holes runs through this first chip; And this first line layer is electrically connected this at least one perforating holes in this step (c), and this second line layer is electrically connected this at least one perforating holes.
6. manufacture method as claimed in claim 5 comprises in addition after this step (b) that wherein one arranges this first chip in the step of a substrate.
7. manufacture method as claimed in claim 6 comprises in addition after this step (b) that wherein one forms at least one perforating holes in the step of this substrate, and this at least one perforating holes runs through this substrate; And this first line layer is electrically connected this at least one perforating holes in this step (c), and this second line layer is electrically connected this at least one perforating holes.
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Citations (2)

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Publication number Priority date Publication date Assignee Title
CN101232008A (en) * 2007-01-03 2008-07-30 育霈科技股份有限公司 Multi-chips package and method of forming the same
CN101789380A (en) * 2009-01-23 2010-07-28 日月光半导体制造股份有限公司 Structure and process of internally buried package

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101232008A (en) * 2007-01-03 2008-07-30 育霈科技股份有限公司 Multi-chips package and method of forming the same
CN101789380A (en) * 2009-01-23 2010-07-28 日月光半导体制造股份有限公司 Structure and process of internally buried package

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