CN108122885A - A kind of semiconductor devices and preparation method thereof, electronic device - Google Patents
A kind of semiconductor devices and preparation method thereof, electronic device Download PDFInfo
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- CN108122885A CN108122885A CN201611067310.0A CN201611067310A CN108122885A CN 108122885 A CN108122885 A CN 108122885A CN 201611067310 A CN201611067310 A CN 201611067310A CN 108122885 A CN108122885 A CN 108122885A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
- H01L23/5223—Capacitor integral with wiring layers
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76832—Multiple layers
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/7687—Thin films associated with contacts of capacitors
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1005—Formation and after-treatment of dielectrics
- H01L2221/1052—Formation of thin functional dielectric layers
- H01L2221/1057—Formation of thin functional dielectric layers in via holes or trenches
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1068—Formation and after-treatment of conductors
- H01L2221/1073—Barrier, adhesion or liner layers
- H01L2221/1078—Multiple stacked thin films not being formed in openings in dielectrics
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Abstract
The present invention provides a kind of semiconductor devices and preparation method thereof, electronic devices.The semiconductor devices includes：Semiconductor substrate；Silicon hole capacitor is arranged in the Semiconductor substrate, and the silicon hole capacitor includes：Silicon hole main body as interior electrode；Barrier layer, threshold voltage adjustments layer and insulating layer are set in turn in the outside of the silicon hole main body from the inside to the outside, wherein the formation process on the barrier layer, the threshold voltage adjustments layer and the insulating layer is compatible；As the first doped region of external electrode, the outside of the insulating layer is arranged at, to be formed the silicon hole capacitor with the silicon hole main body, the barrier layer, the threshold voltage adjustments layer and the insulating layer.The threshold voltage adjustments layer can be formed by the method for atomic layer deposition, more compatible with the preparation process on the barrier layer and the insulating layer, make preparation process simpler easy.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of semiconductor devices and preparation method thereof, electronics
Device.
Background technology
In consumer electronics field, multifunctional equipment is increasingly liked be subject to consumer, compared to the simple equipment of function,
Multifunctional equipment manufacturing process will be more complicated, than the chip if desired for integrated multiple and different functions in circuit version, thus go out
3D integrated circuits (integrated circuit, IC) technology, 3D integrated circuits (integrated circuit, IC) quilt are showed
A kind of system-level integrated morphology is defined as, multiple chips are stacked in vertical plane direction, so as to save space.
Therefore, at present in the 3D IC technologies mostly using silicon hole (Through Silicon Via, TSV), silicon
Through hole is a kind of perpendicular interconnection for penetrating Silicon Wafer or chip, TSV can storehouse multi-plate chip, drilling out duck eye in chip, (processing procedure is again
First drilling and rear two kinds of drilling, Via Fist, Via Last can be divided into), enter metal from underfill, on Silicon Wafer with etching or
Laser mode drills (via), then is filled up with the conductive material such as substances such as copper, polysilicon, tungsten, so as to fulfill between different silicon chips
Interconnection.
In addition, by that can realize the sensing to temperature to the measurement of silicon hole capacitance, it is bent in conventional silicon hole capacitance
Line includes accumulation area, depletion region and reversal zone.Although the inversion capacitance in reversal zone is minimum, but is unstable
, and as substrate doping and signal frequency and underlayer temperature fluctuate.
When there is hot spot heating heterogeneous, temperature may result in the dependence of inversion capacitance the change of silicon hole performance
Change, so that the complexity that the design of 3D IC becomes.
Therefore need to improve the stability of silicon hole accumulation capacitive region to meet the needs of 3D IC.
The content of the invention
A series of concept of reduced forms is introduced in Summary, this will in specific embodiment part into
One step is described in detail.The Summary of the present invention is not meant to attempt to limit technical solution claimed
Key feature and essential features do not mean that the protection domain for attempting to determine technical solution claimed more.
In order to overcome the problems, such as presently, there are, an embodiment of the present invention provides a kind of semiconductor devices, including：
Semiconductor substrate；
Silicon hole capacitor is arranged in the Semiconductor substrate, and the silicon hole capacitor includes：
Silicon hole main body as interior electrode；
Barrier layer, threshold voltage adjustments layer and insulating layer are set in turn in the outside of the silicon hole main body from the inside to the outside,
The formation process on wherein described barrier layer, the threshold voltage adjustments layer and the insulating layer is compatible；
As the first doped region of external electrode, be arranged at the outside of the insulating layer, with the silicon hole main body, described
Barrier layer, the threshold voltage adjustments layer and the insulating layer form the silicon hole capacitor.
Optionally, the threshold voltage adjustments layer includes HfO2。
Optionally, the threshold voltage adjustments layer is formed by the method for atomic layer deposition.
Optionally, the Semiconductor substrate has the first conduction type；
First doped region has the second conduction type.
Optionally, the silicon hole capacitor further includes the second doped region, and second doped region has the first conductive-type
Type, in the Semiconductor substrate and interval the outside for being arranged at first doped region.
Optionally, the silicon hole capacitor further includes interconnection structure, is mixed respectively with the silicon hole main body, described first
Miscellaneous area and second doped region electrical connection.
Optionally, the silicon hole main body is electrically connected with bias voltage, first doped region and second doped region
It is electrically connected with ground terminal.
Optionally, first doped region forms ring-type around the silicon hole main body.
The present invention also provides a kind of preparation method of semiconductor devices, the described method includes：
Semiconductor substrate is provided, silicon hole opening is formed in the Semiconductor substrate；
Insulating layer, threshold voltage adjustments layer and barrier layer are sequentially formed on the side wall of the silicon hole opening；
Conductive material is filled in the silicon hole opening, to form the silicon hole main body as interior electrode；
The first doped region is formed in the Semiconductor substrate on the outside of the insulating layer, using as external electrode.
Optionally, the threshold voltage adjustments layer includes HfO2。
Optionally, the method forms the second doped region with may further include the outside spacers of first doped region
The step of.
The present invention also provides a kind of electronic device, the electronic device includes above-mentioned semiconductor devices.
The present invention provides a kind of semiconductor devices, wherein the semiconductor devices includes silicon hole capacitor, in order to steady
The capacitance of the fixed silicon hole capacitor, sets between the silicon hole main body as interior electrode and the first doped region as external electrode
Barrier layer and insulating layer are equipped with, threshold voltage adjustments layer is further provided between the barrier layer and the insulating layer,
Such as HfO2, wherein the HfO2The negative electrical charge generated in silicon hole preparation process can be made to generate threshold voltage shift, when described
First doped region is electrically connected with ground terminal, and when the silicon hole main body applies positive bias voltage, electronics is injected into the HfO2
In layer and by HfO2Layer capture, so that positivity offset, silicon hole capacitor work under accumulation state occur for threshold voltage
Make, ensure that capacitance is more stablized, further improve the performance and yield of the semiconductor devices.
In addition, the HfO2It can be formed by the method for atomic layer deposition, with the barrier layer and the insulating layer
Preparation process is more compatible, makes preparation process simpler easy.
Description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, principle used to explain the present invention.
In attached drawing：
Fig. 1 is the preparation process flow diagram using the semiconductor devices of the embodiment of the present invention；
Fig. 2 is the structure diagram of the semiconductor devices of the embodiment of the present invention；
Fig. 3 shows the schematic diagram of electronic device according to an embodiment of the present invention.
Specific embodiment
In the following description, a large amount of concrete details are given in order to provide more thorough understanding of the invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid with the present invention obscure, for some technical characteristics well known in the art not into
Row description.
It should be appreciated that the present invention can be implemented in different forms, and it should not be construed as being limited to what is proposed here
Embodiment.On the contrary, providing these embodiments disclosure will be made thoroughly and complete, and will fully convey the scope of the invention to
Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in Ceng He areas may be exaggerated.From beginning to end
Same reference numerals represent identical element.
It should be understood that when element or layer be referred to as " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " it is other
When element or layer, can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer or
Person may have element or layer between two parties.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " directly
It is connected to " or " being directly coupled to " other elements or during layer, then there is no elements or layer between two parties.It should be understood that although it can make
Various elements, component, area, floor and/or part are described with term first, second, third, etc., these elements, component, area, floor and/
Or part should not be limited by these terms.These terms be used merely to distinguish an element, component, area, floor or part with it is another
One element, component, area, floor or part.Therefore, do not depart from present invention teach that under, first element discussed below, portion
Part, area, floor or part are represented by second element, component, area, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... under ", " ... it
On ", " above " etc., herein can for convenience description and being used describe an element shown in figure or feature with
The relation of other elements or feature.It should be understood that in addition to orientation shown in figure, spatial relationship term intention, which further includes, to be made
With the different orientation with the device in operation.For example, if the device overturning in attached drawing, then, is described as " under other elements
Face " or " under it " or " under it " element or feature will be oriented to other elements or feature " on ".Therefore, exemplary art
Language " ... below " and " ... under " it may include upper and lower two orientations.Device can additionally be orientated (be rotated by 90 ° or its
It is orientated) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as the limitation of the present invention.Make herein
Used time, " one " of singulative, "one" and " described/should " be also intended to include plural form, unless context is expressly noted that separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when in this specification in use, determining the feature, whole
Number, step, operation, the presence of element and/or component, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of element, component and/or group.Herein in use, term "and/or" includes any and institute of related Listed Items
There is combination.
It describes to send out herein with reference to the cross-sectional view of the schematic diagram of the desirable embodiment (and intermediate structure) as the present invention
Bright embodiment.As a result, it is contemplated that due to caused by such as technology of preparing and/or tolerance from the variation of shown shape.Therefore,
The embodiment of the present invention should not necessarily be limited to the given shape in area shown here, but including due to for example preparing caused shape
Shape deviation.For example, it is shown as the injection region of rectangle usually has circle at its edge or bending features and/or implantation concentration ladder
Degree rather than the binary from injection region to non-injection regions change.Equally, the disposal area can be caused by injecting the disposal area formed
Some injections in area between the surface passed through during injection progress.Therefore, the area shown in figure is substantially schematic
, their shape is not intended the true form in the area of display device and is not intended to limit the scope of the present invention.
In order to thoroughly understand the present invention, detailed step and detailed structure will be proposed in following description, so as to
Illustrate technical solution proposed by the present invention.Presently preferred embodiments of the present invention is described in detail as follows, however except these detailed descriptions
Outside, the present invention can also have other embodiment.
In order to solve the problems in the existing technology the present invention provides a kind of semiconductor devices, including：
Semiconductor substrate；
Silicon hole capacitor, is arranged in Semiconductor substrate, including：
Silicon hole main body as interior electrode；
Barrier layer, threshold voltage adjustments layer and insulating layer are set in turn in the outside of the silicon hole main body from the inside to the outside,
The formation process on wherein described barrier layer, the threshold voltage adjustments layer and the insulating layer is compatible；
As the first doped region of external electrode, be arranged at the outside of the insulating layer, with the silicon hole main body, described
Barrier layer, the threshold voltage adjustments layer and the insulating layer form the silicon hole capacitor.
Wherein, the threshold voltage adjustments layer includes HfO2。
Wherein, the threshold voltage adjustments layer is formed by the method for atomic layer deposition.
The present invention provides a kind of semiconductor devices, wherein the semiconductor devices includes silicon hole capacitor, in order to steady
The capacitance of the fixed silicon hole capacitor, sets between the silicon hole main body as interior electrode and the first doped region as external electrode
Barrier layer and insulating layer are equipped with, threshold voltage adjustments layer is further provided between the barrier layer and the insulating layer,
Such as HfO2, wherein the HfO2The negative electrical charge generated in silicon hole preparation process can be made to generate threshold voltage shift, when described
First doped region is electrically connected with ground terminal, and when the silicon hole main body applies positive bias voltage, electronics is injected into the HfO2
In layer and by HfO2Layer capture, so that positivity offset, silicon hole capacitor work under accumulation state occur for threshold voltage
Make, ensure that capacitance is more stablized, further improve the performance and yield of the semiconductor devices.
In addition, the HfO2It can be formed by the method for atomic layer deposition, with the barrier layer and the insulating layer
Preparation process is more compatible, makes preparation process simpler easy.
Embodiment one
It is understandable for objects, features and advantages of the present invention is enable to become apparent, below in conjunction with the accompanying drawings to the tool of the present invention
Body embodiment is described in detail.Wherein, Fig. 1 is the preparation process stream using the semiconductor devices of the embodiment of the present invention
Journey schematic diagram；Fig. 2 is the structure diagram of the semiconductor devices of the embodiment of the present invention.
Detail is elaborated in the following description in order to fully understand the present invention.But the present invention can with it is a variety of not
Other manner described here is same as to implement, those skilled in the art can do class without violating the connotation of the present invention
Like popularization.Therefore the present invention is not limited to the specific embodiments disclosed below.
The embodiment of the present invention provides firstly a kind of semiconductor devices, please refers to Fig.2, the semiconductor device of the embodiment of the present invention
The cross-sectional view of part, including：
Semiconductor substrate 201 has the first conduction type；
Silicon hole capacitor, is arranged in Semiconductor substrate, including：
Silicon hole main body 204 as interior electrode；
Barrier layer 206, threshold voltage adjustments layer 205 and insulating layer 203 are set in turn in the silicon hole master from the inside to the outside
The outside of body；
As the first doped region 202 of external electrode, be arranged at the outside of the insulating layer 203, with the silicon hole master
Body, the barrier layer, the threshold voltage adjustments layer and the insulating layer form the silicon hole capacitor.
Wherein, the semiconductor devices still further comprises the second doped region 209, has the first conduction type, positioned at institute
It states in Semiconductor substrate and is arranged at intervals at the outside of first doped region.
Wherein, the semiconductor devices still further comprises interconnection structure, respectively with the silicon hole main body, described first
Doped region and second doped region electrical connection.
Specifically, the Semiconductor substrate 201 is silicon substrate, germanium substrate, silicon-Germanium substrate, silicon carbide substrates, gallium nitride lining
Bottom one kind therein.
In the present embodiment, the Semiconductor substrate 201 is silicon substrate, and the silicon substrate is interior doped with foreign ion, is P
Type ion, such as boron ion, indium ion.In other embodiments, the ion adulterated in the silicon substrate be N-type ion, such as phosphorus
Ion, arsenic ion etc..
Optionally, the semiconductor substrate surface can also be formed with semiconductor devices, such as MOS transistor, resistance, capacitance
Deng.
Silicon hole is formed in the Semiconductor substrate 201, the shape of the cross section of the silicon hole is square, rectangular
Shape, circle etc..
In the present embodiment, the shape of the cross section of the silicon hole is circle.
The silicon hole is embedded among the Semiconductor substrate, and the silicon hole includes the silicon hole main body positioned at center
204 (conductive layers) and the barrier layer 206 being looped around on the outside of silicon hole main body and insulating layer 203.
Wherein, the conductive layer is formed by metal material, and the metal material includes one kind in Pt, Au, Cu, Ti and W
Or it is a variety of, polysilicon can also be selected, limitation and a certain kind, can not realize conducting function.
It is preferably Ni metal in the present invention, selects Ni metal that can not only reduce cost, and metallic copper is selected to be formed
The technique of the silicon hole can be compatible with process simplification with existing process.
The barrier layer is in order to improve the adhesiveness that metal is filled in silicon hole, in the dielectric layer and the silicon hole
Between formed, thickness is 300-500 angstroms, including one or more in titanium nitride TiN and titanium Ti, the one of the present invention
It is preferably specifically the titanium nitride TiN of levels lamination and titanium Ti in embodiment.
The thickness of the insulating layer is 1000-3000 angstroms, but is not limited to the numberical range, the effect of the insulating layer
It is that the metal that is subsequently filled into order to prevent in silicon hole and substrate turn on, the insulating layer is preferably oxide, can be with
It is made of the materials such as stearic acid tetraethoxysilane (SATEOS) or tetraethoxysilane (TEOS), but be not limited to that institute
State material.And the insulating layer in subsequent steps can be as the dielectric layer of silicon hole capacitor.
The insulating layer selects silica in the present invention.Further, in order to make the capacitance of the silicon hole capacitor
More stablize, threshold voltage adjustments layer 205 is additionally provided between the barrier layer 206 and insulating layer 203.
Wherein described threshold voltage adjustments layer 205 be not arbitrary selection, it has to be possible to realize when the silicon hole main body with
Bias voltage is electrically connected, and when first doped region and second doped region are electrically connected with ground terminal, makes threshold voltage
Positivity deviates, and the capacitance can be made more to stablize, and needs mutually compatible with the preparation process of current silicon hole.
The threshold voltage adjustments layer 205 selects HfO in the present invention as a result,2。
Optionally, the threshold voltage adjustments layer is formed by the method for atomic layer deposition.Wherein, the shape of the insulating layer
Into method selection chemical vapor deposition.
The outside of the silicon hole set around the silicon hole the first doped region, first doped region have with
The different conduction type of the Semiconductor substrate.
Optionally, the silicon hole is cylinder, and first doped region is set around the silicon hole.Lead in the silicon
The first doped region 202 is formed in Semiconductor substrate 201 around hole, first doped region 202 forms ring-type around silicon hole.
In the present embodiment, when the shape of the cross section of the silicon hole is circular, first doped region 202 is circle
Ring, and the side wall of the annulus to silicon hole has a certain distance.
In other embodiments, when the shape of the cross section of the silicon hole is square, rectangle, described first mixes
Miscellaneous area 202 is straight-flanked ring, and the side wall of the straight-flanked ring to silicon hole has a certain distance.
Wherein, first doped region 202 is formed by the technique of ion implanting in the Semiconductor substrate 201, is made
The surface and the surface of Semiconductor substrate 201 for obtaining first doped region 202 maintain an equal level.
The type of the Doped ions of first doped region 202 is different from the type of the Doped ions of Semiconductor substrate 201,
Such as the Semiconductor substrate is P-type semiconductor substrate in the present embodiment, then first doped region 202 is N-doped zone
Domain, such as phosphorus is injected, to form first doped region 202.
Wherein, the doping concentration N of first doped regionA=1E15cm-3。
Further, it is additionally provided with the second doped region 209 in the outside of first doped region 202.
The type of the Doped ions of second doped region 209 is identical with the type of the Doped ions of Semiconductor substrate 201,
And the concentration of the Doped ions of second doped region 209 is more than the concentration of the Doped ions of the Semiconductor substrate 201.
In the present embodiment, the Doped ions of the Semiconductor substrate 201 are p-type ion, second doped region 209
Doped ions are also p-type ion.
Wherein, first doped region 202 and second doped region 209 are arranged at intervals, and second doped region
209 not entirely around first doped region 202, and second doped region 209 is arranged at the one of first doped region 202
Side, for example, when the silicon hole for it is cylindrical when, first doped region 202 wraps the silicon hole in circular ring shape, and institute
The second doped region 209 is stated only to be formed in the outside of the surface of first doped region 202, and not in entire side.
Dielectric layer 210 is formed with above the Semiconductor substrate 201, the first doped region 202, the dielectric layer 210
Material is silica, p-doped silicate glass (PSG), boron-doping phosphosilicate glass (BPSG) or low-K dielectric material.It is being given an account of
210 surface of electric layer is formed with interconnection structure.
Wherein, it is mutual to include the first metal interconnecting layer 207, the second metal interconnecting layer 211 and the 3rd metal for the interconnection structure
Even layer 208；
Wherein, first metal interconnecting layer is electrically connected with first doped region；
Second metal interconnecting layer is electrically connected with second doped region；
3rd metal interconnecting layer is electrically connected with the silicon hole.
First metal interconnecting layer 207 is connected by the first conductive through hole below and the first doped region electricity
It connects, second metal interconnecting layer 208 is electrically connected by the second conductive through hole and the second doped region.Described and the first doped region
The metal interconnecting layer being connected and the 3rd metal interconnecting layer electric isolation being connected with silicon hole main body so that the silicon leads to
202 electric isolation of conductive material and the first doped region in hole.
Wherein, the silicon hole main body is electrically connected with bias voltage, first doped region and second doped region with
Ground terminal is electrically connected.Such as first doped region and second doped region pass through the first metal interconnecting layer and described respectively
Two metal interconnecting layers are electrically connected with ground terminal.
The present invention provides a kind of semiconductor devices, wherein the semiconductor devices includes silicon hole capacitor, in order to steady
The capacitance of the fixed silicon hole capacitor, sets between the silicon hole main body as interior electrode and the first doped region as external electrode
Barrier layer and insulating layer are equipped with, threshold voltage adjustments layer is further provided between the barrier layer and the insulating layer,
Such as HfO2, wherein the HfO2The negative electrical charge generated in silicon hole preparation process can be made to generate threshold voltage shift, when described
First doped region is electrically connected with ground terminal, and when the silicon hole main body applies positive bias voltage, electronics is injected into the HfO2
In layer and by HfO2Layer capture, so that positivity offset, silicon hole capacitor work under accumulation state occur for threshold voltage
Make, ensure that capacitance is more stablized, further improve the performance and yield of the semiconductor devices.
In addition, the HfO2It can be formed by the method for atomic layer deposition, with the barrier layer and the insulating layer
Preparation process is more compatible, makes preparation process simpler easy.
Embodiment two
The present invention also provides a kind of preparation method of semiconductor devices, as shown in Figure 1, the described method includes：
Semiconductor substrate is provided, silicon hole opening is formed in the Semiconductor substrate；
Insulating layer, threshold voltage adjustments layer and stop are sequentially formed by outer preparation on the side wall of the silicon hole opening
Layer；
Conductive material is filled in the silicon hole opening, to be formed as interior electrode silicon hole main body；
The outside of the insulating layer described in the Semiconductor substrate forms the first doped region, to form external electrode.
Specifically, in one embodiment of this invention, the Semiconductor substrate can be in the following material being previously mentioned
It is at least one：Silicon, silicon-on-insulator (SOI) are stacked silicon (SSOI) on insulator, are stacked SiGe (S- on insulator
SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI) etc..
Optionally, the Semiconductor substrate is patterned, to form silicon hole opening in the Semiconductor substrate.
Optionally, the method for deep reaction ion etching (DRIE) is selected to etch the Semiconductor substrate in this step.
Gas hexa-fluoride (SF is selected in the deep reaction ion etching (DRIE) step6) as process gas, it applies
Add radio-frequency power supply so that hexa-fluoride reaction air inlet forms high ionization, controls in the etching step operating pressure to be
20mTorr-8Torr, power 600W, frequency 13.5MHz, Dc bias can the continuous control in -500V-1000V, ensure
The needs of anisotropic etching.
At least form insulating layer 203,205 and of threshold voltage adjustments layer from outside to inside on the side wall of the silicon hole opening
Barrier layer 206.
The barrier layer is in order to improve the adhesiveness that metal is filled in silicon hole, in the dielectric layer and the silicon hole
Between formed, thickness is 300-500 angstroms, including one or more in titanium nitride TiN and titanium Ti, the one of the present invention
It is preferably specifically the titanium nitride TiN of levels lamination and titanium Ti in embodiment.
The thickness of the insulating layer is 1000-3000 angstroms, but is not limited to the numberical range, the effect of the insulating layer
It is that the metal that is subsequently filled into order to prevent in silicon hole and substrate turn on, the insulating layer is preferably oxide, can be with
It is made of the materials such as stearic acid tetraethoxysilane (SATEOS) or tetraethoxysilane (TEOS), but be not limited to that institute
State material.And the insulating layer in subsequent steps can be as the dielectric layer of silicon hole capacitor.
The insulating layer selects silica in the present invention.Further, in order to make the capacitance of the silicon hole capacitor
More stablize, threshold voltage adjustments layer 205 is additionally provided between the barrier layer 206 and insulating layer 203.
Wherein described threshold voltage adjustments layer 205 be not arbitrary selection, it has to be possible to realize when the silicon hole main body with
Bias voltage is electrically connected, and when first doped region and second doped region are electrically connected with ground terminal, makes threshold voltage
Positivity deviates, and the capacitance can be made more to stablize, and needs mutually compatible with the preparation process of current silicon hole.
The threshold voltage adjustments layer 205 selects HfO in the present invention as a result,2。
Optionally, the threshold voltage adjustments layer is formed by the method for atomic layer deposition.Wherein, the shape of the insulating layer
Into method selection chemical vapor deposition.
Then deposition conductive layer is selected, the conductive layer can be metal material, and the conductive layer can be in the present invention
For copper, aluminium or tungsten layer：The surface deposition conductive layer on barrier layer, deposition method can be selected in the prior art often in the through hole
Deposition method, such as can be by chemical vapor deposition (CVD) method, physical vapour deposition (PVD) (PVD) method or atomic layer deposition
Product (ALD) method, then planarizes the conductive layer.
The conductive layer is formed by metal material, and the metal material includes a kind of or more in Pt, Au, Cu, Ti and W
Kind, polysilicon can also be selected, limitation and a certain kind, can not realize that conducting function can
It is preferably Ni metal in the present invention, selects Ni metal that can not only reduce cost, and metallic copper is selected to be formed
The technique of the silicon hole can be compatible with process simplification with existing process.
Further, the method is also further formed the step of the first doped region and the second doped region 209, wherein, it is described
Semiconductor substrate has the first conduction type；, first doped region is with the second conduction type.Second doped region 209
With the first conduction type, in the Semiconductor substrate and the outside of first doped region is arranged at intervals at.
Wherein, the semiconductor devices still further comprises the step of forming interconnection structure, with respectively with the silicon hole
Main body, first doped region and second doped region electrical connection.
Wherein, the first doped region around the silicon hole, first doped region are set in the outside of the silicon hole
With the conduction type different from the Semiconductor substrate.
Optionally, the silicon hole is cylinder, and first doped region is set around the silicon hole.Lead in the silicon
The first doped region 202 is formed in Semiconductor substrate 201 around hole, first doped region 202 forms ring-type around silicon hole.
In the present embodiment, when the shape of the cross section of the silicon hole is circular, first doped region 202 is circle
Ring, and the side wall of the annulus to silicon hole has a certain distance.
In other embodiments, when the shape of the cross section of the silicon hole is square, rectangle, described first mixes
Miscellaneous area 202 is straight-flanked ring, and the side wall of the straight-flanked ring to silicon hole has a certain distance.
Wherein, first doped region 202 is formed by the technique of ion implanting in the Semiconductor substrate 201, is made
The surface and the surface of Semiconductor substrate 201 for obtaining first doped region 202 maintain an equal level.
The type of the Doped ions of first doped region 202 is different from the type of the Doped ions of Semiconductor substrate 201,
Such as the Semiconductor substrate is P-type semiconductor substrate in the present embodiment, then first doped region 202 is N-doped zone
Domain, such as phosphorus is injected, to form first doped region 202.
The type of the Doped ions of second doped region 209 is identical with the type of the Doped ions of Semiconductor substrate 201,
And the concentration of the Doped ions of second doped region 209 is more than the concentration of the Doped ions of the Semiconductor substrate 201.
In the present embodiment, the Doped ions of the Semiconductor substrate 201 are p-type ion, second doped region 209
Doped ions are also p-type ion.
Dielectric layer 210, the material of the dielectric layer 210 are formed on the Semiconductor substrate 201,202 surface of the first doped region
Expect for silica, p-doped silicate glass (PSG), boron-doping phosphosilicate glass (BPSG) or low-K dielectric material.In the dielectric
210 surface of layer are formed with interconnection structure.
Wherein, it is mutual to include the first metal interconnecting layer 207, the second metal interconnecting layer 211 and the 3rd metal for the interconnection structure
Even layer 208；
Wherein, first metal interconnecting layer is electrically connected with first doped region；
Second metal interconnecting layer is electrically connected with second doped region；
3rd metal interconnecting layer is electrically connected with the silicon hole.
First metal interconnecting layer 207 is connected by the first conductive through hole below and the first doped region electricity
It connects, second metal interconnecting layer 208 is electrically connected by the second conductive through hole and the second doped region.Described and the first doped region
The metal interconnecting layer being connected and the 3rd metal interconnecting layer electric isolation being connected with silicon hole main body so that the silicon leads to
202 electric isolation of conductive material and the first doped region in hole.
Wherein, the silicon hole main body is electrically connected with bias voltage, first doped region and second doped region with
Ground terminal is electrically connected.Such as first doped region and second doped region pass through the first metal interconnecting layer and described respectively
Two metal interconnecting layers are electrically connected with ground terminal.
So far, the introduction of the correlation step of the semiconductor devices preparation of the embodiment of the present invention is completed.Above-mentioned steps it
Afterwards, other correlation steps can also be included, details are not described herein again.Also, in addition to the foregoing steps, the preparation side of the present embodiment
Method can also include other steps among above-mentioned each step or between different steps, these steps can be by existing
Various techniques in technology realize that details are not described herein again.
Embodiment three
The present invention also provides a kind of electronic device, including the semiconductor devices described in embodiment one.
The electronic device of the present embodiment can be mobile phone, tablet computer, laptop, net book, game machine, TV
Any electronic product such as machine, VCD, DVD, navigator, Digital Frame, camera, video camera, recording pen, MP3, MP4, PSP is set
Standby or any intermediate products including circuit.The electronic device of the embodiment of the present invention, due to the use of above-mentioned circuit,
Thus with better performance.
Wherein, Fig. 3 shows the example of mobile phone handsets.Mobile phone handsets 300, which are equipped with, to be included in shell 301
Display portion 302, operation button 303, external connection port 304, loud speaker 305, microphone 306 etc..
Wherein described mobile phone handsets include foregoing semiconductor devices or the semiconductor device according to embodiment two
Semiconductor devices obtained by the preparation method of part, the semiconductor devices include Semiconductor substrate, have the first conduction type；
Silicon hole capacitor, is arranged in Semiconductor substrate, including：Silicon hole main body as interior electrode；Barrier layer, threshold voltage tune
Ganglionic layer and insulating layer are set in turn in the outside of the silicon hole main body from the inside to the outside；As the first doped region of external electrode, if
Be placed in the outside of the depletion region, with the silicon hole main body, the barrier layer, the threshold voltage adjustments layer and it is described absolutely
Edge layer dielectric forms the silicon hole capacitor.Wherein described threshold voltage adjustments layer, such as HfO2Silicon hole can be prepared
The negative electrical charge that generates in the process generates threshold voltage shift, when first doped region is electrically connected with ground terminal, the silicon hole
When main body applies positive bias voltage, electronics is injected into the HfO2In layer and by HfO2Layer capture, so that threshold voltage occurs
Positivity deviates, and the silicon hole capacitor works under accumulation state, ensures that capacitance is more stablized, and further improves and described partly leads
The performance and yield of body device.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
Citing and the purpose of explanation, and be not intended to limit the invention in the range of described embodiment.In addition people in the art
Member is it is understood that the invention is not limited in above-described embodiment, introduction according to the present invention can also be made more kinds of
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (12)
1. a kind of semiconductor devices, which is characterized in that including：
Semiconductor substrate；
Silicon hole capacitor is arranged in the Semiconductor substrate, and the silicon hole capacitor includes：
Silicon hole main body as interior electrode；
Barrier layer, threshold voltage adjustments layer and insulating layer are set in turn in the outside of the silicon hole main body from the inside to the outside, wherein
The formation process on the barrier layer, the threshold voltage adjustments layer and the insulating layer is compatible；
As the first doped region of external electrode, be arranged at the outside of the insulating layer, with the silicon hole main body, the stop
Layer, the threshold voltage adjustments layer and the insulating layer form the silicon hole capacitor.
2. semiconductor devices according to claim 1, which is characterized in that the threshold voltage adjustments layer includes HfO2。
3. semiconductor devices according to claim 1, which is characterized in that the threshold is formed by the method for atomic layer deposition
Threshold voltage regulating course.
4. semiconductor devices according to claim 1, which is characterized in that the Semiconductor substrate has the first conductive-type
Type；
First doped region has the second conduction type.
5. semiconductor devices according to claim 1, which is characterized in that the silicon hole capacitor further includes the second doping
Area, second doped region have the first conduction type, and in the Semiconductor substrate and what is be spaced is arranged at described first
The outside of doped region.
6. semiconductor devices according to claim 5, which is characterized in that the silicon hole capacitor further includes mutual connection
Structure is electrically connected respectively with the silicon hole main body, first doped region and second doped region.
7. semiconductor devices according to claim 6, which is characterized in that the silicon hole main body is electrically connected with bias voltage
It connects, first doped region and second doped region are electrically connected with ground terminal.
8. semiconductor devices according to claim 1, which is characterized in that first doped region surrounds the silicon hole master
The bodily form is circlewise.
9. a kind of preparation method of semiconductor devices, which is characterized in that the described method includes：
Semiconductor substrate is provided, silicon hole opening is formed in the Semiconductor substrate；
Insulating layer, threshold voltage adjustments layer and barrier layer are sequentially formed on the side wall of the silicon hole opening；
Conductive material is filled in the silicon hole opening, to form the silicon hole main body as interior electrode；
The first doped region is formed in the Semiconductor substrate on the outside of the insulating layer, using as external electrode.
10. preparation method according to claim 9, which is characterized in that the threshold voltage adjustments layer includes HfO2。
11. preparation method according to claim 9, which is characterized in that the method may further include described first
The step of forming the second doped region the outside spacers of doped region.
12. a kind of electronic device, which is characterized in that the electronic device includes the semiconductor device described in one of claim 1 to 8
Part.
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| CN108122885B (en) * | 2016-11-28 | 2019-12-17 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device, preparation method thereof and electronic device |
| CN110649030A (en) * | 2019-09-27 | 2020-01-03 | 长江存储科技有限责任公司 | 3D NAND and manufacturing method thereof |
| CN113488467A (en) * | 2020-07-02 | 2021-10-08 | 长江存储科技有限责任公司 | Semiconductor device and manufacturing method thereof |
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| CN101341576A (en) * | 2005-11-08 | 2009-01-07 | Nxp股份有限公司 | Integrated capacitor arrangement for ultrahigh capacitance values |
| US20150279844A1 (en) * | 2009-08-21 | 2015-10-01 | International Business Machines Corporation | Structure and method of forming enhanced array device isolation for implanted plate edram |
| US20150348977A1 (en) * | 2014-05-29 | 2015-12-03 | International Business Machines Corporation | Vertically integrated memory cell |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101341576A (en) * | 2005-11-08 | 2009-01-07 | Nxp股份有限公司 | Integrated capacitor arrangement for ultrahigh capacitance values |
| US20150279844A1 (en) * | 2009-08-21 | 2015-10-01 | International Business Machines Corporation | Structure and method of forming enhanced array device isolation for implanted plate edram |
| US20150348977A1 (en) * | 2014-05-29 | 2015-12-03 | International Business Machines Corporation | Vertically integrated memory cell |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108122885B (en) * | 2016-11-28 | 2019-12-17 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device, preparation method thereof and electronic device |
| CN110649030A (en) * | 2019-09-27 | 2020-01-03 | 长江存储科技有限责任公司 | 3D NAND and manufacturing method thereof |
| CN113488467A (en) * | 2020-07-02 | 2021-10-08 | 长江存储科技有限责任公司 | Semiconductor device and manufacturing method thereof |
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