CN102054751B - Dual-inlay structure and forming method thereof - Google Patents
Dual-inlay structure and forming method thereof Download PDFInfo
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- CN102054751B CN102054751B CN 200910198349 CN200910198349A CN102054751B CN 102054751 B CN102054751 B CN 102054751B CN 200910198349 CN200910198349 CN 200910198349 CN 200910198349 A CN200910198349 A CN 200910198349A CN 102054751 B CN102054751 B CN 102054751B
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Abstract
The invention discloses a forming method of a dual-inlay structure. The method comprises the following steps of: providing a semiconductor substrate with a metal wiring layer; sequentially forming a barrier layer and an interlayer insulating layer on the metal wiring layer; treating the interlayer insulating layer with a reactant capable of reacting with an interlayer insulating layer material to generate a nitride, and forming a protective layer on the surface of the interlayer insulating layer; sequentially etching the protective layer, the interlayer insulating layer and the barrier layer until the metal wiring layer is exposed, and forming a contact hole; forming a bottom antireflection layer used for filling the contact hole and positioned on the surface of the protective layer; forming an isolating layer on the surface of the bottom antireflection layer; forming a photoresist pattern on the surface of the isolating layer; sequentially etching the isolating layer, the bottom antireflection layer, the protective layer and a part of the interlayer insulating layer to form grooves by taking the photoresist pattern as a mask; and removing the photoresist pattern, the isolating layer and the bottom antireflection layer. By the method, an undercut can be avoided in the process of etching to form the grooves.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly dual-damascene structure and forming method thereof.
Background technology
Along with further developing of semiconductor device manufacturing technology, the high-performance between the device, high density connect not only carries out in single interconnection layer, and will interconnect between multilayer.Therefore, usually provide multilayer interconnect structure, wherein a plurality of interconnection layers are stacking mutually, and interlayer dielectric places therebetween, are used for connecting semiconductor device.The multilayer interconnect structure that particularly utilizes dual damascene (dual-damascene) technique to form, it forms contact hole (via) and groove (trench) in advance in interlayer dielectric, then fill described contact hole and groove with electric conducting material.The boost device reliability because the restriction that dual-damascene structure can be avoided aliasing error and solve known smithcraft, dual-damascene technics just are widely used in the semiconductor fabrication process.Therefore, dual-damascene technics has become the now main flow of plain conductor connecting technology.
The formation method of existing a kind of dual-damascene structure comprises the steps:
As shown in Figure 1, provide the Semiconductor substrate 100 with metal wiring layer 110, described metal wiring layer 110 materials are one or several in aluminium, silver, the copper;
As shown in Figure 2, on metal wiring layer 110, form successively barrier layer 120, interlayer insulating film 130, cover layer 140, described barrier layer 120 materials are selected from the silicon nitride (NDC) of carbon dope, and thickness is 400 dust to 500 dusts, are used for safeguarding the stability of metal wiring layer 210; Described interlayer insulating film 130 materials are selected from the silica (Black Diamond, BD) that carbon mixes, and thickness is 3500 dust to 4500 dusts, are used for the inter-level dielectric isolation; Described cover layer 140 materials are TEOS, and its Main Ingredients and Appearance is silicon dioxide, avoids the impact of other processing procedure for the protection of interlayer insulating film.
As shown in Figure 3, form photoetching offset plate figure 150 at protective layer, take described photoetching offset plate figure 150 as mask, etching cover layer 140, interlayer insulating film 130, barrier layer 120 are until expose metal wiring layer 110, formation contact hole 151 successively;
As shown in Figure 4, remove described photoetching offset plate figure 150, form the bottom anti-reflection layer 160 of filling described contact hole 151 and being positioned at cover surface, and form separator 170 on described bottom anti-reflection layer 160 surfaces;
Described bottom anti-reflection layer 160 is used for filling described contact hole 151, and can select model is the bottom anti-reflection layer of GF315, is used for better filling described contact hole 151, and forms the plane on protective layer 140 surfaces.
Described separator 170 materials are selected from the low-temperature oxidation silicon materials, thickness is 1000 dust to 1500 dusts, the photoetching offset plate figure that is used for isolation bottom anti-reflection layer 160 and follow-up formation, the formation temperature of described separator 170 is 200 degrees centigrade to 220 degrees centigrade, and described formation temperature can not cause the sex change of bottom anti-reflection layer.
As shown in Figure 5, form photoetching offset plate figure 180 on described separator 170 surfaces, take described photoetching offset plate figure 180 as mask, etching separator 170, bottom anti-reflection layer 160, cover layer 140, interlayer insulating film 130 form groove 181 successively;
As shown in Figure 6, remove described photoetching offset plate figure 180, separator 170 and bottom anti-reflection layer 160.The technique of described removal photoetching offset plate figure 180 and bottom anti-reflection layer 160 can be cineration technics; The technique of described removal separator 170 can be plasma etch process.
Subsequently, fill for example metallic copper of interconnecting metal material in described groove and contact hole, perhaps first deposit and spread barrier layer Ta/TaN deposits for example metallic copper of interconnecting metal material layer again.
The manufacture method of described dual-damascene structure, form in the technique of groove 181 at etching separator 170, bottom anti-reflection layer 160, cover layer 140, interlayer insulating film 130, because cover layer 140 is different from the etch rate of interlayer insulating film 130, in the etching process, near the contact interface of cover layer 140 and interlayer insulating film 130, will form different shapes, cause interlayer insulating film 130 to produce undercutting (under-cut) phenomenon, produce relatively poor groove side surface, and then increased the possibility that punctures occurs between the interlayer insulating film between the metal interconnecting wires.Transmission electron microscope figure as shown in Figure 7 is the groove that produces undercutting.
Summary of the invention
The problem that the present invention solves provides a kind of manufacture method of dual-damascene structure, avoids interlayer insulating barrier generation undercut phenomenon in the process of etching formation groove.
For addressing the above problem, the invention provides a kind of formation method of dual-damascene structure, comprising: the Semiconductor substrate with metal wiring layer is provided; On metal wiring layer, form successively barrier layer, interlayer insulating film; Employing can be processed described interlayer insulating film with the reactant of layer insulation layer material reaction generation nitride, forms protective layer on the interlayer insulating film surface; Etching protective layer, interlayer insulating film, barrier layer are until expose metal wiring layer, the formation contact hole successively; Form the bottom anti-reflection layer of filling described contact hole and being positioned at protective layer; Form separator on described bottom anti-reflection layer surface; Form photoetching offset plate figure in described insulation surface; Take described photoetching offset plate figure as mask, etching separator, bottom anti-reflection layer, protective layer and part interlayer insulating film form groove successively; Remove described photoetching offset plate figure, separator and bottom anti-reflection layer.
The present invention also provides a kind of dual-damascene structure, comprising: Semiconductor substrate; Be positioned at the metal wiring layer on the described Semiconductor substrate; Be positioned at successively barrier layer, interlayer insulating film, protective layer on the described metal wiring layer; Run through protective layer, interlayer insulating film, barrier layer and expose the contact hole of metal wiring layer; Run through protective layer and part interlayer insulating film and the groove corresponding with the contact hole position.
Compared with prior art; the present invention has the following advantages: the formation method of dual-damascene structure provided by the present invention; form protective layer owing to process interlayer insulating film on the interlayer insulating film surface with ammonia; make between the interlayer insulating film of formation and the protective layer and do not have obvious interlayer line of demarcation; adopt etching agent to carry out in the technique of etching; etching agent is approaching with the etch rate to interlayer insulating film to the etch rate of protective layer; reduced the undercutting problem that the etch rate of cover layer and interlayer insulating film in the prior art does not coexist and causes in the etch process; dwindle the characteristic size suitable for reading after the metal valley etching, thereby improved the reliability properties of the anti-electric leakage of plain conductor.
Description of drawings
Fig. 1 to Fig. 6 is the process schematic diagram of the formation method of existing a kind of dual-damascene structure;
Fig. 7 is the projection Electronic Speculum figure of the dual-damascene structure that forms of the formation method of existing dual-damascene structure;
Fig. 8 is the schematic flow sheet of the formation method of dual-damascene structure provided by the invention;
Fig. 9 to Figure 16 is the process schematic diagram of the formation method of a kind of dual-damascene structure provided by the invention;
Figure 17 is the transmission electron microscope picture of the dual-damascene structure that forms of the formation method of a kind of dual-damascene structure provided by the invention.
Embodiment
A lot of details have been set forth in the following description so that fully understand the present invention.But the present invention can implement much to be different from alternate manner described here, and those skilled in the art can do similar popularization in the situation of intension of the present invention, so the present invention is not subjected to the restriction of following public implementation.
Secondly, the present invention utilizes schematic diagram to be described in detail, when the embodiment of the invention is described in detail in detail; for ease of explanation; the profile of expression device architecture can be disobeyed general ratio and be done local the amplification, and described schematic diagram is example, and it should not limit the scope of protection of the invention at this.The three-dimensional space that in actual fabrication, should comprise in addition, length, width and the degree of depth.
Fig. 8 is the schematic flow sheet of the formation method of a kind of dual-damascene structure of providing of present embodiment, specifically comprises the steps: step S100, and the Semiconductor substrate with metal wiring layer is provided; Step S110 forms barrier layer, interlayer insulating film successively on metal wiring layer; Step S120, employing can be processed described interlayer insulating film with the reactant of layer insulation layer material reaction generation nitride, forms protective layer on the interlayer insulating film surface; Step S130, etching protective layer, interlayer insulating film, barrier layer are until expose metal wiring layer, the formation contact hole successively; Step S140 forms the bottom anti-reflection layer of filling described contact hole and being positioned at protective layer; Step S150 forms separator on described bottom anti-reflection layer surface; Step S160 forms photoetching offset plate figure in described insulation surface; Step S170, take described photoetching offset plate figure as mask, etching separator, bottom anti-reflection layer, protective layer and part interlayer insulating film form groove successively; Step S180 removes described photoetching offset plate figure, separator and bottom anti-reflection layer.
Below in conjunction with accompanying drawing, the formation method of semiconductor structure of the present invention is elaborated.
With reference to figure 9, Semiconductor substrate 200 is provided, described Semiconductor substrate 200 can be the substrate (part that comprises integrated circuit and other elements) of multi layer substrate (silicon substrate that for example, has covering dielectric and metal film), classification substrate, silicon-on-insulator substrate (SOI), epitaxial silicon substrate, section processes.
Form metal wiring layer 210 in described Semiconductor substrate 200, described metal wiring layer 210 materials are one or several in aluminium, silver, chromium, molybdenum, nickel, palladium, platinum, titanium, tantalum, the copper, more preferably use copper, described metal wiring layer 210 thickness are 2000 dust to 3000 dusts.
With reference to Figure 10, on metal wiring layer 210, form successively barrier layer 220, interlayer insulating film 230.
Described barrier layer 220 materials are selected from the silicon nitride (NDC) of carbon dope, thickness is 400 dust to 500 dusts, be used for safeguarding the stability of metal wiring layer 210, and the silicon nitride of described carbon dope to have water absorption lower, the advantage of the low interlayer insulating film coupling with follow-up formation of dielectric constant.
The formation technique on described barrier layer 220 can be selected chemical vapor deposition method, adopt tetraethoxysilane and ammonia as reaction material, the concrete technology parameter is: reaction temperature is 300 degrees centigrade to 400 degrees centigrade, chamber pressure is that 3.7 holders are to 4.2 holders, interresponse time is 5 millimeters to 8 millimeters, power is 200 watts to 240 watts, the tetraethoxysilane flow is that per minute 300 standard cubic centimeters are to per minute 400 standard cubic centimeters, ammonia flow is that per minute 650 standard cubic centimeters are to per minute 750 standard cubic centimeters, until form the barrier layer 220 of 400 dust to 500 dust thickness.
Described interlayer insulating film 230 materials are selected from the silica (Black Diamond, BD) that carbon mixes, and thickness is 3500 dust to 4500 dusts, are used for the inter-level dielectric isolation.The silica that described carbon mixes is low except having dielectric constant, and the advantage that transmission delay is little also possesses with barrier layer 220 selective etchings than high advantage.
Described interlayer insulating film 230 can select chemical vapor deposition method to form, the concrete technology parameter is: reaction temperature is 300 degrees centigrade to 400 degrees centigrade, chamber pressure be 4 the holder to 6 the holder, interresponse time is 5 millimeters to 9 millimeters, power is 400 watts to 600 watts, and oxygen flow is per minute 100cm
3/ min～300cm
3/ min, helium gas flow are 800cm
3/ min to 1200cm
3/ min, prestox cyclisation tetrasiloxane flow is 2000cm
3/ min to 4000cm
3/ min is until form the interlayer insulating film 230 of 3500 dust to 4500 dusts.
With reference to Figure 11, employing can be processed described interlayer insulating film 230 with the reactant of layer insulation layer material reaction generation nitride, forms protective layers 240 on interlayer insulating film 230 surfaces; Described can for example be NH with the reactant of layer insulation layer material reaction generation nitride
3, after interlayer insulating film 230 reactions, can form material on described interlayer insulating film 230 surfaces is the protective layer 240 of silicon nitride; concrete; the technique that forms described protective layer 240 is: reaction chamber pressure is 2～7 holders (Torr), and the reaction chamber radio-frequency power is 300～800 watts, NH
3Flow be 500～1200cm
3/ min, the processing time is 5～40S.The thickness of the protective layer 240 that forms is the 200-300 dust.
Form protective layer owing to process interlayer insulating film on the interlayer insulating film surface with ammonia; make between the interlayer insulating film of formation and the protective layer and do not have obvious interlayer line of demarcation; adopt etching agent to carry out in the technique of etching; etching agent is approaching with the etch rate to interlayer insulating film to the etch rate of protective layer; therefore, avoided in the prior art because the different undercut phenomenon that cause of etch rate on interlayer insulating film and barrier layer.
With reference to Figure 12, form photoetching offset plate figure 250 on protective layer 240 surfaces, described photoetching offset plate figure 250 is used for defining the contact hole graph of dual-damascene structure.Take described the 3rd photoetching offset plate figure 250 as mask, etching protective layer 240, interlayer insulating film 230, barrier layer 220 are until expose metal wiring layer 210, formation contact hole 251 successively.
The technique on described etching protective layer 240, interlayer insulating film 230, barrier layer 220 can be plasma etch process; the design parameter of etching technics can for: select plasma etching equipment; the etching apparatus chamber pressure is 10 millitorr to 50 millitorrs; the top radio-frequency power is 200 watts to 500 watts; the bottom radio-frequency power is 150 watts to 300 watts, C
4F
8Flow is 10cm
3/ min to 50cm
3/ min, CO flow are 100cm
3/ min to 200cm
3/ min, Ar flow are 300cm
3/ min to 600cm
3/ min, O
2Flow is 10cm
3/ min to 50cm
3/ min.
With reference to Figure 13, remove described photoetching offset plate figure 250.Remove the technique of described photoetching offset plate figure 250 and can remove technique or cineration technics removal for known chemical reagent.
With reference to Figure 14, form the bottom anti-reflection layer 260 of filling described contact hole 251 and being positioned at protective layer 240 surfaces, subsequently, form separator 270 on described bottom anti-reflection layer 260 surfaces.
It is spin coating proceeding that described bottom anti-reflection layer 260 forms technique.Described bottom anti-reflection layer 260 is used for filling described contact hole 251, and its model is GF315 for example, adopts described bottom anti-reflection layer 260, can better fill described contact hole 251, and forms the plane on protective layer 240 surfaces.
Described separator 270 materials are selected from the low-temperature oxidation silicon materials, thickness is 1000 dust to 1500 dusts, described separator 270 is used for the photoetching offset plate figure of isolation bottom anti-reflection layer 260 and follow-up formation, in addition, select the low-temperature oxidation silicon materials as separator 270 materials, has the film densification, the advantage that isolation performance is good.Need to be pointed out that further that the formation temperature of described separator 270 is 200 degrees centigrade to 220 degrees centigrade, described formation temperature can not cause the sex change of bottom anti-reflection layer.
The formation technique of described separator 270 can strengthen chemical vapor deposition method for plasmaassisted, concrete technological parameter is: the depositing device chamber pressure is that 0.5 holder is to 3 holders, depositing temperature is 200 degrees centigrade to 220 degrees centigrade, and radio-frequency power is 500 watts to 1000 watts, SiH
4Flow is 100cm
3/ min to 200cm
3/ min, N
2The O flow is 10000cm
3/ min to 20000cm
3/ min, N
2Flow is 1000cm
3/ min to 2000cm
3/ min.
Continuation forms photoetching offset plate figure 290 with reference to Figure 14 on described separator 270 surfaces.Described photoetching offset plate figure 290 is used for defining the groove position of dual-damascene structure, and the position of described groove is corresponding with the position of contact hole, and groove width is greater than the contact hole width.
With reference to Figure 15, take described photoetching offset plate figure 290 as mask, etching separator 270, bottom anti-reflection layer 260, protective layer 240 and part interlayer insulating film 230 form groove 291 successively.
The technique of described etching separator 270, bottom anti-reflection layer 260, protective layer 240 and part interlayer insulating film 230 can be plasma etch process.
The design parameter of described plasma etch process is: select plasma etching equipment, the etching apparatus chamber pressure is 10 millitorr to 50 millitorrs, and the top radio-frequency power is 200 watts to 500 watts, and the bottom radio-frequency power is 150 watts to 300 watts, C
4F
8Flow is 10cm
3/ min to 50cm
3/ min, CO flow are 100cm
3/ min to 200cm
3/ min, Ar flow are 300cm
3/ min to 600cm
3/ min, O
2Flow is 10cm
3/ min to 50cm
3/ min.
With reference to Figure 16, remove described photoetching offset plate figure 290, separator 270 and bottom anti-reflection layer 260.
The technique of the described photoetching offset plate figure 290 of described removal and bottom anti-reflection layer 260 can be cineration technics; The technique of described removal separator 270 can be plasma etch process.
In the present embodiment, adopt first cineration technics to remove photoetching offset plate figure 290, until expose separator 270, then using plasma gram etching technics is removed separator 270, until expose bottom anti-reflection layer 260, adopt again cineration technics to remove bottom anti-reflection layer 260.
Semiconductor structure based on the formation method of above-mentioned dual-damascene structure forms comprises: Semiconductor substrate 200; Be positioned at the metal wiring layer 210 on the described Semiconductor substrate 200; Be positioned at the barrier layer 220 on the described metal wiring layer 210; Be positioned at the interlayer insulating film 230 on the described barrier layer 220; Be positioned at the protective layer 240 on the described interlayer insulating film 230; Contact hole 251 runs through protective layer 240, interlayer insulating film 230, barrier layer 220 to exposing metal wiring layer 210; Run through protective layer and part interlayer insulating film and the groove 291 corresponding with the contact hole position.。
Although the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art without departing from the spirit and scope of the present invention, all can make various changes or modifications, so protection scope of the present invention should be as the criterion with the claim limited range.
Claims (6)
1. the formation method of a dual-damascene structure is characterized in that, comprises the steps:
Semiconductor substrate with metal wiring layer is provided;
On metal wiring layer, form successively barrier layer, interlayer insulating film;
Employing can be processed described interlayer insulating film with the reactant of layer insulation layer material reaction generation nitride, forms protective layer on the interlayer insulating film surface;
Etching protective layer, interlayer insulating film, barrier layer are until expose metal wiring layer, the formation contact hole successively;
Form the bottom anti-reflection layer of filling described contact hole and being positioned at protective layer;
Form separator on described bottom anti-reflection layer surface;
Form photoetching offset plate figure in described insulation surface, take described photoetching offset plate figure as mask, etching separator, bottom anti-reflection layer, protective layer and part interlayer insulating film form groove successively;
Remove described photoetching offset plate figure, separator and bottom anti-reflection layer.
2. the formation method of dual-damascene structure as claimed in claim 1 is characterized in that, described can be NH with the reactant of layer insulation layer material reaction generation nitride
3
3. the formation method of dual-damascene structure as claimed in claim 1 is characterized in that, described protective layer material is silicon nitride layer.
4. the formation method of dual-damascene structure as claimed in claim 1 is characterized in that, described protective layer thickness is 200～300 dusts.
5. the formation method of dual-damascene structure as claimed in claim 2 is characterized in that, the technique that forms described protective layer is: NH
3Flow be 500～1200cm
3/ min, the processing time is 5～40 seconds.
6. the formation method of dual-damascene structure as claimed in claim 1 is characterized in that, described insolated layer materials is the low-temperature oxidation silicon materials.
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|---|---|---|---|
| CN 200910198349 CN102054751B (en) | 2009-11-05 | 2009-11-05 | Dual-inlay structure and forming method thereof |
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| CN102054751B true CN102054751B (en) | 2013-03-13 |
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Families Citing this family (2)
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| CN109860043B (en) * | 2018-12-13 | 2021-03-16 | 深圳市华星光电半导体显示技术有限公司 | Array substrate preparation method |
| CN112259503A (en) * | 2020-10-26 | 2021-01-22 | 上海华力集成电路制造有限公司 | Dual damascene process |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6589711B1 (en) * | 2001-04-04 | 2003-07-08 | Advanced Micro Devices, Inc. | Dual inlaid process using a bilayer resist |
| CN101207018A (en) * | 2006-12-22 | 2008-06-25 | 中芯国际集成电路制造(上海)有限公司 | Method for forming anti-reflecting layer and method for manufacturing dual mosaic structure |
| CN101996929A (en) * | 2009-08-20 | 2011-03-30 | 中芯国际集成电路制造(上海)有限公司 | Forming method of dual-damascene structure and semiconductor structure |
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2009
- 2009-11-05 CN CN 200910198349 patent/CN102054751B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6589711B1 (en) * | 2001-04-04 | 2003-07-08 | Advanced Micro Devices, Inc. | Dual inlaid process using a bilayer resist |
| CN101207018A (en) * | 2006-12-22 | 2008-06-25 | 中芯国际集成电路制造(上海)有限公司 | Method for forming anti-reflecting layer and method for manufacturing dual mosaic structure |
| CN101996929A (en) * | 2009-08-20 | 2011-03-30 | 中芯国际集成电路制造(上海)有限公司 | Forming method of dual-damascene structure and semiconductor structure |
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