CN104979273B - The method for forming interconnection structure - Google Patents
The method for forming interconnection structure Download PDFInfo
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- CN104979273B CN104979273B CN201410136507.XA CN201410136507A CN104979273B CN 104979273 B CN104979273 B CN 104979273B CN 201410136507 A CN201410136507 A CN 201410136507A CN 104979273 B CN104979273 B CN 104979273B
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Abstract
The present invention provides a kind of method for forming interconnection structure, including：Interlayer dielectric layer is formed on substrate；Barrier layer is formed on interlayer dielectric layer；Hard mask is formed over the barrier layer, and the first opening of hard mask thickness is formed through in hard mask；Sacrifice layer is filled in the first opening, until sacrifice layer covering hard mask；Graphical sacrifice layer, formed in the sacrifice layer in the first opening and expose barrier layer second and be open, the second opening is less than the first opening；Remove the barrier layer that the second opening is exposed；The interlayer dielectric layer exposed to the second opening in the sacrifice layer and sacrifice layer after graphical performs etching, to form through hole；Using hard mask as mask, interlayer dielectric layer that the interlayer dielectric layer that exposes of opening of etching first and through hole expose forms groove in the interlayer dielectric layer that the first opening is exposed and through hole is run through interlayer dielectric layer.The method of present invention formation interconnection structure reduces the damage to interlayer dielectric layer.
Description
Technical field
The present invention relates to field of semiconductor manufacture, and in particular to a kind of method for forming interconnection structure.
Background technology
With the continuous development of ic manufacturing technology, the integrated level more and more higher of integrated circuit, accordingly, electricity is integrated
The arrangement of the interconnection structure of semiconductor devices is also more intensive in road.The reason such as parasitic capacitance between interconnection structure and caused RC
It is increasing to postpone the influence of (RC delay) to semiconductor devices.
In order to solve the above problems, prior art starts to use low k dielectric（low-k）Or ultra low k dielectric materials
（ultra low-k）The interlayer dielectric layer of interconnection structure is formed, to reduce the parasitic capacitance between metal plug, and then reduces RC
Delay.
At the same time, prior art also substitutes traditional aluminium as in interconnection structure using the smaller copper of resistance coefficient
The material of metal plug, to reduce the resistance of metal plug itself.Simultaneously as the fusing point of copper is high, and anti-electromigration ability
Also it is stronger, relative to the metal plug of traditional aluminum, higher current density can be carried, is entered and is advantageous to and improves shape
Into chip packaging density.Specifically, prior art uses Damascus（Damascene）Or dual damascene (Dual
Damascene) technique forms the metal plug of copper.
But above-mentioned low k dielectric or ultra low k dielectric materials be easy to during dual damascene process by
To damage.For example, generally required in dual damascene process by photoresist to define the groove for needing to be formed（Trench）With
And through hole（Via）, but photoresist is to need to be stripped（strip）, due to low k dielectric or ultra low k dielectric materials
Mostly loose porous structure, not only easily oxidation, and mechanical strength is low, the process for removing photoresist is easy to described low
The interlayer dielectric layer of k dielectric material or ultra low k dielectric materials causes to damage.
So the damage that the interlayer dielectric layer for how reducing low k dielectric or ultra low k dielectric materials is subject to, turns into
Those skilled in the art's urgent problem to be solved.
The content of the invention
The present invention solves the problems, such as to be to provide a kind of method for forming interconnection structure, when forming the interconnection structure of semiconductor
The damage of interlayer dielectric layer is reduced as far as possible.
To solve the above problems, the present invention provides a kind of method for forming interconnection structure, including：
Substrate is provided；
Interlayer dielectric layer is formed over the substrate；
Barrier layer is formed on the interlayer dielectric layer；
Hard mask is formed on the barrier layer, first that the hard mask thickness is formed through in the hard mask opens
Mouthful；
Sacrifice layer is filled in the described first opening, until the sacrifice layer covers the hard mask；
The graphical sacrifice layer, formed in the sacrifice layer in the first opening and expose the barrier layer second and open
Mouthful, second opening is less than the described first opening；
Remove the barrier layer that the second opening is exposed；
The interlayer dielectric layer exposed to the second opening in the sacrifice layer and sacrifice layer after graphical performs etching, to be formed
Through hole；
Using the hard mask as mask, interlayer that etching first interlayer dielectric layer that exposes of opening and through hole expose
Dielectric layer, groove is formed in the interlayer dielectric layer that the described first opening is exposed and the through hole is run through the inter-level dielectric
Layer.
Optionally, the step of filling sacrifice layer in the described first opening includes：Using spin coating or fluid chemistry gas phase
The mode of deposition forms the sacrifice layer.
Optionally, the step of filling sacrifice layer in the described first opening includes：The material of the sacrifice layer is low k dielectric
Material, ultra low k dielectric materials, oxide material, nitride material, tetraethyl orthosilicate, silicon oxynitride, amorphous carbon and have
One or more in machine anti-reflecting layer.
Optionally, the graphical sacrifice layer, in the sacrifice layer in the first opening the step of the opening of formation second
Including：
Anti-reflecting layer is formed on the sacrifice layer；
Anti-reflecting layer described in photoetching and sacrifice layer are open with forming described second；
Remove remaining anti-reflecting layer.
Optionally, the step of forming anti-reflecting layer includes：Amorphous carbon layer and medium are sequentially formed on the sacrifice layer
Anti-reflecting layer.
Optionally, the step of forming anti-reflecting layer includes：Anti-etching dose of organic bottom is sequentially formed on the sacrifice layer
Layer and the anti-reflecting layer based on silicon.
Optionally, remaining anti-reflecting layer is removed using the mixed gas of nitrogen and hydrogen, or, using oxygen, dioxy
Any one changed in carbon, carbon monoxide removes remaining anti-reflecting layer.
Optionally, after the step of groove is formed in interlayer dielectric layer, in addition to：
Metal level is filled into the through hole and groove；
Planarize the metal level and remove unnecessary metal level, retain the metal level in the through hole and groove.
Optionally, the step of forming interlayer dielectric layer over the substrate includes：Low k dielectric is formed on substrate
Interlayer dielectric layer.
Optionally, include in the step of interlayer dielectric layer of formation low k dielectric on substrate：It is low less than 3 to form k values
K dielectric material.
Optionally, the step of forming hard mask includes, and forms the hard mask of titanium nitride or boron nitride material.
Optionally, the interlayer dielectric layer exposed to the second opening in the sacrifice layer and sacrifice layer after graphical is carved
Erosion, the step of to form through hole in, sacrifice layer is removed.
Compared with prior art, technical scheme has advantages below：
The first opening of the invention first formed in the hard mask, to define the ditch subsequently formed in interlayer dielectric layer
Groove, the second opening is then formed in sacrifice layer, to define the through hole subsequently formed in interlayer dielectric layer.Due to the through hole
Defined by the second opening in the sacrifice layer, and the second opening formed is only to expose barrier layer, interlayer dielectric layer
Now expose, compared in the prior art by way of photoresist is come the through hole of the formation defined, in the absence of existing
In technology, the situation of interlayer dielectric layer can be damaged to while removing photoresist.
In addition, using the sacrifice layer after graphical as mask, interlayer dielectric layer that the opening of etching second is exposed, to form through hole
During, sacrifice layer can be completely removed, that is to say, that the step of without setting one of removal sacrifice layer again, also will not
Because remove sacrifice layer and caused by interlayer dielectric layer cross poly-injury, therefore, the present invention will not increase interconnection structure manufacture answer
Miscellaneous degree, while also improve the quality of interconnection structure.
Brief description of the drawings
Fig. 1 to Fig. 9 is the structural representation of each step in method one embodiment of the invention for forming interconnection structure.
Embodiment
In the last part technology of semiconductor manufacturing（backend of the line technology,BEOL）In, frequently with
To Damascus（Damascene）Or dual damascene (Dual Damascene) technique forms interconnection structure.In the work
, it is necessary to define the size of the groove to be formed and through hole and position by forming photoresist, after this in skill, it is also necessary to
Photoresist is removed.Due to low k or ultra low k dielectric materials generally more loose porous, mechanical strength very little, and very easy
It is oxidized, so when being removed to photoresist, it is easy to which low k or ultra low k dielectric materials interlayer dielectric layer are caused
Damage.
For example, wet-cleaning may be used to remove photoresist under certain situation, but due to low k or ultra low k dielectric material
The interlayer dielectric layer of material is easily oxidized, and is easy to that interlayer dielectric layer is caused to damage in cleaning process；Other feelings
Dry method may be used to clean under condition, but the relatively low low k or ultra low k dielectric materials of mechanical strength is also highly susceptible to plasma
The bombardment of body and damage.
Correspondingly, the present invention provides a kind of method for forming interconnection structure, and methods described includes：Substrate is provided；Described
Interlayer dielectric layer is formed on substrate；Barrier layer is formed on the interlayer dielectric layer；Hard mask, institute are formed on the barrier layer
State the first opening that the hard mask thickness is formed through in hard mask；Sacrifice layer is filled in the described first opening, until
The sacrifice layer covers the hard mask；The graphical sacrifice layer, formed and exposed in the sacrifice layer in the first opening
The barrier layer second is open, and second opening is less than the described first opening；Remove the barrier layer that the second opening is exposed；To figure
The interlayer dielectric layer that the second opening is exposed in sacrifice layer and sacrifice layer after shape performs etching, to form through hole；With described
Hard mask is mask, the interlayer dielectric layer that the interlayer dielectric layer and through hole that etching first opening is exposed expose, described
Groove is formed in the interlayer dielectric layer that first opening is exposed and the through hole is run through the interlayer dielectric layer.
The first opening of the invention first formed in the hard mask, to define the ditch subsequently formed in interlayer dielectric layer
Groove, the second opening is then formed in sacrifice layer, to define the through hole subsequently formed in interlayer dielectric layer.Due to the through hole
Defined by the second opening in the sacrifice layer, and the second opening formed is only to expose barrier layer, interlayer dielectric layer
Now expose, compared in the prior art by way of photoresist is come the through hole of the formation defined, in the absence of existing
In technology, the situation of interlayer dielectric layer can be damaged to while removing photoresist.
In addition, using the sacrifice layer after graphical as mask, interlayer dielectric layer that the opening of etching second is exposed, to form through hole
During, sacrifice layer can be completely removed, that is to say, that the step of without setting one of removal sacrifice layer again, also will not
Because remove sacrifice layer and caused by interlayer dielectric layer cross poly-injury, therefore, the present invention will not increase interconnection structure manufacture answer
Miscellaneous degree, while also improve the quality of interconnection structure.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings to the present invention
Specific embodiment elaborate.
With reference to figure 1, there is provided substrate (not shown).The substrate can be silicon substrate, silicon-on-insulator, silicon-Germanium substrate
Deng.In the present embodiment, FEOL has been passed through in the substrate（Frontend of the line technology,
FEOL）Form the semiconductor devices such as grid, source-drain area.Substrate surface may be also formed with metal plug or metal is mutual
Line.But the present invention to this and is not construed as limiting.
Please continue to refer to Fig. 1, interlayer dielectric layer 100 is formed over the substrate, and formed on dielectric layer 100 between described
Barrier layer 110.
In the present embodiment, the interlayer dielectric layer 100 is formed using low k dielectric of the k values less than 3, to subtract as far as possible
Parasitic capacitance between the small metal interconnecting wires being subsequently formed.It should be understood that the present invention is for the inter-level dielectric
The k values of layer 100 do not do any restrictions, in other embodiments of the invention, can use the lower or higher material of k values
The interlayer dielectric layer 100 is formed, so present invention should not be limited with this.
As shown in figure 1, it should also be noted that, in the present embodiment, etch stop layer is also formed with over the substrate
20, for playing a part of etching stopping in the step of etching forms through hole and groove, and in the step for forming through hole and groove
After rapid, the etch stop layer 20 that through hole exposes is removed, in order to which after metal is filled, the metal of filling is with being located at
The parts such as other metal levels or metal plug in substrate are in contact to realize electrical connection.But the etch stop layer 20
The structure only arrived employed in the present embodiment, the present invention should not be limited with this.
Incorporated by reference to reference to figure 1 and Fig. 2, the layer of hard mask material 122, figure are formed on the interlayer dielectric layer 100
Change the layer of hard mask material 122 and form hard mask 120, the thickness of hard mask 120 is formed through in the hard mask 120
First opening, for defining the size of groove in interlayer dielectric layer 100.
In the present embodiment, the hard mask 120 can use titanium nitride（TiN）As material.But the present invention is to this
Also do not limit, such as boron nitride（BN）Etc. can also be as the material of the hard mask 120.
Specifically, the step of graphical layer of hard mask material 122 include：In the layer of hard mask material 122 according to
Secondary formation anti-reflecting layer 210 and photoresist 220.
Photoresist 220 described in photoetching, to form the opening 221 of expose portion anti-reflecting layer 210, wherein, the opening 221
Size d1 be used to define the groove that is subsequently formed in the interlayer dielectric layer 100（trench）Size.
In the present embodiment, the anti-reflecting layer 210 is bottom anti-reflection layer（Bottom Anti-Reflect
Coating,BARC）, but this is not limited by the present invention.
Include with reference to figure 2, the step of graphical layer of hard mask material 122：With the photoresist after being photo-etched in Fig. 1
220 be mask, the anti-reflecting layer 210 exposed, hard mask 120 and partial barrier 110 is etched, to be formed shown in this Fig. 2
First opening 121；The size of first opening 121 is substantially identical with the size d1 of the opening 221 in photoresist 220.
Then photoresist 220 and anti-reflecting layer 210 are removed.
It should be noted that in the present embodiment, before the layer of hard mask material 122 is formed, also it is situated between in the interlayer
Barrier layer 110 is formed on matter layer 100, for being used as etching barrier layer during subsequent etching.
Specifically, the barrier layer 110 can be formed using the material such as silicon nitride, this material and the hard mask
There is larger etching selection ratio between 120.But the present invention is not limited this, can also be formed using other materials
The barrier layer 110, for example, silica, tetraethyl orthosilicate（Tetra Ethyl Ortho Silicate,TEOS）Or
It is one or more kinds of combinations of above-mentioned material.
In the present embodiment, the barrier layer 110 is used to subsequently perform etching with described in formation the hard mask 120
In the step of first opening 121, play a part of etching stop layer.
As shown in figure 3, the 121 filling sacrifice layer 300 in the described first opening, until the sacrifice layer 300 cover it is described
Hard mask 120.The sacrifice layer 300 is used for the etching mask in subsequent step as interlayer dielectric layer 100.
In addition, the material of sacrifice layer 300 can or material character identical with interlayer dielectric layer 100 it is close, sacrifice layer 300 exists
While as etching mask, its own is also thinned or even removed, that is to say, that in subsequent step, in interlayer dielectric layer
After forming through hole in 100, the sacrifice layer 300 is also completely removed.
In the present embodiment, the sacrifice layer 300 is formed using low k or ultra low k dielectric materials, and such benefit exists
In the selection between low k or ultra low k dielectric materials sacrifice layer 300 and the interlayer dielectric layer 100 is smaller, follow-up
The step of in, be advantageous to remove the sacrifice layer 300 while interlayer dielectric layer 100 are etched, that is to say, that be advantageous to
The sacrifice layer 300 can be removed while being performed etching to the interlayer dielectric layer 100.
It should be noted that it can remove and then perform etching completely the step of forming groove, phase in sacrifice layer 300
Ying Di, before sacrifice layer 300 removes completely, in interlayer dielectric layer 100 etching formed for through hole, that is to say, that sacrifice
The thickness of layer 300 is related with the difference of via depth to the groove ultimately formed.The thickness of sacrifice layer 300 need to meet following bar
Part：At least it is filled in first opening and covers the hard mask, while the thickness of sacrifice layer 300 is desirably no more than the layer
Between dielectric layer 100 thickness.In actual process, the thickness of sacrifice layer 300 can be adjusted according to factors such as the etching technics of reality
It is whole.
But in other embodiments of the invention, the material of the sacrifice layer 300 can also be such as DUO（DUV
Light Absorbing Oxide, a kind of ARC of SiO2 bases, contain the elements such as silicon, carbon, oxygen）, such as carbon oxide
Oxide materials such as (Carbon Doped Oxide, CDO), nitride material, tetraethyl orthosilicate, silicon oxynitride, nothing are fixed
Shape carbon, organic antireflection layer, and the combination of one or more above-mentioned materials.
In the present embodiment, can form the sacrifice layer 300 by the way of spin coating, this method relative cost compared with
It is low, and the sacrifice layer 300 formed is in corresponding planarisation step of arranging in pairs or groups（Such as cmp etc.）Afterwards, have preferably flat
Smooth property.But the present invention is without limitation, and the sacrifice layer 300, such as fluid chemistry can also be formed using other manner
Vapour deposition（Fluidized Chemical Vapor Deposition,FCVD）This mode has preferable filling capacity.
As shown in Figure 3 and Figure 4, the graphical sacrifice layer, remove and correspond to the first opening 121（Shown in Fig. 2）In portion
Divide sacrifice layer, to form second opening on exposed portion barrier layer in sacrifice layer.Wherein, second opening is less than described the
One opening.
Specifically, the step of graphical sacrifice layer includes：Sequentially formed on the sacrifice layer anti-reflecting layer 400 with
And photoresist 230.
In the present embodiment, the anti-reflecting layer 400 includes dielectric anti reflective layer 410 and amorphous carbon layer 420.
Photoresist 230 described in photoetching, to form the opening 231 of exposed portion dielectric anti reflective layer 410；The opening 231
Size d2 be used to define the through hole formed in follow-up interlayer dielectric layer 100 described again（via）Size.
It should be noted that the present invention is not construed as limiting for above-mentioned 400 specific material of anti-reflecting layer, and the number of plies,
In the other embodiment of the present invention, anti-reflecting layer 400 can also be the organic bottom being sequentially formed on the sacrifice layer anti-quarter
Lose oxidant layer（organic under-layer resist,ODL）And the anti-reflecting layer based on Si（Si-ARC）, wherein described
ODL layers are that a kind of often arranged in pairs or groups with the Si-ARC layers uses, and have the bottom anti-reflective material of certain filling capacity；Anti-reflective
Penetrate layer 400 and can also be the three-decker that bottom anti-reflection layer, dielectric anti reflective layer and amorphous carbon are formed（tri-layer）.
As shown in figure 4, the step of graphical sacrifice layer, also includes：It is mask with the photoresist 230 after photoetching,
The dielectric anti reflective layer 410 exposed from the opening 231, and amorphous carbon layer 420 and sacrifice layer 300 are etched, so as in institute
Give an account of and the second opening 301 is formed in matter anti-reflecting layer and sacrifice layer 300.Second opening 301 is by the barrier layer 110
A part is exposed.
Then remaining photoresist 230 and dielectric anti reflective layer 410 are removed, because interlayer dielectric layer 100 now has
The sacrifice layer 300 blocks, so the step of removing photoresist 230 will not cause poly-injury to the interlayer dielectric layer 100.
With reference to reference to figure 5, after the graphical sacrifice layer 300, remaining amorphous carbon layer 420 is also removed.
In the present embodiment, dry etching can be used to remove the amorphous carbon layer 420.Oxygen conduct can specifically be used
Etching gas, selection of this gas for amorphous carbon layer 420 is higher, can as far as possible do not interfere with sacrifice layer 300 and
While barrier layer 110, ensure the etching for the greater efficiency of amorphous carbon layer 420.
But the present invention to this and does not limit, the mixed gas of nitrogen or hydrogen, or dioxy can also be used
Change carbon, carbon monoxide removes the amorphous carbon layer 420.
When then removing remaining amorphous carbon layer 420, due to sacrifice layer 300 and barrier layer 110 block, will not be to institute
State interlayer dielectric layer 100 and cause poly-injury.
With reference to figure 6, to inter-level dielectric corresponding to the second opening 301 in the sacrifice layer 300 and sacrifice layer 300 after graphical
Layer 100 performs etching, to form through hole 102（With reference to figure 7）.
Now, due to being all that the selection between the sacrifice layer 300 of low k dielectric, the interlayer dielectric layer 100 is compared
Small, while the interlayer dielectric layer 100 is etched, the sacrifice layer 300 is also being consumed, i.e., described sacrifice layer 300
Thickness is thinned or even removed.
In the present embodiment, after through hole 102 is formed, the sacrifice layer 300 is removed.
In order to ensure that the sidewall profile for the through hole 102 to be formed is ideal, in the present embodiment using dry etching.And have
The etching parameters such as etching agent of body, the material of the interlayer dielectric layer 100 according to actual conditions, should be coordinated to be adjusted
It is whole, the invention is not limited in this regard.
Referring next to Fig. 7, when the through hole 102 be etched depth gradually increase when, sacrifice layer 300 is also little by little disappeared
Consumption, and expose the first opening 121 in hard mask 120.
With reference to reference to figure 8, it is mask with the hard mask 120, etches the inter-level dielectrics that first opening 121 is exposed
Layer, until the through hole 102 runs through the interlayer dielectric layer 100, and the interlayer dielectric layer exposed in the described first opening 121
Groove 101 is formed in 100（trench）.
It is in the present embodiment, further comprising the steps of after the through hole 102 and groove 101 is formed：
The partial etching stop layer 20 positioned at the bottom of through hole 102 is removed, exposes substrate；
Metal level is filled in the groove and through hole 102（Not shown in figure）；
Unnecessary metal level is removed by flatening process, to form the interconnection structure with damascene structure.
In the present embodiment, the flatening process is cmp（CMP）.
In the present embodiment, the metal interconnecting wires 50 can be used described in electroplating technology filling using copper as material
Metal level, still, the present invention should not be limited with this, the metal interconnecting wires can also be formed using such as aluminium, tungsten other materials
50, the metal level can also be formed using other techniques.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art, this is not being departed from
In the spirit and scope of invention, it can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
The scope of restriction is defined.
Claims (11)
- A kind of 1. method for forming interconnection structure, it is characterised in that including：Substrate is provided；Interlayer dielectric layer is formed over the substrate；Barrier layer is formed on the interlayer dielectric layer；Hard mask is formed on the barrier layer, the first opening of the hard mask thickness is formed through in the hard mask；Sacrifice layer is filled in the described first opening, until the sacrifice layer covers the hard mask；The graphical sacrifice layer, the second opening for exposing the barrier layer is formed in the sacrifice layer in the first opening, Second opening is less than the described first opening；Wherein, the graphical sacrifice layer,The step of forming the second opening in the sacrifice layer in the first opening includes：Anti-reflecting layer is formed on the sacrifice layer；Anti-reflecting layer described in photoetching and sacrifice layer are open with forming described second；Remove remaining anti-reflecting layer；Remove the barrier layer that the second opening is exposed；The interlayer dielectric layer exposed to the second opening in the sacrifice layer and sacrifice layer after graphical performs etching, logical to be formed Hole；Using the hard mask as mask, inter-level dielectric that etching first interlayer dielectric layer that exposes of opening and through hole expose Layer, groove is formed in the interlayer dielectric layer that the described first opening is exposed and the through hole is run through the interlayer dielectric layer.
- 2. the method as described in claim 1, it is characterised in that the step of filling sacrifice layer in the described first opening includes： The sacrifice layer is formed by the way of spin coating or fluid chemistry vapour deposition.
- 3. the method as described in claim 1, it is characterised in that the step of filling sacrifice layer in the described first opening includes： The material of the sacrifice layer is low k dielectric, ultra low k dielectric materials, oxide material, nitride material, tetrem base silicon One or more in hydrochlorate, silicon oxynitride, amorphous carbon and organic antireflection layer.
- 4. the method as described in claim 1, it is characterised in that the step of forming anti-reflecting layer includes：On the sacrifice layer Sequentially form amorphous carbon layer and dielectric anti reflective layer.
- 5. the method as described in claim 1, it is characterised in that the step of forming anti-reflecting layer includes：On the sacrifice layer Sequentially form the anti-etching oxidant layer of organic bottom and the anti-reflecting layer based on silicon.
- 6. method as claimed in claim 4, it is characterised in that remaining anti-reflective is removed using the mixed gas of nitrogen and hydrogen Layer is penetrated, or, remaining anti-reflecting layer is removed using any one in oxygen, carbon dioxide and carbon monoxide.
- 7. the method as described in claim 1, it is characterised in that after the step of groove is formed in interlayer dielectric layer, also wrap Include：Metal level is filled into the through hole and groove；Planarize the metal level and remove unnecessary metal level, retain the metal level in the through hole and groove.
- 8. the method as described in claim 1, it is characterised in that the step of forming interlayer dielectric layer over the substrate includes： The interlayer dielectric layer of low k dielectric is formed on substrate.
- 9. method as claimed in claim 8, it is characterised in that the interlayer dielectric layer of low k dielectric is formed on substrate Step includes：Form the low k dielectric that k values are less than 3.
- 10. the method as described in claim 1, it is characterised in that the step of forming hard mask includes, and forms titanium nitride or nitridation The hard mask of boron material.
- 11. the method as described in claim 1, it is characterised in that open in the sacrifice layer and sacrifice layer after graphical second The interlayer dielectric layer that exposes of mouth performs etching, the step of to form through hole in, sacrifice layer is removed.
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| CN106706172A (en) * | 2015-11-12 | 2017-05-24 | 上海丽恒光微电子科技有限公司 | Preparation method of pressure sensor |
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| CN112071804A (en) * | 2020-09-17 | 2020-12-11 | 长江存储科技有限责任公司 | Semiconductor device and manufacturing method thereof |
| CN113488392B (en) * | 2021-07-13 | 2022-08-02 | 武汉新芯集成电路制造有限公司 | Method for manufacturing integrated circuit device |
| CN114182202B (en) * | 2021-12-06 | 2023-11-24 | 江西省纳米技术研究院 | Micromachining method for metal pattern of electronic device |
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| CN1433062A (en) * | 2002-01-10 | 2003-07-30 | 联华电子股份有限公司 | Method of forming opening in low dielectric constant material |
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| US20030008490A1 (en) * | 2001-07-09 | 2003-01-09 | Guoqiang Xing | Dual hardmask process for the formation of copper/low-k interconnects |
| US7132369B2 (en) * | 2002-12-31 | 2006-11-07 | Applied Materials, Inc. | Method of forming a low-K dual damascene interconnect structure |
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| CN1433062A (en) * | 2002-01-10 | 2003-07-30 | 联华电子股份有限公司 | Method of forming opening in low dielectric constant material |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106706172A (en) * | 2015-11-12 | 2017-05-24 | 上海丽恒光微电子科技有限公司 | Preparation method of pressure sensor |
| CN106706172B (en) * | 2015-11-12 | 2021-04-02 | 上海丽恒光微电子科技有限公司 | Preparation method of pressure sensor |
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