CN111128865A - Damascus interconnection process - Google Patents
Damascus interconnection process Download PDFInfo
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- CN111128865A CN111128865A CN201911308086.3A CN201911308086A CN111128865A CN 111128865 A CN111128865 A CN 111128865A CN 201911308086 A CN201911308086 A CN 201911308086A CN 111128865 A CN111128865 A CN 111128865A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/7681—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving one or more buried masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76813—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving a partial via etch
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention relates to a Damascus interconnection process, in particular to a semiconductor integrated circuit manufacturing process.A second cap layer is deposited by carrying out a back-etching process on a metal hard mask layer pattern, covers the side wall of the metal hard mask layer, and is reserved until a cleaning process, so that the chance that the side wall of the metal hard mask layer is contacted with the atmospheric environment and reacts with water vapor in the air to generate a compound is avoided, the copper filling defect is reduced, and the yield of a semiconductor device is improved.
Description
Technical Field
The invention relates to a semiconductor integrated circuit manufacturing process, in particular to a Damascus interconnection process.
Background
In the semiconductor manufacturing technology, with the continuous reduction of the device size, the damascene interconnection technology is commonly used in the industry, and in the damascene copper interconnection technology, a device is required to be etched to form a copper interconnection trench, then a copper diffusion barrier layer is deposited to cover the inner surface of the copper interconnection trench, and then metal copper is filled and chemical mechanical polishing is performed to obtain a required structure.
In addition, as the Critical Dimension (CD) of the back-end process is reduced, a Metal Hard Mask (MHM) such as TIN (TIN) is increasingly used in the damascene interconnection process. Some semiconductor foundries use metal hard masks starting at 65 nm. The pattern is transferred to the metal hard mask layer through photoetching and etching processes, the pattern is transferred to the dielectric layer by taking the metal hard mask layer as a mask, a through hole and a groove which are inlaid are formed in the dielectric layer, copper is filled in the through hole and the groove, and a Chemical Mechanical Polishing (CMP) planarization process is carried out, so that copper interconnection is formed. The use of the metal hard mask layer can have good selectivity and structure retention for the underlying dielectric layer. However, in the damascene interconnection process, the metal hard mask layer is liable to react with water vapor in the air to generate compounds, which leads to the subsequent copper filling defect, and further leads to the reduction of the yield of the semiconductor device.
Specifically, referring to fig. 1a-1b, fig. 1a-1b are schematic diagrams illustrating defects generated in a metal hard mask layer in the prior art, such as copper defects shown in fig. 1b caused by peeling off of the metal hard mask layer shown in fig. 1 a.
Disclosure of Invention
The invention aims to provide a Damascus interconnection process method to reduce metal filling defects and further improve the yield of semiconductor devices.
The invention provides a Damascus interconnection process method, which comprises the following steps: s1: providing a front layer, and sequentially forming a nitrogen-doped silicon carbide layer, an interlayer dielectric layer, a hard mask oxidation layer, a metal hard mask layer and an oxide cap layer on the front layer; s2: carrying out photoetching process to form metal hard mask layer patterns and grooves between the metal hard mask layer patterns; s3: carrying out back etching process on the metal hard mask layer pattern, and then carrying out deposition process to deposit a second cap layer, wherein the second cap layer covers the surfaces of the oxide cap layer and the hard mask oxide layer and the side walls of the oxide cap layer and the metal hard mask layer; s4: depositing a bottom anti-reflection layer and a photoresist layer in sequence, and carrying out a photoetching exposure process to form contact hole pattern morphology at the position on the photoresist layer corresponding to the groove between the metal hard mask layer patterns; s5: sequentially etching the bottom anti-reflection layer, the second cap layer and the hard mask oxide layer into the interlayer dielectric layer to form a contact hole, extending the contact hole into the interlayer dielectric layer, and removing the photoresist layer; s6: removing the bottom anti-reflection layer; s7: etching to remove the second cap layer and the oxide cap layer on the surface, continuously etching the interlayer dielectric layer until the nitrogen-doped silicon carbide layer stops, and forming a groove and a contact hole extending to the bottom of the interlayer dielectric layer; and S8: and cleaning and removing the metal hard mask layer, the second cap layer on the side of the metal hard mask layer and the hard mask oxide layer.
Further, in step S1, the nitrogen doped silicon carbide layer has a thickness between 250 and 700 angstroms.
Further, in step S1, the thickness of the interlayer dielectric layer is between 1500 angstroms and 6000 angstroms.
Further, in step S1, the hard mask oxide layer has a thickness of 100 to 500 angstroms.
Further, in step S1, the metal hard mask layer is a titanium nitride metal hard mask layer.
Further, in step S1, the metal hard mask layer has a thickness of between 300 and 700 angstroms.
Further, in step S1, the thickness of the oxide capping layer is between 30 and 100 angstroms.
Further, in step S3, the etching-back process has an etching-back thickness of 3nm to 10 nm.
Further, in step S3, the second cap layer formed by the deposition process has a thickness of 3nm to 10 nm.
Further, in step S3, the etch-back process has an etch-back thickness equal to the thickness of the second cap layer formed by the deposition process.
Further, step S7 includes etching the nitrogen-doped silicon carbide layer at the bottom of the contact hole to form a final contact hole.
Further, step S8 includes etching the nitrogen-doped silicon carbide layer at the bottom of the contact hole to form a final contact hole.
Furthermore, the front layer is a metal layer or a semiconductor substrate.
Further, in step S2, the etching process stops on the hard mask oxide layer.
Further, the second cap layer is a silicon nitride layer.
According to the Damascus interconnection process provided by the invention, the metal hard mask layer pattern is subjected to a back etching process, then a second cap layer is deposited, the second cap layer covers the side wall of the metal hard mask layer, and the second cap layer covering the side wall of the metal hard mask layer is reserved until the second cap layer is subjected to a cleaning process, so that the chance that the side wall of the metal hard mask layer is contacted with the atmospheric environment and reacts with water vapor in the air to generate a compound is avoided, the copper filling defect is reduced, and the yield of a semiconductor device is improved.
Drawings
FIGS. 1a-1b are schematic diagrams illustrating the defect generation of a metal hard mask layer in the prior art.
FIG. 2 is a process flow diagram of a damascene interconnect process according to an embodiment of the invention.
FIGS. 3a-3h are schematic views of a damascene interconnect process according to an embodiment of the invention.
Detailed Description
The technical solutions in the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.
In one embodiment of the present invention, a damascene interconnect process is provided. Referring to fig. 2, fig. 2 is a flow chart of a damascene interconnect process according to an embodiment of the invention, and fig. 3a to 3h are combined, and fig. 3a to 3h are schematic diagrams of a damascene interconnect process according to an embodiment of the invention. Specifically, the damascene interconnection process method of an embodiment of the present invention includes:
s1: providing a front layer 110, and sequentially forming a nitrogen-doped silicon carbide (NDC) layer 120, an interlayer dielectric layer 130, a hard mask oxide (HM OX)140, a metal hard mask layer 150, and an oxide cap layer 160 on the front layer 110, as shown in fig. 3 a;
in one embodiment, the thickness of the nitrogen doped silicon carbide layer 120 is between 250 angstroms and 700 angstroms.
In one embodiment of the present invention, the interlayer dielectric layer 130 may be a low dielectric constant material layer (LK material layer) which is a material mainly including SiCOH and IMD and has a thickness of 1500 to 6000 angstroms.
In one embodiment of the present invention, the hard mask oxide layer 140 is a hard mask silicon dioxide layer having a thickness of between 100 angstroms and 500 angstroms.
In one embodiment of the present invention, the metal hard mask layer 150 is a titanium nitride metal hard mask layer (MHM TIN) having a thickness of between 300 angstroms and 700 angstroms.
In one embodiment of the present invention, the oxide capping layer 160 is a silicon dioxide capping layer (OX Cap) having a thickness of between 30 angstroms and 100 angstroms.
In an embodiment of the present invention, the front layer 110 is a metal layer (e.g., copper) or a semiconductor substrate, and more particularly, may be a metal contact layer on the semiconductor substrate.
S2: performing a photolithography etching process to form the metal hard mask layer patterns 151 and the trenches between the metal hard mask layer patterns 151, please refer to fig. 3 b;
in an embodiment of the present invention, the etching process is dry etching.
In an embodiment of the present invention, the etching process is stopped on the hard mask oxide layer 140.
S3: performing an etch-back process on the metal hard mask layer pattern 151, and then performing a deposition process to deposit a second cap layer 170, where the second cap layer 170 covers the surfaces of the oxide cap layer 160 and the hard mask oxide layer 140 and the sidewalls of the oxide cap layer 160 and the metal hard mask layer 150, please refer to fig. 3 c;
in an embodiment of the present invention, the etching-back process is a wet etching process, for example, a wet etching process using a solution such as EKC.
In an embodiment of the present invention, the back etching thickness of the back etching process is between 3nm and 10nm, that is, both sides of the metal hard mask layer pattern 151 are reduced by a dimension between 3nm and 10 nm.
In an embodiment of the present invention, the second cap layer 170 formed by the deposition process has a thickness of 3nm to 10 nm.
In an embodiment of the present invention, the back-etching process has a back-etching thickness equal to that of the second cap layer 170 formed by the deposition process, so as not to affect the size of the semiconductor device.
In an embodiment of the invention, the second cap layer 170 is a silicon nitride layer.
S4: depositing a bottom anti-reflection coating (BARC)180 and a photoresist layer 190 in sequence, performing a photolithography exposure process, and forming a contact hole pattern morphology 191 at a position on the photoresist layer 190 corresponding to a trench between the metal hard mask layer patterns 151, as shown in fig. 3 d;
s5: sequentially etching the bottom anti-reflection layer 180, the second cap layer 170, and the hard mask oxide layer 140 into the interlayer dielectric layer 130, forming a contact hole 192 and extending the contact hole into the interlayer dielectric layer 130, and removing the photoresist layer 190, as shown in fig. 3 e;
s6: removing the bottom anti-reflection layer 180, please refer to FIG. 3 f;
s7: etching to remove the second cap layer 170 and the oxide cap layer 160 on the surface and continuing to etch the interlayer dielectric layer 130 until the nitrogen-doped silicon carbide layer 120 stops, forming a trench 193 and a contact hole 192 extending to the bottom of the interlayer dielectric layer 130, as shown in fig. 3 g;
more specifically, in one embodiment of the present invention, step S7 further includes continuing to etch the nitrogen-doped silicon carbide layer 120 at the bottom of the contact hole 192 to form a final contact hole.
S8: the metal hard mask layer 150, the second cap layer 170 on the side of the metal hard mask layer 150, and the hard mask oxide layer 140 are removed by cleaning, as shown in fig. 3 h.
More specifically, in one embodiment of the present invention, step S8 further includes continuing to etch the nitrogen-doped silicon carbide layer 120 at the bottom of the contact hole 192 to form a final contact hole.
As described above, the metal hard mask layer pattern is etched back in step S3, and then a second cap layer is deposited, the second cap layer covers the sidewall of the metal hard mask layer, and the second cap layer covering the sidewall of the metal hard mask layer is remained until the cleaning process in step S8, so that the chance that the sidewall of the metal hard mask layer contacts the atmospheric environment and reacts with water vapor in the air to generate a compound is avoided, thereby reducing the metal filling defect and further improving the yield of the semiconductor device.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (15)
1. A Damascus interconnection process method is characterized by comprising the following steps:
s1: providing a front layer, and sequentially forming a nitrogen-doped silicon carbide layer, an interlayer dielectric layer, a hard mask oxidation layer, a metal hard mask layer and an oxide cap layer on the front layer;
s2: carrying out photoetching process to form metal hard mask layer patterns and grooves between the metal hard mask layer patterns;
s3: carrying out back etching process on the metal hard mask layer pattern, and then carrying out deposition process to deposit a second cap layer, wherein the second cap layer covers the surfaces of the oxide cap layer and the hard mask oxide layer and the side walls of the oxide cap layer and the metal hard mask layer;
s4: depositing a bottom anti-reflection layer and a photoresist layer in sequence, and carrying out a photoetching exposure process to form contact hole pattern morphology at the position on the photoresist layer corresponding to the groove between the metal hard mask layer patterns;
s5: sequentially etching the bottom anti-reflection layer, the second cap layer and the hard mask oxide layer into the interlayer dielectric layer to form a contact hole, extending the contact hole into the interlayer dielectric layer, and removing the photoresist layer;
s6: removing the bottom anti-reflection layer;
s7: etching to remove the second cap layer and the oxide cap layer on the surface, continuously etching the interlayer dielectric layer until the nitrogen-doped silicon carbide layer stops, and forming a groove and a contact hole extending to the bottom of the interlayer dielectric layer; and
s8: and cleaning and removing the metal hard mask layer, the second cap layer on the side of the metal hard mask layer and the hard mask oxide layer.
2. The damascene interconnect process of claim 1, wherein in step S1, the thickness of the nitrogen doped silicon carbide layer is between 250 and 700 angstroms.
3. The damascene interconnection process of claim 1, wherein in step S1, the thickness of the interlayer dielectric layer is between 1500 angstroms and 6000 angstroms.
4. The damascene interconnection process of claim 1, wherein in step S1, the hard mask oxide layer has a thickness of 100 to 500 angstroms.
5. The damascene interconnection process of claim 1, wherein in step S1, the metal hard mask layer is a titanium nitride metal hard mask layer.
6. The damascene interconnection process of claim 1 or 5, wherein in step S1, the thickness of the metal hard mask layer is between 300 and 700 angstroms.
7. The damascene interconnect process of claim 1, wherein in step S1, the thickness of the capping oxide layer is between 30 and 100 angstroms.
8. The damascene interconnection process of claim 1, wherein in step S3, the etch-back process has an etch-back thickness of 3nm to 10 nm.
9. The damascene interconnection process of claim 1, wherein in step S3, the second capping layer formed by the deposition process has a thickness of 3nm to 10 nm.
10. The damascene interconnection process of claim 1, wherein in step S3, the etch-back process has an etch-back thickness equal to the thickness of the second capping layer formed by the deposition process.
11. The damascene interconnection process of claim 1, further comprising continuing to etch open the nitrogen doped silicon carbide layer at the bottom of the contact hole to form a final contact hole in step S7.
12. The damascene interconnection process of claim 1, further comprising continuing to etch open the nitrogen doped silicon carbide layer at the bottom of the contact hole to form a final contact hole in step S8.
13. The damascene interconnection process of claim 1, wherein the front layer is a metal layer or a semiconductor substrate.
14. The damascene interconnection process of claim 1, wherein in step S2, the etching process stops on the hard mask oxide layer.
15. The damascene interconnect process of claim 1, wherein the second capping layer is a silicon nitride layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201911308086.3A CN111128865A (en) | 2019-12-18 | 2019-12-18 | Damascus interconnection process |
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| CN201911308086.3A CN111128865A (en) | 2019-12-18 | 2019-12-18 | Damascus interconnection process |
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Citations (8)
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| CN1433062A (en) * | 2002-01-10 | 2003-07-30 | 联华电子股份有限公司 | Method of forming opening in low dielectric constant material |
| US20050014384A1 (en) * | 2003-07-18 | 2005-01-20 | Cho Ihl Hyun | Method of forming metal line in semiconductor device |
| CN101359619A (en) * | 2007-08-01 | 2009-02-04 | 联华电子股份有限公司 | Interconnecting process |
| US20130078806A1 (en) * | 2011-09-28 | 2013-03-28 | Shanghai Huali Microelectronics Corporation | Method for Fabricating Copper Interconnections in an Ultra Low Dielectric Constant Film |
| CN103337476A (en) * | 2013-06-27 | 2013-10-02 | 上海华力微电子有限公司 | Method for reducing critical size of copper interconnection groove |
| CN104183538A (en) * | 2013-05-21 | 2014-12-03 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device manufacturing method |
| CN106684031A (en) * | 2015-11-05 | 2017-05-17 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of semiconductor structure |
| US20190355617A1 (en) * | 2018-05-21 | 2019-11-21 | Tokyo Electron Limited | Atomic Layer Deposition For Low-K Trench Protection During Etch |
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2019
- 2019-12-18 CN CN201911308086.3A patent/CN111128865A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1433062A (en) * | 2002-01-10 | 2003-07-30 | 联华电子股份有限公司 | Method of forming opening in low dielectric constant material |
| US20050014384A1 (en) * | 2003-07-18 | 2005-01-20 | Cho Ihl Hyun | Method of forming metal line in semiconductor device |
| CN101359619A (en) * | 2007-08-01 | 2009-02-04 | 联华电子股份有限公司 | Interconnecting process |
| US20130078806A1 (en) * | 2011-09-28 | 2013-03-28 | Shanghai Huali Microelectronics Corporation | Method for Fabricating Copper Interconnections in an Ultra Low Dielectric Constant Film |
| CN104183538A (en) * | 2013-05-21 | 2014-12-03 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device manufacturing method |
| CN103337476A (en) * | 2013-06-27 | 2013-10-02 | 上海华力微电子有限公司 | Method for reducing critical size of copper interconnection groove |
| CN106684031A (en) * | 2015-11-05 | 2017-05-17 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of semiconductor structure |
| US20190355617A1 (en) * | 2018-05-21 | 2019-11-21 | Tokyo Electron Limited | Atomic Layer Deposition For Low-K Trench Protection During Etch |
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Application publication date: 20200508 |