CN102412188A - Metal hard mask dual damascene process of super-thick top metal - Google Patents
Metal hard mask dual damascene process of super-thick top metal Download PDFInfo
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- CN102412188A CN102412188A CN2011101236658A CN201110123665A CN102412188A CN 102412188 A CN102412188 A CN 102412188A CN 2011101236658 A CN2011101236658 A CN 2011101236658A CN 201110123665 A CN201110123665 A CN 201110123665A CN 102412188 A CN102412188 A CN 102412188A
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Abstract
The invention relates to the technical field of semiconductor manufacture,more precisely, the invention relates to a metal hard mask dual damascene process of super-thick top metal. The process comprises the following steps: firstly, depositing a through hole dielectric barrier layer, a through hole dielectric layer and a through hole metal hard mask on a wafer substrate; secondly, carrying out photo-etching on the metal hard mask to open the metal hard mask and form a through hole opening and a trench barrier layer; then depositing a trench dielectric layer and a trench metal hard mask on the trench barrier layer; carrying out photo-etching on the trench metal hard mask to form a trench opening; etching the dielectric layer to form a trench and a through hole; depositing a metal barrier layer and a copper seed crystal layer on the trench and the through hole obtained in the previous step, and electroplating the copper to fill the through hole and the trench; and finally, carrying out chemical mechanical grinding planarization to remove excess metal and trench metal hard mask. According to the invention, the problem of height-depth-width ratio and size control of through hole in through hole etching in the existing method can be solved, and the process in the invention can reduce the production cost and shorten the production cycle.
Description
Technical field
The present invention relates to a kind of semiconductor fabrication technical field, more precisely, the present invention relates to a kind of metal hard mask dual damascene process of ultra thick top-level metallic.
Background technology
In existing semiconductor components and devices manufacturing technology, film inductor is the important component part of RF IC.For inductor, quality factor is a very important parameter.Quality factor is high more, and the power consumption of inductor is more little, efficient is high more.In order to improve the inductor quality factor, require to improve as far as possible gash depth to reduce the inductor dead resistance.The present ultra thick metal layers of the common used thickness of industry more than 3 μ m.And the dual damascene manufacturing process through first all-pass hole (Via) back groove (Trench), the depth-to-width ratio of via etch surpasses more than the 10:1, and via etch process is difficult to realize.
At present, single Damascus manufacturing process of making through hole (Via) and groove (Trench) respectively commonly used in the manufacture process of the inherent ultra thick top-level metallic of semiconductor industry.Use this manufacturing process, deposition of dielectric layer at first, photoetching via hole image and adopt dry etching through hole depositing metal barrier layer and copper seed layer and fill up through hole with electro-coppering is subsequently then removed excess metal with cmp subsequently; After accomplishing through hole, deposition of dielectric layer and photoetching form groove figure once more on through hole, adopt dry etching groove depositing metal barrier layer and copper seed layer and fill up groove with electro-coppering subsequently, then remove excess metal with cmp once more.This kind technology has solved the problem of via etch high-aspect-ratio, but this technology can increase the processing step of making, and extends manufacture cycle.
Also have,, can first etched portions through hole solve the problem of all-pass hole etching high-aspect-ratio, but this method is difficult to the control clear size of opening like groove dual damascene manufacture craft after the disclosed a kind of first partial through holes of patent US7297629.Use the high selectivity dielectric material as hard mask manufacture double damask structure respectively like disclosed a kind of method through hole of patent US7452806 and groove, but little for the hard mask etch process window of dielectric material, be difficult to the realization superelevation and select to compare etching technics.These two kinds of technologies all can't solve the problem of etching technics control when solving via etch high-aspect-ratio problem.
A kind of new dual damascene process that the present invention proposes in order to satisfy the demand in the present semiconductor production application is just made ultra thick top-level metallic, to solve the deficiency in the existing production technology.
Summary of the invention
In view of the above problems, the present invention provides a kind of metal hard mask dual damascene process of ultra thick top-level metallic, may further comprise the steps:
Step 4 is opened the hard mask of trench metal through chemical wet etching and is formed groove opening;
Step 5 forms groove through the hard mask groove opening of described trench metal etching groove dielectric layer, and further through the hard mask via opening of via metal etching through hole dielectric layer, to form through hole;
Step 6, depositing metal barrier layer and copper seed layer on the groove of gained and through hole, and described through hole and groove are filled up in electro-coppering;
Above-mentioned technology wherein, when opening hard mask formation via openings of via metal and trench barrier, adopts the Twi-lithography etching technics to open hard mask via opening and formation trench barrier respectively.
Above-mentioned technology wherein, when opening hard mask formation via openings of via metal and trench barrier, adopts a chemical wet etching technology to open hard mask via opening simultaneously and form trench barrier.
Above-mentioned technology, wherein, said dielectric barrier layer is SiN, SiC, SiCN of chemical vapor deposition etc.
Above-mentioned technology, wherein, described via dielectric layer and trench dielectric layer adopt the chemical vapor deposition Si oxide.
Above-mentioned technology, wherein, said chemical vapor deposition Si oxide comprises the silicate glass of pure silicon silicate glass or fluoridize.
Above-mentioned technology, wherein, said metal barrier is the TaN/Ta metal barrier.
Above-mentioned technology, wherein, the thickness of described trench dielectric layer >=3 μ m.
Above-mentioned technology, wherein, hard mask of said via metal and the hard mask of trench metal are TaN, Ta, TiN, Ti of chemical vapor deposition or physical vapor deposition etc.
Above-mentioned technology, wherein, the size of said trench barrier is greater than the size of said groove.
Above-mentioned technology wherein, during the substep technological operation of said step 5, adopts wet-cleaned to remove the polymer that gathers because of etching behind the etching groove.
The metal hard mask dual damascene process of the ultra thick top-level metallic of the present invention, advantage is:
1. the preparation production technology that provided of the metal hard mask dual damascene process of the ultra thick top-level metallic of the present invention can reduce processing step, shortens the production cycle.
2. the preparation production technology that provided of the metal hard mask dual damascene process of the ultra thick top-level metallic of the present invention can reduce production costs.
3. the preparation technology that provided of the metal hard mask dual damascene process of the ultra thick top-level metallic of the present invention can satisfy via etch high-aspect-ratio and control clear size of opening simultaneously.
Those skilled in the art reads the detailed description of following preferred embodiment, and with reference to after the accompanying drawing, of the present invention these are incited somebody to action obvious with otherwise advantage undoubtedly.
Description of drawings
With reference to appended accompanying drawing, to describe embodiments of the invention more fully.Yet appended accompanying drawing only is used for explanation and sets forth, and does not constitute limitation of the scope of the invention.
Fig. 1-the 8th, the schematic flow sheet of the metal hard mask dual damascene process of the ultra thick top-level metallic of the present invention.
Embodiment
Shown in Fig. 1-8, in the metal hard mask dual damascene process of the ultra thick top-level metallic of the present invention,
1) at first on a wafer matrix 1, distinguishes deposit through hole dielectric barrier layer 2, via dielectric layer 3 and the hard mask 4 of via metal from bottom to top;
2) on described metal hard mask 4, coat photoresist 5 subsequently; Photoetching forms the figure 6 of through hole and trench barrier; Utilize etching technics to open metal hard mask 4 to it subsequently and form via openings and trench barrier 7, wherein, when forming via openings and trench barrier 7; Adopt the Twi-lithography etching to open hard mask via and formation trench barrier 7 respectively, or a chemical wet etching is opened hard mask via simultaneously and is formed trench barrier 7;
3) deposit trench dielectric layer from bottom to top 8 and the hard mask 9 of trench metal successively on trench barrier 7 again;
4) groove figure of opening along photoetching 10 is carried out etching technics and is formed groove opening to open the hard mask 9 of trench metal;
5) form groove 11 through described groove opening etching groove dielectric layer 8; And further form through hole 12 through via openings etching through hole dielectric layer 3 and through-hole blocking layer 2; Wherein, in this step, can adopt the direct etching groove 11 of a step process and through hole 12 or branch step process to separate etching groove 11 and through hole 12;
6) depositing metal barrier layer (TaN/Ta) and copper seed layer on the groove of back gained 11 and through hole 12, and described through hole 12 and groove 11 are filled up in electro-coppering 13;
7) at last the material surface of gained is carried out the cmp planarization and remove excess metal and the remaining hard mask 9 of trench metal.
As shown in Figure 1, go up the hard mask 4 of deposit through hole dielectric barrier layer 2, via dielectric layer 3 and via metal from bottom to top respectively in a wafer matrix 1.Wherein, through hole dielectric barrier layer 2 is general to adopt the materials such as SiN, SiC, SiCN of chemical vapor depositions, and described via dielectric layer 3 then adopts the chemical vapor deposition Si oxide, like the silicate glass (FSG) of pure silicon silicate glass (USG) or fluoridize etc.; Formations such as the TaN of metal hard mask 4 employings chemical vapor deposition or physical vapor deposition, Ta, TiN, Ti.
Among Fig. 2, coat photoresist 5 on the described metal hard mask 4, adopt photoetching on metal hard mask 4, to form through hole and trench barrier figure 6.
In Fig. 3; Metal hard mask 4 (Fig. 2) along photoetching is opened is gone up formation through hole and trench barrier figure 6 (Fig. 2); Utilize etching technics to open metal hard mask 4 (Fig. 2) to it and form via openings and trench barrier 7, and ashing removal photoresistance obtains bright and clean material surface.
Among Fig. 4, capable more from bottom to top deposit trench dielectric layer 8 and the hard mask 9 of trench metal on trench barrier shown in Figure 37; Wherein, described trench dielectric layer 8 adopts the chemical vapor deposition Si oxides, like the silicate glass (FSG) of pure silicon silicate glass (USG) or fluoridize etc., and the thickness of trench dielectric layer 8 >=3 μ m; Formations such as the TaN of the hard mask of trench metal 9 employings chemical vapor deposition or physical vapor deposition, Ta, TiN, Ti.
As shown in Figure 5, after the deposit trench dielectric layer of accomplishing last step 8 and the hard mask 9 of trench metal, on the hard mask 9 of trench metal, coat photoresist 14, and photoetching forms groove figure 10.
According to Fig. 6 and shown in Figure 7; After forming groove figure 10, adopt and divide step process to separate etching groove 11 and through hole 12, in this step; The etching groove metal hard mask 9 formation groove opening that opens it, ashing are subsequently removed photoresistance and are also continued etching groove dielectric layer 8 and form grooves 11.Established trench barrier is connected in the operation of the groove 11 of gained and preorder, and the size of groove 11 is less than trench barrier 7.
Among Fig. 7, connect last procedure, after etching groove 11, and then the operation of etching through hole 12, wherein, the via dielectric layer 3 of trench barrier 7 under stopping it served as the hard mask of through hole 12 when preventing to be etched simultaneously; Before etching through hole 12, remove the polymer that gathers because of etching groove 11 with wet-cleaned earlier, carry out etching operation subsequently, the via dielectric layer 3 of trench barrier 7 belows is retained, and etching forms through hole 12.
In Fig. 8; Depositing metal barrier layer (TaN/Ta) and copper seed layer are also filled up through hole 12 and groove 11 with electro-coppering 13 on groove 11 and through hole 12; Then remove excess metal and the remaining hard mask 9 of trench metal, the promptly final metal hard mask dual damascene process of accomplishing ultra thick top-level metallic provided by the present invention with cmp.
Through explanation and accompanying drawing, provided the exemplary embodiments of the ad hoc structure of embodiment, for example, this case is to carry out groove with TaN/Ta metal barrier and electro-coppering to fill up operation, based on the present invention's spirit, above-mentioned material is the conversion of available other materials also.Although foregoing invention has proposed existing preferred embodiment, yet these contents are not as limitation.
For a person skilled in the art, read above-mentioned explanation after, various variations and revise undoubtedly will be obvious.Therefore, appending claims should be regarded whole variations and the correction of containing true intention of the present invention and scope as.Any and all scope of equal value and contents all should be thought still to belong in the intent of the present invention and the scope in claims scope.
Claims (11)
1. the metal hard mask dual damascene process of a ultra thick top-level metallic is characterized in that, may further comprise the steps:
Step 1 is deposited with the hard mask of through hole dielectric barrier layer, via dielectric layer and via metal from bottom to top respectively on a wafer matrix;
Step 2 is utilized chemical wet etching technology to open the hard mask of via metal on described metal hard mask and is formed via openings and trench barrier;
Step 3, deposit trench dielectric layer from bottom to top and the hard mask of trench metal successively on the trench barrier that forms;
Step 4 is opened the hard mask of trench metal through chemical wet etching and is formed groove opening;
Step 5 forms groove through the hard mask groove opening of described trench metal etching groove dielectric layer, and is further passing through the hard mask via opening of via metal etching through hole dielectric layer, to form through hole;
Step 6, depositing metal barrier layer and copper seed layer on the groove of gained and through hole, and described through hole and groove are filled up in electro-coppering;
Step 7 is carried out the cmp planarization to the material surface of gained and is removed excess metal, and the remaining hard mask of trench metal.
2. technology according to claim 1 is characterized in that, when opening hard mask formation via openings of via metal and trench barrier, adopts the Twi-lithography etching technics to open hard mask via opening and formation trench barrier respectively.
3. technology according to claim 1 is characterized in that, when opening hard mask formation via openings of via metal and trench barrier, adopts a chemical wet etching technology to open hard mask via opening simultaneously and form trench barrier.
4. technology according to claim 1 is characterized in that, said dielectric barrier layer is SiN, SiC, the SiCN of chemical vapor deposition.
5. technology according to claim 1 is characterized in that, described via dielectric layer and trench dielectric layer adopt the chemical vapor deposition Si oxide.
6. technology according to claim 5 is characterized in that said chemical vapor deposition Si oxide comprises the silicate glass of pure silicon silicate glass or fluoridize.
7. technology according to claim 1 is characterized in that, said metal barrier is the TaN/Ta metal barrier.
8. technology according to claim 1 is characterized in that, the thickness of described trench dielectric layer >=3 μ m.
9. technology according to claim 1 is characterized in that, hard mask of said via metal and the hard mask of trench metal are TaN, Ta, TiN, the Ti of chemical vapor deposition or physical vapor deposition.
10. technology according to claim 1 is characterized in that the size of said trench barrier is greater than the size of said groove.
11. technology according to claim 1 is characterized in that, during the substep technological operation of said step 5, adopts wet-cleaned to remove the polymer that gathers because of etching behind the etching groove.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2011101236658A CN102412188A (en) | 2011-05-13 | 2011-05-13 | Metal hard mask dual damascene process of super-thick top metal |
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| CN2011101236658A CN102412188A (en) | 2011-05-13 | 2011-05-13 | Metal hard mask dual damascene process of super-thick top metal |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104051324A (en) * | 2013-03-13 | 2014-09-17 | 中芯国际集成电路制造(上海)有限公司 | Forming method of metal interconnection structure |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5916823A (en) * | 1998-10-13 | 1999-06-29 | Worldwide Semiconductor Manufacturing Corporation | Method for making dual damascene contact |
| CN1459844A (en) * | 2002-04-17 | 2003-12-03 | 三星电子株式会社 | Method for forming double Damascus interconnecting by using low-K dielectric material |
| KR20050067829A (en) * | 2003-12-29 | 2005-07-05 | 매그나칩 반도체 유한회사 | Method of forming a inductor in a semiconductor devices |
| CN101017794A (en) * | 2007-03-02 | 2007-08-15 | 上海集成电路研发中心有限公司 | A method for sealing the small hole of the multi-hole low dielectric material in the Damascus structure |
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2011
- 2011-05-13 CN CN2011101236658A patent/CN102412188A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5916823A (en) * | 1998-10-13 | 1999-06-29 | Worldwide Semiconductor Manufacturing Corporation | Method for making dual damascene contact |
| CN1459844A (en) * | 2002-04-17 | 2003-12-03 | 三星电子株式会社 | Method for forming double Damascus interconnecting by using low-K dielectric material |
| KR20050067829A (en) * | 2003-12-29 | 2005-07-05 | 매그나칩 반도체 유한회사 | Method of forming a inductor in a semiconductor devices |
| CN101017794A (en) * | 2007-03-02 | 2007-08-15 | 上海集成电路研发中心有限公司 | A method for sealing the small hole of the multi-hole low dielectric material in the Damascus structure |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104051324A (en) * | 2013-03-13 | 2014-09-17 | 中芯国际集成电路制造(上海)有限公司 | Forming method of metal interconnection structure |
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Application publication date: 20120411 |