JP2005311350A - Method of producing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve ashing resistance of an intermediate layer in the three-layer resist process. <P>SOLUTION: The intermediate layer 222 in three resist layers 225 are formed by the chemical vapor deposition process using Si(OR<SB>1</SB>)(OR<SB>2</SB>)(OR<SB>3</SB>)(OR<SB>4</SB>) at the temperature of 300°C or lower, wherein R<SB>1</SB>, R<SB>2</SB>R<SB>3</SB>, and R<SB>4</SB>individually denote carbon-containing radicals or hydrogen atoms. Here, the case is not included that all of R<SB>1</SB>, R<SB>2</SB>, R<SB>3</SB>and R<SB>4</SB>are hydrogen atoms. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a semiconductor device in which wiring grooves and via holes are formed using a three-layer resist method.

  As miniaturization of semiconductor devices progresses, microfabrication has become necessary also in an etching technique using a photoresist. The three-layer resist method is known as a method capable of performing fine processing without being affected by the step of the substrate. In the three-layer resist method, first, a thick lower resist layer is applied on a substrate to be finely processed. Next, SOG (Spin On Glass) is applied on the lower resist layer to form an intermediate film. An upper resist layer is applied thereon, and the upper resist is exposed and developed to form a processing mask (Patent Document 1).

When misalignment or the like occurs, a process is performed in which only the upper resist layer is peeled and removed by O ₂ ashing or an organic solvent, and the upper resist layer is formed again, exposed and developed. However, when the upper resist layer is removed using an organic solvent, the SOG of the intermediate film is also peeled off. Patent Document 1 discloses a technique of using a low-concentration resolution resist for the upper layer resist so that only the upper layer resist layer can be easily peeled off.

Further, in Patent Document 2, an intermediate film pattern formed by a plasma CVD method using high-density plasma is used as an intermediate film of a three-layer resist in order to improve a dimensional conversion difference and a pattern shape when etching a lower resist layer. A technique using a SiO ₂ film prepared by the method is disclosed.
JP-A-5-341533 JP-A-7-183194

By the way, when the upper resist layer is peeled and removed by O ₂ ashing, there is a phenomenon that C and O in the SOG easily form a bond at the time of ashing, and the Si—CH ₃ bond is easily broken. Therefore, there is a problem that dangling bonds are formed in the Si bonds at the portion where the Si—CH ₃ bonds are broken, and the moisture absorption rate is increased. As described above, the film properties change due to moisture absorption of the underlying SOG, whereby the exposure conditions of the upper resist change and pattern defects occur. For these reasons, in the three-layer resist technology using SOG, it is difficult to peel off and remove only the upper resist layer and to form it again, resulting in inferior mass productivity.

As will be described later in Examples, as shown in Patent Document 2, the ashing resistance was not sufficient in the SiO ₂ film formed using SiH ₄ and N ₂ O gas.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a technique for increasing the ashing resistance of an intermediate film when forming a wiring groove or a via hole using a three-layer resist method. Objective.

  According to the present invention, a step of forming an insulating film on a film to be etched formed on a semiconductor substrate, and a compound represented by the following general formula (1) at a temperature of 300 ° C. or less on the insulating film: A step of forming an intermediate film by the chemical vapor deposition method used, a step of forming a resist film on the intermediate film, a step of etching the film to be etched using the insulating film, the intermediate film, and the resist film, A method for manufacturing a semiconductor device is provided.

Here, R ₁ , R ₂ , R ₃ and R ₄ each independently represent a carbon-containing group or a hydrogen atom. However, it does not include when all of R _{1 to} R ₄ are hydrogen atoms. Moreover, R < ₁ > -R < ₄ > can respectively independently represent a C1-C6 alkyl group or a hydrogen atom.

Thereby, an intermediate film composed of a SiO ₂ film can be formed. By forming the intermediate film using such a material, the ashing resistance of the intermediate film can be increased. Thereby, after patterning the resist film, misalignment occurs in the resist film, and even when the resist film has to be removed by ashing, the deterioration of the intermediate film can be prevented.

  Although the minimum of the temperature at the time of forming an intermediate film by a chemical vapor deposition method is not specifically limited, For example, it can be 100 degreeC or more. Thereby, the water | moisture content, organic substance, etc. which were adhering to the board | substrate originally can be removed, and adhesiveness with a lower layer can be made favorable.

In Si (OR ₁ ) (OR ₂ ) (OR ₃ ) (OR ₄ ) in the step of forming the intermediate film of the method for manufacturing a semiconductor device of the present invention, R ₁ , R ₂ , R ₃ , and R ₄ are independent of each other. A carbon-containing group. Further, TEOS (tetraethyl orthosilicate) can be used in the step of forming the intermediate film in the method for manufacturing a semiconductor device of the present invention.

  By forming the intermediate film using such a material, the ashing resistance of the intermediate film can be increased. In addition, the hygroscopicity of the intermediate film can be reduced.

  In the step of forming the intermediate film in the method for manufacturing a semiconductor device of the present invention, an oxidizing gas can be further used.

Here, as the oxidizing gas, O ₂ gas, O ₃ gas, or the like can be used. As the oxidizing gas, it is preferable to use a gas not containing nitrogen. Thereby, when the resist film is formed of a chemically amplified resist on the intermediate film, it is possible to prevent the resist poisoning due to the nitrogen source from occurring.

  In the method for manufacturing a semiconductor device of the present invention, the resist film can be a chemically amplified resist. Thereby, the resist film can be finely processed. Further, as described above, since the intermediate film is formed of a gas not containing a nitrogen source, even when a chemically amplified resist is used as the resist film, resist poisoning due to the nitrogen source does not occur and the resolution is good. Can be. Although not particularly limited, the insulating film can also be formed of a chemically amplified resist.

  The method for manufacturing a semiconductor device of the present invention can further include a step of forming a first antireflection film on the insulating film before the step of forming the intermediate film. In the step of forming the intermediate film An intermediate film can be formed on the first antireflection film.

  In this way, by forming an antireflection film under the intermediate film, even if the resist film is ashed and reconstructed, the intermediate film functions as a protective film, and it is necessary to re-form the antireflection film. There is no. The first antireflection film can be made of, for example, SiON.

  The method for manufacturing a semiconductor device of the present invention may further include a step of forming a second antireflection film on the intermediate film before the step of forming the resist film. In the step of forming the resist film A resist film can be formed on the second antireflection film.

  Thus, by forming a desired second antireflection film between the intermediate film and the resist film, the wettability of the resist film can be improved. The second antireflection film can be composed of, for example, a novolac resin to which an antireflection component is added.

  According to the present invention, it is possible to improve the ashing resistance of an intermediate film when forming a wiring groove or a via hole of a semiconductor device using a three-layer resist method.

(First embodiment)
1 to 4 are process cross-sectional views illustrating the manufacturing procedure of the semiconductor device 200 according to the present embodiment.
In the present embodiment, an example in which the present invention is applied when a multilayer wiring structure is formed by a dual damascene process will be described. Here, a method of forming wirings and vias by the so-called via first method will be described as an example.

  A procedure for forming a multilayer wiring structure in the state shown in FIG. First, an etching stopper film 202, a first inter-wiring insulating film 203, and a first protective film 204 are sequentially stacked on a base insulating film 201 formed on a semiconductor substrate (not shown). Etching stopper film 202 is, for example, a SiC or SiCN film.

As the first inter-wiring insulating film 203, polyhydrogensiloxane such as HSQ (hydrogen silsesquioxane), MSQ (methyl silsesquioxane), or MHSQ (methylated hydrogen silsesquioxane), polyaryl, etc. Aromatic-containing organic materials such as ether (PAE), divinylsiloxane-bis-benzocyclobutene (BCB), or Silk (registered trademark), SOG, FOX (flowable oxide), Cytop, or BCB (Bencyclic cycloneene), SiOC, etc. The low dielectric constant material can be used. Among these, it is preferable to use a material having a SiO structure such as polyhydrogensiloxane or SiOC. Further, these porous films can be used as the first inter-wiring insulating film 203. As the first inter-wiring insulating film 203, for example, a porous SiOC film or a porous polysiloxane film having a relative dielectric constant of 2.7 or less can be used. The first protective film 204 is composed of, for example, a SiO ₂ film. The film to be etched in this embodiment can be an insulating film such as an inter-wiring insulating film, a protective film, an etching stopper film, or an interlayer insulating film.

  In this state, a wiring groove is formed in the first inter-wiring insulating film 203 and the first protective film 204, and the wiring groove is filled with the barrier film 208 and the wiring metal film 209. The barrier film 208 is formed in the wiring trench by a sputtering method. The barrier film 208 is composed of, for example, Ta, TaN, Ti, TiN, or a laminated structure thereof. The wiring metal film 209 is formed on the barrier film 208 by, for example, electrolytic plating. Wiring metal film 209 is made of, for example, a copper film.

  Thereafter, the barrier film 208 and the wiring metal film 209 formed outside the wiring trench are removed by CMP (Chemical Mechanical Polishing) to form the lower layer wiring 255.

  Subsequently, an etching stopper film 211, an interlayer insulating film 212, an etching stopper film 213, a second inter-wiring insulating film 216, and a second protective film 217 are sequentially stacked on the lower layer wiring 255. At this time, after the formation of the interlayer insulating film 212, in order to reduce unevenness generated in the CMP process when the lower layer wiring 255 is formed, the interlayer insulating film 212 is preferably processed by CMP to perform surface planarization. Thereby, even when a multilayer wiring structure is formed, each layer can be kept flat, and a semiconductor device can be manufactured accurately and stably. The etching stopper film 211 and the etching stopper film 213 can be made of the same material as the etching stopper film 202. The interlayer insulating film 212 and the second inter-wiring insulating film 216 can be made of the same material as the first inter-wiring insulating film 203. The second protective film 217 can be made of the same material as the first protective film 204.

  Next, a first resist film 220 is formed on the second protective film 217. As a result, a multilayer wiring structure having the structure shown in FIG.

  The first resist film 220 (with a film thickness of about 300 to 500 nm) can be made of the same material as the lower resist layer normally used in the three-layer resist method, and is, for example, a novolak-type positive resist. The first resist film 220 can also be composed of a polyimide resin or a thermosetting phenol.

Subsequently, an intermediate film 222 (film thickness of about 50 to 100 nm) is formed on the first resist film 220 (FIG. 1B). In the present embodiment, for example, the intermediate film 222 is formed by a CVD method using TEOS as a film forming gas under a reduced pressure of about 3 Torr and a temperature of 300 ° C. or lower, more preferably 200 ° C. or lower. The intermediate film 222 can be formed at a temperature of 100 ° C. or higher. The intermediate film 222 can be formed by a two-frequency plasma CVD method. By using such a method, the film stress of the intermediate film 222 can be controlled. In this case, one frequency can be 1 MHz or less. By setting such conditions, the intermediate film 222 can have a compressive stress even when the intermediate film 222 is formed at a relatively low temperature of 300 ° C. or lower, more preferably 200 ° C. or lower. By making the intermediate film 222 have a compressive stress, the hygroscopicity of the intermediate film 222 can be reduced. For example, the intermediate film 222 can be formed by a two-frequency plasma CVD method in which the frequency of the high frequency component (High Frequency) is 13.56 MHz and the frequency of the low frequency component (Low Frequency) is about 500 KHz. Here, as the film forming gas, an oxidizing gas such as O ₂ can be used in addition to TEOS.

  Thereafter, a second resist film 224 (film thickness of about 150 to 300 nm) is formed on the intermediate film 222 (FIG. 1C). The second resist film 224 can be made of the same material as the upper resist layer normally used in the three-layer resist method, and is, for example, a positive chemically amplified resist. Thereby, a three-layer resist film 225 is formed.

Subsequently, via holes are formed in the interlayer insulating film 212, the second inter-wiring insulating film 216, and the second protective film 217 using the three-layer resist film 225 formed as described above. Here, the via hole diameter can be about 0.1 μm. First, the second resist film 224 is patterned into a predetermined shape and opened (FIG. 2D). At this time, if misalignment or the like occurs, the second resist film 224 can be removed by O ₂ ashing (about 250 ° C.). In the present embodiment, since the intermediate film 222 is made of a material having high ashing resistance, the influence on the intermediate film 222 can be reduced even if ashing is performed. Therefore, after the second resist film 224 is removed, the second resist film 224 can be patterned again by forming the second resist film 224 on the intermediate film 222 again.

  Thereafter, using the second resist film 224 as a mask, the intermediate layer 222 is patterned into a predetermined shape and opened (FIG. 2E). Next, using the second resist film 224 and the intermediate film 222 as a mask, the first resist film 220 is patterned into a predetermined shape and opened (FIG. 2F).

  Subsequently, with the three-layer resist film 225 patterned in a predetermined shape as described above as a mask, an interlayer insulating film 212, an etching stopper film 213, a second inter-wiring insulating film 216, by a known lithography technique and etching technique, A via hole 226 is formed in the second protective film 217 (FIG. 2G). Here, the etching stopper film 211 has a function of stopping etching when the via hole 226 is formed. Although the second resist film 224 and the intermediate film 222 are illustrated here, the second resist film 224 may be formed of a material that is removed in the process of opening the intermediate film 222. Further, the intermediate film 222 can be made of a material that is removed in the process of opening the first resist film 220. Thereby, the three-layer resist film 225 can be easily removed in a later step.

  Thereafter, the three-layer resist film 225 is removed, and a three-layer resist film 235 including the third resist film 230, the intermediate film 232, and the fourth resist film 234 is formed in the same manner as the three-layer resist film 225 (FIG. 3). (H)).

  Subsequently, a wiring groove is formed in the second inter-wiring insulating film 216 and the second protective film 217 using the three-layer resist film 235. First, the fourth resist film 234 is patterned and opened in a predetermined shape. Subsequently, using the fourth resist film 234 as a mask, the intermediate film 232 is patterned into a predetermined shape and opened. Next, using the fourth resist film 234 and the intermediate film 232 as a mask, the third resist film 230 is patterned and opened in a predetermined shape (FIG. 3I).

By the way, when wiring and vias are formed by the via first method as described above, there is a problem that resist resolution failure (resist poisoning) is likely to occur when a chemically amplified resist is used. Such a problem is more likely to occur when a low dielectric constant film is used as an interlayer insulating film. A chemically amplified resist is a resist that contains an acid generator that generates an acid upon irradiation with light and a compound that reacts with the acid. By using an acid-catalyzed reaction, the alkali dissolution characteristics of the compound are changed to change the resist pattern. Is formed. In such a chemically amplified resist, if basic impurities such as amine are present in the lower layer of the resist layer, the acid catalyst generated by irradiating the chemically amplified resist with light is neutralized by basic impurities such as amine. It is considered that the alkali dissolution characteristics of the compound in the chemically amplified resist do not change, and the poor resolution occurs because the compound does not dissolve even when an alkaline aqueous solution is applied. Therefore, it is preferable to provide a layer that does not contain a nitrogen source under the chemically amplified resist. In the present embodiment, the second resist film 224 and the intermediate film 222 and the intermediate film 232 below the fourth resist film 234 are formed without using a gas containing nitrogen such as N ₂ O, so the second resist film There is also an effect that the resolution of the 224 and the fourth resist film 234 can be improved.

  Subsequently, the wiring groove 236 is formed in the second inter-wiring insulating film 216 and the second protective film 217 by a known lithography technique and etching technique using the three-layer resist film 235 patterned in a predetermined shape as described above as a mask. It forms (FIG.3 (j)). As a result, a via hole 226 and a wiring groove 236 are continuously formed on the lower layer wiring 255. In this process, the fourth resist film 234 and the intermediate film 232 are also removed.

  Thereafter, the three-layer resist film 235 used for forming the wiring groove 236 is completely removed using a stripping solution, and the etching stopper film 211 at the bottom of the via hole 226 is removed by etching (FIG. 4K). Subsequently, a barrier film 240 is formed in the via hole 226 and the wiring groove 236 by sputtering. Next, a wiring metal film 242 is formed on the barrier film 240 by, for example, electrolytic plating so as to fill the via hole 226 and the wiring groove 236. Next, the barrier film 240 and the wiring metal film 242 formed outside the wiring groove 236 are removed by CMP. Thereby, the semiconductor device 200 is formed.

  A semiconductor having a multilayer wiring structure having a desired number of layers by a dual damascene process by repeating the process of forming a wiring as described above and forming a via and a wiring for electrically connecting the wiring on the wiring. The device can be manufactured.

  As described above, according to the manufacturing method of semiconductor device 200 in the present embodiment, the intermediate film 222 in the three-layer resist film 225 and the intermediate film 232 in the three-layer resist film 235 are formed using TEOS as a film forming gas. Since it is formed by the CVD method, ashing resistance can be increased. Thereby, when the second resist film 224, which is the upper layer of the intermediate film 222, is removed by ashing, the influence on the intermediate film 222 can be suppressed.

  In addition, since the intermediate film 222 formed in this way has low hygroscopicity, the stability when the intermediate film 222 is formed and placed can be improved.

  Furthermore, since the intermediate film 222 does not contain a nitrogen source, resist poisoning when a chemically amplified resist film is used as the upper second resist film 224 can be suppressed, and the resolution can be improved.

  For example, in the case where the first inter-wiring insulating film 203, the interlayer insulating film 212, the second inter-wiring insulating film 216 and the like that are to be etched are formed of a porous SiOC film (for example, a relative dielectric constant of 2.7 or less), There was a problem that resist poisoning was likely to occur. This is presumably because the amine-based stripping solution penetrates into the porous SiOC film or a nitrogen source is mixed by plasma treatment, which affects the resist film. However, according to the method for manufacturing a semiconductor device in the present embodiment, resist poisoning is suppressed even when the first inter-wiring insulating film 203, the interlayer insulating film 212, the second inter-wiring insulating film 216, and the like are formed of a porous SiOC film. It was confirmed that This is because the intermediate film 222 does not contain a nitrogen source, and even if there is a nitrogen source in the etching target film in the lower layer, it could prevent the upper layer chemically amplified resist from being affected. it is conceivable that.

(Second embodiment)
5 and 6 are structural views showing the manufacturing process of the semiconductor device 200 in the present embodiment. Here, the detailed structure of the lower layer of the three-layer resist film 235 is omitted, and is simply referred to as an object to be etched.

As shown in FIG. 5, the three-layer resist film 235 may have a configuration in which an antireflection film 244 is provided between the third resist film 230 and the intermediate film 232. Here, the antireflection film 244 can be made of, for example, SiON or SiOC. For example, when the antireflection film 244 is made of SiON, the SiON can be formed by parallel plate plasma CVD at a temperature of 200 ° C. or lower using SiH ₄ and N ₂ O gas. The antireflection film 244 is preferably formed in the same apparatus as that for forming the intermediate film 232. By making the composition in the antireflection film 244 Si-rich, the light attenuation coefficient can be increased. Thereby, it can be made difficult to transmit light. The three-layer resist film 225 can have the same configuration.

  As shown in FIG. 6, the three-layer resist film 235 can have a configuration in which an antireflection film 246 is provided between the intermediate film 232 and the fourth resist film 234. Here, the antireflection film 246 can be made of, for example, a novolac resin to which an antireflection component is added. Thereby, the wettability with the 4th resist film 234 and the layer under it can be made favorable. The three-layer resist film 225 can have the same configuration.

  As described above, by providing the antireflection film in the three-layer resist film 235 or the three-layer resist film 225, resist patterning can be performed with good control.

(Example 1)
The structural changes of the TEOS-SiO ₂ film, SiH ₄ -SiO ₂ film, and SOG film before and after ashing were examined. Each membrane was prepared as follows.

i) TEOS-SiO ₂ film Using a mixed gas of TEOS and O ₂ (flow rate ratio 1:10) as a film forming gas, a film was formed by a two-frequency plasma CVD method at 200 ° C. under a reduced pressure of about 3 Torr. Here, the power is set so that the frequency of the high frequency component (High Frequency, 13.56 MHz) is about 100 W and the frequency of the low frequency component (Low Frequency, about 500 KHz) is about 200 W.

ii) SiH ₄ —SiO ₂ film A mixed gas of SiH ₄ and N ₂ O (flow rate ratio 1:20) was used as a film forming gas, and a film was formed by a CVD method at 200 ° C. under a reduced pressure of about 3 Torr.

iii) SOG film An SOG chemical solution was dropped by a coater and baked at about 200 ° C. by a hot plate to form a film, which was then formed.

The above three types of films were prepared, and the FT-IR change, the change rate of the film thickness, and the change rate of the refractive index of each film before and after ashing when O ₂ ashing was performed at about 250 ° C. were measured.

FIG. 7 is a diagram showing FT-IR changes. As shown in FIG. 7A, in the TEOS-SiO ₂ film, almost no change was observed before ashing (INIT) and after ashing (ASH). Further, in the SiH ₄ —SiO ₂ film, an increase in Si—OH bonds was observed after ashing (ASH) as compared to before ashing (INIT). In the SOG film, the disappearance of the CH ₃ group was observed due to ashing, and an increase in H—OH was observed.

FIG. 8 is a diagram showing changes in film thickness. Here, on the basis of the film thickness before ashing, in the TEOS-SiO ₂ film, the film thickness hardly changed even after ashing was performed three times. On the other hand, with the SOG film, the film thickness contracted significantly only by performing ashing once. In the SiH ₄ —SiO ₂ film, the film thickness did not change as significantly as the SOG film, but compared with the TEOS—SiO ₂ film, the film thickness changed. This is probably because the membrane is fragile.

FIG. 9 is a diagram showing a change in refractive index. Again, with the refractive index before ashing as a reference, the TEOS-SiO ₂ film hardly changed the refractive index even after ashing was performed three times. On the other hand, in the SiH ₄ —SiO ₂ film, the refractive index changed significantly only by performing ashing once. In the SOG film, the film thickness did not change as significantly as the SiH ₄ —SiO ₂ film, but the refractive index changed compared to the TEOS—SiO ₂ film. This is presumably because the film quality was changed by breaking the Si—CH ₃ bond.

As described above, in the TEOS-SiO ₂ film, structural change hardly occurred before and after ashing, and it was shown that the ashing resistance was high.

(Example 2)
The TEOS-SiO ₂ film and SiH ₄ -SiO ₂ film formed in the same manner as in Example 1 were stored for 1 month in a clean room atmosphere (23 ° C.), and then the FT-IR of these films was measured. FIG. 10A shows the FT-IR of the TEOS-SiO ₂ film, and FIG. 10B shows the FT-IR of the SiH ₄ -SiO ₂ film.

As shown in FIG. 10B, it can be seen that the SiH ₄ —SiO ₂ film has a H—OH bond and absorbs moisture as compared to after the film formation. On the other hand, in the TEOS-SiO ₂ film, no peak of H—OH— bond was observed even after 1 month, and it was found that the film did not absorb moisture. In the TEOS-SiO ₂ film, since Si is bonded to four O atoms in the raw material TEOS, the resulting low-temperature CVD film has a high proportion of Si—O bonds and has a stable structure. It is guessed. In order to form a film at a low temperature, Si—H bonds may exist, but the ratio is small and the film is considered to be stable. On the other hand, in the SiH ₄ —SiO ₂ film, the abundance of Si—H bonds is large, so that it is presumed that the film is unstable.

(Example 3)
A TEOS-SiO ₂ film was formed in the same manner as in Example 1, and the film stress was measured at room temperature. As a result, the compressive stress was about 50 MPa.

In this embodiment, when a TEOS-SiO ₂ film is formed, the film is formed by a two-frequency plasma CVD method, and the frequency of the low frequency component (Low Frequency) is set to 1 MHz or less, so that the ion bombardment effect is obtained. It is thought that the film stress could be controlled. As a result, it is considered that the hygroscopicity could be reduced.

  The present invention has been described based on the embodiments and examples. It is to be understood by those skilled in the art that the embodiments and examples are merely examples, and various modifications are possible and that such modifications are within the scope of the present invention.

  For example, in the embodiment, the example in which the wiring and the via are formed by the so-called via first method of the dual damascene process has been shown. Can be applied to the process.

It is process sectional drawing which shows the manufacturing procedure of the semiconductor device in embodiment of this invention. It is process sectional drawing which shows the manufacturing procedure of the semiconductor device in embodiment of this invention. It is process sectional drawing which shows the manufacturing procedure of the semiconductor device in embodiment of this invention. It is process sectional drawing which shows the manufacturing procedure of the semiconductor device in embodiment of this invention. It is a structural diagram showing a manufacturing process of a semiconductor device in an embodiment of the present invention. It is a structural diagram showing a manufacturing process of a semiconductor device in an embodiment of the present invention. It is a figure which shows FT-IR change. It is a figure which shows the change of a film thickness. It is a figure which shows the change of a refractive index. It is a figure which shows FT-IR.

Explanation of symbols

200 Semiconductor Device 201 Base Insulating Film 202 Etching Stopper Film 203 First Inter-wiring Insulating Film 204 First Protection Film 208 Barrier Film 209 Wiring Metal Film 211 Etching Stopper Film 212 Interlayer Insulating Film 213 Etching Stopper Film 216 Second Inter-wiring Insulating Film 217 Second protective film 220 First resist film 222 Intermediate film 224 Second resist film 225 Three-layer resist film 226 Via hole 230 Third resist film 232 Intermediate film 234 Fourth resist film 235 Three-layer resist film 236 Wiring groove 240 Barrier film 242 Wiring Metal film

Claims (11)

Forming an insulating film on a film to be etched formed on a semiconductor substrate;
Forming an intermediate film on the insulating film by a chemical vapor deposition method using a compound represented by the following general formula (1) at a temperature of 300 ° C. or less;
Forming a resist film on the intermediate film;
Etching the film to be etched using the insulating film, the intermediate film, and the resist film;
A method for manufacturing a semiconductor device, comprising:

(R ₁ , R ₂ , R ₃ and R ₄ each independently represent a carbon-containing group or a hydrogen atom. However, it is not included when all of R _{1 to} R ₄ are hydrogen atoms.) In the manufacturing method of the semiconductor device according to claim 1,
In the compound in the step of forming the intermediate film, R ₁ , R ₂ , R ₃ , and R ₄ each independently represent a carbon-containing group. In the manufacturing method of the semiconductor device according to claim 1 or 2,
The method for manufacturing a semiconductor device, wherein the carbon-containing group is an alkyl group having 1 to 6 carbon atoms. In the manufacturing method of the semiconductor device according to claim 1,
A method of manufacturing a semiconductor device, wherein TEOS (tetraethyl orthosilicate) is used in the step of forming the intermediate film. In the manufacturing method of the semiconductor device according to claim 1,
A method for manufacturing a semiconductor device, wherein an oxidizing gas is further used in the step of forming the intermediate film. In the manufacturing method of the semiconductor device according to claim 1,
The method of manufacturing a semiconductor device, wherein the resist film is a chemically amplified resist. In the manufacturing method of the semiconductor device according to claim 1,
Before the step of forming the intermediate film, further comprising a step of forming a first antireflection film on the insulating film;
A method of manufacturing a semiconductor device, wherein in the step of forming the intermediate film, the intermediate film is formed on the first antireflection film. In the manufacturing method of the semiconductor device in any one of Claims 1 thru | or 7,
Before the step of forming the resist film, further comprising a step of forming a second antireflection film on the intermediate film;
A method of manufacturing a semiconductor device, wherein in the step of forming the resist film, the resist film is formed on the second antireflection film. In the manufacturing method of the semiconductor device according to claim 1,
A method of manufacturing a semiconductor device, wherein the intermediate film has a compressive stress. In the manufacturing method of the semiconductor device in any one of Claims 1 thru | or 9,
In the step of forming the intermediate film, the intermediate film is formed by a two-frequency plasma CVD method in which one frequency is 1 MHz or less. In the manufacturing method of the semiconductor device according to claim 1,
The method for manufacturing a semiconductor device, wherein the film to be etched includes a porous film having a relative dielectric constant of 2.7 or less.

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