JP2005109343A - Manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enable the formation of a multilayer wiring of low capacitance between wirings and wiring layers. <P>SOLUTION: A multilayer wiring structure is formed on a substrate 2, which comprises an interlayer insulating film where fluorinated arylene films 6, 16, and 26 which do not contain vacancy as an organic film and SiC films 8, 14, 18, 24, and 28 as an inorganic film are laminated, and wirings 12 and 32 formed in the interlayer insulating film. A through hole 36 penetrating the fluorinated arylene films 6, 16, and 26 and the SiC films 8, 14, 18, 24, and 28 is formed around the wirings 12 and 32. The entire surface of the substrate 2 is irradiated with an electron beam to remove the fluorinated arylene films 6, 16, and 26. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a hollow multilayer wiring.

As semiconductor devices are miniaturized, wiring resistance increases and parasitic capacitance increases between wirings and between wiring layers. As an improvement measure, a method has been proposed in which copper is used as a wiring material and a low dielectric constant film is used as an interlayer insulating film to reduce wiring resistance and parasitic capacitance between wirings and wiring layers.
In recent years, as a low dielectric constant film, for example, an inorganic film such as a SiOC film in which a methyl group is introduced into a SiO ₂ film or an organic film such as a polyallyl ether derivative has been developed. The relative dielectric constant of these films is about 2.6 to 2.9.
In order to further reduce the dielectric constant required for next-generation semiconductor devices, by introducing holes into the thin film, the film density is reduced, and a film having a relative dielectric constant of 2.0 to 2.4 is realized. Development is underway (see, for example, Patent Document 1).

Japanese Patent Laid-Open No. 9-298241

However, the thin film into which such pores are introduced has a problem in that the mechanical strength is lowered, so that the thin film easily breaks during the manufacturing process.
Further, since gas and chemicals are adsorbed in the pores, there is a problem that the film characteristics are deteriorated, and a post-treatment needs to be performed as a countermeasure against the deterioration, resulting in an increase in manufacturing cost. For this reason, it has been difficult to apply a low dielectric constant film having pores to the manufacture of a semiconductor device.

  The present invention has been made to solve the above-described conventional problems, and an object thereof is to form a multilayer wiring having a low capacitance between wirings and between wiring layers.

A method of manufacturing a semiconductor device according to the present invention includes an interlayer insulating film formed by laminating an organic film not containing holes and an inorganic film on a substrate, and a wiring layer formed in the interlayer insulating film. Forming a multilayer wiring structure;
Forming a through-hole penetrating the organic film and the inorganic film;
After forming the through hole, irradiating the entire surface of the substrate with an electron beam to remove the organic film;
It is characterized by including.

  In the method for manufacturing a semiconductor device according to the present invention, it is preferable that the substrate is heated to a temperature of 200 ° C. or higher and irradiated with the electron beam.

  In the method for manufacturing a semiconductor device according to the present invention, it is preferable that a plurality of the through holes are formed around the wiring layer.

  In the method for manufacturing a semiconductor device according to the present invention, it is preferable that the organic film is a fluorinated arylene film.

In the method for manufacturing a semiconductor device according to the present invention, it is preferable that the inorganic film is a SiO ₂ film, a SiN film, a SiON film, a SiC film, a SiOC film, or a SiCN film.

  In the method of manufacturing a semiconductor device according to the present invention, it is preferable that the method further includes a step of closing the through hole after removing the organic film.

  In the present invention, as described above, the multi-layer wiring structure is formed using the interlayer insulating film having the organic film that does not include the vacancies, and then the capacitance between the wirings and between the wiring layers is reduced by removing the organic film. A multilayer wiring structure can be formed.

1 to 2 are process cross-sectional views for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention.
In the present embodiment, only a method for forming a multilayer wiring structure, which is a main process, will be described, and a description of a method for forming a lower layer structure such as a semiconductor element or wiring below the multilayer wiring structure will be omitted.

First, as shown in FIG. 1A, an SiC film as the inorganic film 4 is formed on the substrate 2 by a plasma CVD method to a film thickness of, for example, 100 nm. Next, a fluorinated arylene film as an organic film 6 that does not contain vacancies is formed on the SiC film 4 by a CVD method to a thickness of, for example, 200 nm. Then, an SiC film as a hard mask 8 is formed on the fluorinated arylene film 6 by a plasma CVD method with a film thickness of, for example, 100 nm.
In addition to the SiC film, for example, a SiO ₂ film, a SiN film, a SiON film, a SiOC film, or a SiCN film can be used as the inorganic film 4 (the same applies to an inorganic film described later).
Moreover, as a specific example of the fluorinated arylene film 6, for example, a fluorinated polyxylylene film can be exemplified. A fluorinated polyxylylene film is formed by supplying a precursor (radical) obtained by activating a source gas of a xylylene compound to which fluorine is bonded to the substrate surface and polymerizing the precursor. .

  Next, as shown in FIG. 1B, the SiC film 8 is patterned by lithography and dry etching. Then, the fluorinated arylene film 6 is dry-etched using the patterned SiC film 8 as a mask. As a result, a wiring groove 10 is formed in the SiC film 8 and the fluorinated arylene film 6.

Subsequently, as shown in FIG. 1C, after a barrier metal film is formed on the entire surface of the substrate 2 including the inner surface of the wiring groove 10, a copper film as a metal film is formed thereon. Then, using the SiC film 8 as a stopper film, unnecessary copper film and barrier metal film are removed by CMP. As a result, the metal wiring 12 composed of the barrier metal film and the copper film is embedded in the wiring groove 10.
As the barrier metal film, for example, a Ta film, a TaN film, a Ti film, a TiN film, or a laminated film thereof can be used. In addition to the copper film, a tungsten film, an aluminum film, or the like can be used as the metal film (the same applies to the via contact 22 and the metal wiring 32 described later).

  Next, as shown in FIG. 1D, an SiC film as an inorganic film 14 is formed on the SiC film 8 and the metal wiring 12 by a plasma CVD method to a film thickness of, for example, 100 nm. Then, a fluorinated arylene film as the organic film 16 is formed on the SiC film 14 with a film thickness of, for example, 200 nm by the CVD method. Further, an SiC film as a hard mask 18 is formed on the fluorinated arylene film 16 by a plasma CVD method to a thickness of 100 nm, for example.

  Next, as shown in FIG. 1E, the SiC film 18 is patterned by a lithography technique and dry etching. Then, the fluorinated arylene film 16 is dry-etched using the patterned SiC film 18 as a mask. Thus, a via hole 20 reaching the upper surface of the metal wiring 12 is formed in the SiC film 18 and the fluorinated arylene film 6.

  Subsequently, as shown in FIG. 2A, after a barrier metal film is formed on the entire surface of the substrate including the inner surface of the via hole 20, a copper film as a metal film is formed thereon. Then, using the SiC film 18 as a stopper film, unnecessary copper film and barrier metal film are removed by CMP. As a result, a via contact 22 made of a barrier metal film and a copper film is formed in the via hole 20 and connected to the underlying metal wiring 12.

  Next, as shown in FIG. 2B, an SiC film as an inorganic film 24 is formed on the SiC film 18 and the via contact 22 by a plasma CVD method to a film thickness of, for example, 100 nm. Then, a fluorinated arylene film as the organic film 26 is formed on the SiC film 24 with a film thickness of, for example, 200 nm by the CVD method. Further, an SiC film as a hard mask 28 is formed on the fluorinated arylene film 26 with a film thickness of, for example, 100 nm by a plasma CVD method.

  Next, as shown in FIG. 2C, the SiC film 28 is patterned by a lithography technique and dry etching. Then, the fluorinated arylene film 26 is dry-etched using the patterned SiC film 28 as a mask. As a result, a wiring groove 30 reaching the upper surface of the via contact 22 is formed in the SiC film 28 and the fluorinated arylene film 26.

  Subsequently, as shown in FIG. 2D, after a barrier metal film is formed on the entire surface of the substrate including the inner surface of the wiring groove 30, a copper film as a metal film is formed thereon. Then, using the SiC film 28 as a stopper film, unnecessary copper film and barrier metal film are removed by CMP. As a result, the upper metal wiring 32 made of the barrier metal film and the copper film is formed in the wiring groove 30 and connected to the via contact 22.

  Next, as shown in FIG. 2E, an SiC film as a hard mask 34 is formed on the SiC film 28 and the metal wiring 32 by a plasma CVD method to a film thickness of, for example, 100 nm.

Then, as shown in FIG. 2F, the SiC film 34 is patterned by a lithography technique and dry etching. Then, using this patterned SiC film 34 as a mask, the SiC film 28 around the wiring layers 12, 22, 32, the fluorinated arylene film 26, the SiC films 24, 18, the fluorinated arylene film 16, the SiC films 14, 8, The fluorinated arylene film 6 is sequentially dry etched. Thus, a through hole 36 for removing the organic film reaching the surface of the SiC film 4 from the surface of the SiC film 28 is formed.
In addition, what is necessary is just to set the opening density and diameter of the through-hole 36 suitably according to a wiring pattern. If the opening density of the through holes 36 is low, the SiC film or the metal wiring may be deformed by a gas generated when the fluorinated arylene film is decomposed (described later). For example, when a 0.16 μm L & S pattern is formed as the metal wirings 12 and 32 in the 500 μm ² region, through holes having a diameter of 0.5 μm are formed outside the L & S pattern at intervals of 20 μm. Good.

Next, the substrate 2 subjected to the above processing is transferred into an electron beam irradiation apparatus (not shown). In the chamber of this electron beam irradiation apparatus, the substrate 2 is heated to 400 ° C., and an electron irradiation unit in which a plurality of electron beam irradiation tubes (Min-EB manufactured by USHIO INC.) Are installed is used. Pressure: 100 mTorr The entire surface of the substrate is irradiated with an electron beam under the conditions of acceleration voltage: 60 kV, irradiation rate: 5 μC / cm ² · sec, and irradiation time: 10 min. As shown in FIG. 2 (g), the fluorinated arylene films 26, 16 are decomposed by electron beam irradiation (indicated by arrows in the figure) and exhausted as a gas, so that the fluorinated arylene films 26, 16, 6 are exhausted. Is removed.
Further, the conditions such as the irradiation rate and the irradiation time may be appropriately set according to the thickness of the fluorinated arylene film to be removed and the hole density of the through holes.

FIG. 3 is a diagram showing the relationship between the amount of organic film removed by electron beam irradiation and the substrate temperature in the present embodiment. Specifically, FIG. 3 is a diagram showing the relationship between the removal rate of the fluorinated arylene film and the substrate temperature when the electron beam is irradiated under the above conditions except for the irradiation time.
As shown in FIG. 3, the film removal rate increases as the substrate temperature increases. Accordingly, the substrate temperature during electron irradiation is preferably 200 ° C. or higher, and more preferably 300 ° C. or higher.

  Thereafter, a through-hole 36 is closed by forming a silicon nitride film (SiN film) used as a passivation film over the entire surface of the substrate by plasma CVD. Instead of forming the SiN film, the through hole 36 may be closed by packaging in a later process.

As described above, in the present embodiment, a multilayer wiring structure including the interlayer insulating film mainly including the fluorinated arylene films 6, 16, and 26 including no holes and the multilayer wirings 12 and 32 is formed. Thereafter, the fluorinated arylene films 6, 16, and 26 were selectively removed by irradiation with an electron beam. Thereby, it is possible to form a hollow structure multilayer wiring having a low capacitance between wirings and between wiring layers.
In this embodiment, since the low dielectric constant film into which the holes are introduced is not used as the interlayer insulating film, it is possible to prevent the deterioration of the film characteristics of the low dielectric constant film which has occurred conventionally.

In this embodiment, the through-hole 36 reaching the surface of the SiC film 4 is formed and all the fluorinated arylene films 6, 16, 26 are removed, but only the desired fluorinated arylene film is removed. You may do it. That is, the through hole 36 may be formed so as to penetrate the fluorinated arylene film that needs to be removed.
In this embodiment, the multilayer wiring structure before the organic film removal is formed using the single damascene method. However, the multilayer wiring structure may be formed using the dual damascene method.
In this embodiment, the two-layer wiring structure including the two wiring layers 12 and 32 has been described. However, the present invention is not limited to this, and the present invention is also applicable to a multilayer wiring structure of one layer or three or more layers. Can do.

It is process sectional drawing for demonstrating the manufacturing method of the semiconductor device by embodiment of this invention (the 1). It is process sectional drawing for demonstrating the manufacturing method of the semiconductor device by embodiment of this invention (the 2). In embodiment of this invention, it is a figure which shows the relationship between the organic film removal amount by electron beam irradiation, and substrate temperature.

Explanation of symbols

2 Substrate 4, 14, 24 Inorganic film (SiC film)
6, 16, 26 Organic film (fluorinated arylene film)
8, 18, 28, 34 Hard mask (SiC film)
10, 30 Wiring groove 12, 32 Metal wiring 20 Via hole 22 Via contact 36 Through hole

Claims (6)

Forming a multilayer wiring structure having an interlayer insulating film formed by laminating a hole-free organic film and an inorganic film on a substrate, and a wiring layer formed in the interlayer insulating film;
Forming a through-hole penetrating the organic film and the inorganic film;
After forming the through hole, irradiating the entire surface of the substrate with an electron beam to remove the organic film;
A method for manufacturing a semiconductor device, comprising: In the manufacturing method of the semiconductor device according to claim 1,
A method of manufacturing a semiconductor device, wherein the substrate is heated to a temperature of 200 ° C. or higher and irradiated with the electron beam. In the manufacturing method of the semiconductor device according to claim 1 or 2,
A method of manufacturing a semiconductor device, wherein a plurality of the through holes are formed around the wiring layer. In the manufacturing method of the semiconductor device in any one of Claim 1 to 3,
A method of manufacturing a semiconductor device, wherein the organic film is a fluorinated arylene film. In the manufacturing method of the semiconductor device in any one of Claim 1 to 4,
A method of manufacturing a semiconductor device, wherein the inorganic film is a SiO ₂ film, a SiN film, a SiON film, a SiC film, a SiOC film, or a SiCN film. In the manufacturing method of the semiconductor device in any one of Claim 1 to 5,
A method of manufacturing a semiconductor device, further comprising the step of closing the through hole after removing the organic film.

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