JP2010050118A - Semiconductor device, and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of preventing a mechanical strength from getting low, while keeping a capacity between wires of a wiring layer at low level, and to provide a method for manufacturing the semiconductor device. <P>SOLUTION: This semiconductor device and the method for manufacturing the same are provided with: the first wiring layer 6 formed on base layers 1, 2, 3, and a film 4 between the wiring layers formed within a plane same to the first wiring layer 6 and vaporized at a prescribed temperature; a diffusion preventive film 7 formed on the first wiring layer 6 and the film 4 between the wiring layers; an air gap 8 within the plane same to the first wiring layer 6 along the first wiring layer 6. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

  In semiconductor devices, integration and high speed have been pursued, and miniaturization has progressed. Miniaturization is also progressing in the wiring process which is a part of the manufacturing process of the semiconductor device. In the past, high speed could be achieved at the same time by further miniaturization. However, with respect to the operating speed, the specific gravity of the delay caused by the wiring, which was not a problem before, has become a problem. The delay caused by the wiring is proportional to the product of the wiring resistance R and the capacitance C, and is called an RC delay. In order to reduce the wiring resistance R, it is conceivable to introduce Cu having a low specific resistance into the wiring material, and it was gradually introduced from the 130 nm node generation. On the other hand, as a countermeasure for the capacitance C, a low dielectric constant film, a so-called Low-k film, is introduced as a material for an insulating film (hereinafter also referred to as a wiring interlayer film) formed in the same plane as the wiring layer. Has been implemented.

  However, since the specific gravity of the RC delay is increasing with the further miniaturization, the dielectric constant of the wiring interlayer film is being promoted in each generation. This ultimate position is a structure in which a region corresponding to the wiring interlayer film is evacuated or a structure in which gas is sealed in the region. These structures are called an air gap structure, an air bridge structure, an aerial wiring, etc., but in the following, a vacuum region or a gas filled region is referred to as an air gap, and a structure having an air gap is referred to as an air gap structure. I write. By taking such an air gap structure, the capacitance between the wirings of the wiring layer is reduced. Several manufacturing methods have been proposed for the air gap structure.

  As one of them, there is a method of forming an air gap by using a wiring interlayer film as a sacrificial film and evaporating it. For example, a groove is formed in a wiring interlayer film made of a carbon film by a normal damascene method, and after a wiring layer is formed in the groove, a SiN film is formed on the wiring layer and the wiring interlayer film. Thereafter, a method of forming an air gap by evaporating all the wiring interlayer films made of a carbon film by exposing to oxygen plasma treatment is known.

  In the case of a multilayer structure, first, a wiring interlayer film made of the same material as described above is formed on the base layer. Thereafter, vias and trenches are formed in the wiring interlayer film according to the dual damascene formation flow, and metal is embedded. Then, excess metal is removed by, for example, a CMP (Chemical Mechanical Polishing) method, thereby forming the first wiring layer and the via. Thereafter, an insulating film serving as a barrier against the metal is formed on the first wiring layer. Then, as in the above-described process, all of the wiring interlayer film in the same plane as the first wiring layer is vaporized by oxygen plasma treatment. Thereafter, in order to form a second wiring layer above the first wiring layer, an insulating film is formed on the insulating film serving as the above-described barrier according to the flow of a normal damascene method, and then the insulating film is formed on the insulating film. Grooves to be vias and wiring are formed. Finally, the second wiring layer is completed by embedding metal and removing excess metal.

  In Patent Document 1, a material that vaporizes at a high temperature (about 300 ° C.), for example, a chain polymer film is used as a material for the wiring interlayer film. Then, after a wiring layer is formed in a groove provided in the wiring interlayer film by an ordinary damascene method, an insulating film is formed on the wiring layer and the wiring interlayer film. Thereafter, by applying a heat treatment, the entire wiring interlayer film is vaporized to form an air gap. Cu, which is often used as a material for the wiring layer, is stable by heat treatment at about 400 ° C., and an air gap can be formed by appropriately selecting a wiring interlayer film.

JP 2002-110785 A

  However, in the conventional air gap structure, since all the wiring interlayer films used as the sacrificial film are heated and vaporized, there is a problem that the mechanical strength is lowered. In particular, when the distance between the wirings of the wiring layer is large, for example, when the hollow portion exists over 10 μm or more, there is a problem that the mechanical strength is low. In addition, when stress is applied in an assembly or the like, there is no supporting insulating film, so that there is a problem that cracks are generated particularly in a portion that is hollow over a large area.

  The present invention has been made to solve the above-described problems, and a semiconductor device capable of preventing a decrease in mechanical strength while keeping a capacitance between wirings of a wiring layer low, and its manufacture It aims to provide a method.

  The semiconductor device according to the present embodiment includes a wiring layer formed on a base layer and a first insulating film that is formed in the same plane as the wiring layer and vaporizes at a predetermined temperature. A second insulating film formed on the wiring layer and the first insulating film is provided, and an air gap is provided in the plane along the wiring layer.

  According to the semiconductor device of the present invention, since the air gap is provided between the wirings of the wiring layer, the capacitance between the wirings can be reduced. In addition, since the first insulating film is formed in the same plane as the wiring layer and away from the wiring of the wiring layer, it is possible to prevent a decrease in mechanical strength.

<Embodiment 1>
Before describing the semiconductor device according to the present embodiment, the configuration of a conventional semiconductor device will be described. FIG. 7 is a cross-sectional view showing a configuration of a conventional semiconductor device. This semiconductor device includes a substrate contact interlayer film 1, a substrate contact layer 2, an etching stopper film 3, a first wiring layer 6, and diffusion. The protective films 7 and 13, the via interlayer film 9, and the second wiring layer 12 are provided. In the conventional semiconductor device, the air gaps 8 and 14 which are vacuum regions or gas-filled regions are provided in the first and second regions in order to reduce the capacitance between the wirings of the first and second wiring layers 6 and 12. The wiring layers 6 and 12 are provided in the same plane. However, such a semiconductor device has a problem that the mechanical strength is lowered because the air gaps 8 and 14 are provided inside.

  Next, the configuration of the semiconductor device according to the present embodiment that solves this problem will be described using the cross-sectional view of FIG. As shown in FIG. 1, the semiconductor device according to the present embodiment includes a substrate contact interlayer film 1, a substrate contact layer 2, an etching stopper film 3, wiring interlayer films 4 and 10, and a first wiring layer 6. And diffusion preventing films 7 and 13, a via interlayer film 9, and a second wiring layer 12.

  The first wiring layer 6, which is a wiring layer according to the present embodiment, is formed on a base layer composed of the substrate contact interlayer film 1, the substrate contact layer 2, and the etching stopper film 3. Further, the second wiring layer 12 which is the wiring layer according to the present embodiment is formed on the base layer made of the via interlayer film 9. The second wiring layer 12 is also provided in a groove formed in the diffusion prevention film 7 and the via interlayer film 9 and is connected to the first wiring layer 6.

  The wiring interlayer films 4, 10 which are the first insulating films provided in the semiconductor device according to the present embodiment are formed in the same plane as the first and second wiring layers 6, 12, and are vaporized at a predetermined temperature. . The predetermined temperature is about 300 ° C. in the present embodiment. Diffusion prevention films 7 and 13 which are second insulating films included in the semiconductor device according to the present embodiment are formed on first and second wiring layers 6 and 12 and wiring interlayer films 4 and 10. The In the semiconductor device according to the present embodiment, air gaps 8 and 14 are provided in the same plane as the first and second wiring layers 6 and 12 along the first and second wiring layers 6 and 12. It has been. In the present embodiment, only the air gaps 8 and 14 are formed between the wirings having a small distance between the wirings of the first and second wiring layers 6 and 12. On the other hand, in addition to the air gaps 8 and 14, wiring interlayer films 4 and 10 are also formed between the wirings having a large distance between the wirings of the first and second wiring layers 6 and 12.

  In the semiconductor device according to the present embodiment as described above, since the air gaps 8 and 14 are provided between the respective wirings of the first and second wiring layers 6 and 12, the capacitance between the wirings is increased. Can be lowered. Further, in the same plane as the first and second wiring layers 6, 12, wiring interlayer films 4, 10 are formed at locations away from the wirings of the first and second wiring layers 6, 12. Therefore, it is possible to prevent a decrease in mechanical strength.

  In general, the capacitance between the wirings is inversely proportional to the distance between the wirings. Therefore, the capacitance between the wirings having a small distance between the wirings tends to increase. However, in the semiconductor device according to the present embodiment, in the first and second wiring layers 6, 12, the wiring gap films 4, 10 are not formed between the wirings having a short wiring distance, and the air gap 8, Since only 14 is formed, a low dielectric constant is secured. On the other hand, in the first and second wiring layers 6 and 12, in addition to the air gaps 8 and 14, wiring interlayer films 4 and 10 for preventing a decrease in mechanical strength are also formed between the wirings having a large wiring distance. However, there is no problem because the capacitance between the wirings is originally small.

  Next, a method for manufacturing the semiconductor device as described above will be described with reference to FIG. In the present embodiment, the process will be described below on the assumption that the first wiring layer 6 is formed by a single damascene method. First, in the step of forming the configuration of FIG. 2A, a base layer composed of the substrate contact interlayer film 1, the substrate contact layer 2, and the etching stopper film 3 is prepared. As the conductive material of the substrate contact layer 2, tungsten (W) is usually used. As a material of the etching stopper film 3, for example, SiN, SiON, SiCN, or SiCO is used.

  Then, a wiring interlayer film 4 that is vaporized at a predetermined temperature is formed on the above-described base layer. As the wiring interlayer film 4, for example, a chain polymer film that vaporizes at a temperature of about 300 ° C. is used. Subsequently, a cap film 5 is formed on the wiring interlayer film 4 in order to prevent damage due to an ashing method or the like in a later process. For example, a silicon oxide film or a SiON film is used for the cap film 5.

  Next, the process according to FIG. In this step, first, a resist pattern for wiring is formed using a normal photolithography process. Then, using the resist pattern as a mask, the cap film 5 and the wiring interlayer film 4 are processed, and grooves are formed in these films. Thereafter, the resist pattern is removed by an ashing method or a wet method using a chemical solution. Then, the etching stopper film 3 is processed into, for example, a dry etching method, thereby completing a wiring groove.

  Thereafter, the step shown in FIG. In this step, first, a barrier metal layer (for example, Ta, TaN, Ru) serving as a diffusion barrier is formed on the wiring interlayer film 4, and a seed layer serving as a seed in the plating method is formed in the above-described wiring trench. To form. The metal layer and the seed layer are formed by sputtering, for example. Subsequently, a metal that becomes the first wiring layer 6, for example, Cu, is embedded in the wiring groove by plating. Subsequently, the excess Cu and the barrier metal layer are removed by a CMP method.

  In the present embodiment, it is assumed that the cap film 5 is completely removed by the dry etching method in the step according to FIG. 2B and the CMP method in the step according to FIG. Note that since a film having a relatively high dielectric constant is generally used as the cap film 5, the dielectric constant of the entire wiring increases when the cap film 5 remains. Therefore, it is desirable that the cap film 5 is completely removed as in the present embodiment. As described above, in the method for manufacturing the semiconductor device according to the present embodiment, the wiring interlayer film 4 that vaporizes at a temperature of about 300 ° C. and the first wiring layer 6 are in contact with each other on the same surface on the above-described base layer. Form in.

  Then, the process which concerns on FIG.2 (d) is performed. In this step, first, a diffusion prevention film 7 is formed on the wiring interlayer film 4 and the first wiring layer 6. The diffusion prevention film 7 is for preventing the diffusion of the wiring material of the first wiring layer 6, for example, Cu, but is used as an etching stopper in a subsequent process. For the diffusion prevention film 7, for example, a SiN film, a SiCN film, or a SiCO film is used.

  After the step according to FIG. 2D, as shown in FIG. 2E, the first wiring layer 6 is heated to a temperature of about 300 ° C., and the portion of the wiring interlayer film 4 in contact with the first wiring layer 6 By vaporizing the air gap 8, the air gap 8 is formed along the first wiring layer 6. In the present embodiment, the first wiring layer 6 is heated by induction heating. In this way, since only the first wiring layer 6 is heated, heat is transmitted to the wiring interlayer film 4 existing within a predetermined distance from the wiring of the first wiring layer 6, and the wiring interlayer film 4 in that portion is vaporized. . On the other hand, since heat is not transmitted to the wiring interlayer film 4 that is separated from the wiring of the first wiring layer 6 by a predetermined distance, the wiring interlayer film 4 in that portion is not vaporized.

  This predetermined distance is controlled by the time for heating the first wiring layer 6. The larger the predetermined distance, the larger the area where the air gap 8 is formed. Therefore, there is a merit that the capacitance between the wirings of the first wiring layer 6 is reduced, but there is a disadvantage that the mechanical strength is reduced. is there. Therefore, it is desirable to control the heating time so that the predetermined distance becomes an optimum value considering both of them.

  The method for forming the first wiring layer 6 has been described above. Next, the method for forming the second wiring layer 12 will be described. Note that the second wiring layer 12 above the first wiring layer 6 is often formed by, for example, a dual damascene method described later. Therefore, in the present embodiment, the second wiring layer 12 is described as being formed by a via-first dual damascene method using a resist pattern as a mask.

  After the step according to FIG. 2E, the step according to FIG. 2F is performed. In this step, first, a via interlayer film 9 is formed on the diffusion prevention film 7. For example, a silicon oxide film, a SiOF film, a low-k film, a ULK film, or an ELK film is used for the via interlayer film 9. Since the via interlayer film 9 is an insulating film of a via layer, it is desirable to use a film having a low dielectric constant as much as possible. Then, a wiring interlayer film 10 which is vaporized at a predetermined temperature is formed on the via interlayer film 9 which is a base layer. As the wiring interlayer film 10, for example, a chain polymer film that vaporizes at a temperature of about 300 ° C. is used. Subsequently, a cap film 11 is formed on the wiring interlayer film 10 in order to prevent damage due to an ashing method or the like performed in a later process. For the cap film 11, for example, a silicon oxide film or a SiON film is used.

  Next, the process according to FIG. In this step, first, a via resist pattern is formed using a normal photolithography process. Then, using the resist pattern as a mask, the cap film 11, the wiring interlayer film 10 and the via interlayer film 9 are processed, and grooves are formed in these films. For this processing, for example, a dry etching method is used, and the diffusion prevention film 7 is usually used as an etching stopper. After processing, the resist pattern is removed by an ashing method or a wet method using a chemical solution.

  Then, the process which concerns on FIG.3 (b) is performed. In this step, first, a resist pattern for wiring is formed using a normal photolithography process. Then, by using the resist pattern as a mask, the cap film 11 and the wiring interlayer film 10 are processed to complete a wiring groove. After processing, the resist pattern is removed by an ashing method or a wet method using a chemical solution. Then, by processing the diffusion preventing film 7 into, for example, a dry etching method, a via groove is completed.

  Thereafter, as shown in FIG. 3C, a metal to be the second wiring layer 12 is buried in the groove formed by the above-described process according to a normal damascene process. In this step, first, a barrier metal layer (for example, Ta, TaN, Ru) serving as a diffusion barrier is formed on the wiring interlayer film 10, and a seed layer serving as a seed for plating is formed in the groove formed as described above. Form. The metal layer and the seed layer are formed by sputtering, for example. Subsequently, a metal that becomes the second wiring layer 12, for example, Cu, is buried in the wiring groove and the via groove by plating. Subsequently, the excess Cu and the barrier metal layer are removed by a CMP method. In the present embodiment, at the same time, the cap film 11 is completely removed. Thus, the second wiring layer 12 is formed in the above groove.

  Then, the process which concerns on FIG.3 (d) is performed. In this step, first, the diffusion prevention film 13 is formed on the wiring interlayer film 10 and the second wiring layer 12. This diffusion prevention film 13 is for preventing the diffusion of the wiring material of the second wiring layer 12, for example, Cu. For the diffusion preventing film 13, for example, a SiN film, a SiCN film, or a SiCO film is used. After the diffusion prevention film 13 is formed, the second wiring layer 12 is heated to a temperature of about 300 ° C., and the second wiring layer 12 is vaporized at a portion in contact with the second wiring layer 12 of the wiring interlayer film 10. An air gap 14 is formed along the layer 12. In the present embodiment, the second wiring layer 12 is heated by induction heating.

  In the semiconductor device according to the present embodiment as described above, since the air gaps 8 and 14 are provided between the respective wirings of the first and second wiring layers 6 and 12, the capacitance between the wirings is increased. Can be lowered. Further, in the same plane as the first and second wiring layers 6, 12, wiring interlayer films 4, 10 are formed at locations away from the wirings of the first and second wiring layers 6, 12. Therefore, it is possible to prevent a decrease in mechanical strength.

  Further, according to the method of manufacturing a semiconductor device according to the present embodiment as described above, the portions of the wiring interlayer films 4 and 10 that are in contact with the first and second wiring layers 6 and 12 are vaporized. Thereby, the air gaps 8 and 14 can be formed along the first and second wiring layers 6 and 12 in the same plane as the first and second wiring layers 6 and 12.

  In the present embodiment, the configuration for forming the etching stopper film 3 has been described. However, the present invention is not limited to this, and the etching stopper film 3 may be omitted. In this case, the wiring interlayer film 4 is formed directly on the substrate contact interlayer film 1 and the substrate contact layer 2.

  In the present embodiment, the method of forming the second wiring layer 12 by the via-first dual damascene method has been described. However, the present invention is not limited to this, and a single damascene method may be used. The first dual damascene method may be used. In the present embodiment, the case where a two-layer wiring structure including the first and second wiring layers 6 and 12 is formed has been described. However, when it is desired to further form a third wiring layer, It can be formed by repeating the same flow.

<Embodiment 2>
In the first embodiment, the air gaps 8 and 14 are formed by applying heat to the wiring interlayer films 4 and 10. In the present embodiment, the air gaps 8 and 14 are formed by oxidizing the wiring interlayer films 4 and 10 instead of applying heat. Hereinafter, in this Embodiment, the same code | symbol shall be attached | subjected about the same structure as Embodiment 1. FIG.

  FIG. 4 is a cross-sectional view showing the configuration of the semiconductor device according to the present embodiment. As shown in FIG. 4, the semiconductor device according to the present embodiment further includes oxidation action films 15 and 16 in addition to the configuration of the semiconductor device of the first embodiment. The first wiring layer 6, which is a wiring layer according to the present embodiment, is formed on a base layer composed of the substrate contact interlayer film 1, the substrate contact layer 2, and the etching stopper film 3. Further, the second wiring layer 12 which is the wiring layer according to the present embodiment is formed on the base layer made of the via interlayer film 9.

  Oxide films 15 and 16 which are films provided in the semiconductor device according to the present embodiment are formed on the side surfaces of the first and second wiring layers 6 and 12 and are oxidized by a photocatalyst. The wiring interlayer films 4 and 10 as the first insulating films are formed in the same plane as the first and second wiring layers 6 and 12 and are vaporized by oxidation. The diffusion preventing films 7 and 13 as the second insulating films are formed on the first and second wiring layers 6 and 12, the oxidation action films 15 and 16, and the wiring interlayer films 4 and 10. The In the semiconductor device according to the present embodiment, air gaps 8 and 14 are provided in the same plane as the first and second wiring layers 6 and 12 along the oxide films 15 and 16.

  In the present embodiment, only the air gaps 8 and 14 are formed between the wirings having a small distance between the wirings of the first and second wiring layers 6 and 12. On the other hand, in addition to the air gaps 8 and 14, wiring interlayer films 4 and 10 are formed between the wirings having a large distance between the wirings of the first and second wiring layers 6 and 12, respectively.

  Since the semiconductor device according to the present embodiment as described above is provided with the air gaps 8 and 14 between the respective wirings of the first and second wiring layers 6 and 12, as in the first embodiment. The capacitance between the wirings can be reduced. Further, in the same plane as the first and second wiring layers 6, 12, wiring interlayer films 4, 10 are formed at locations away from the wirings of the first and second wiring layers 6, 12. Therefore, it is possible to prevent a decrease in mechanical strength.

  Next, a method for manufacturing the semiconductor device as described above will be described with reference to the drawings. First, the same processes as those in FIGS. 2A and 2B of the first embodiment are performed to form the structure shown in FIG. However, in the present embodiment, the wiring interlayer film 4 is not an insulating film that vaporizes at a predetermined temperature, but an insulating film that vaporizes by oxidation, for example, a carbon film.

  Thereafter, as shown in FIG. 5B, an oxidation film 15 that is oxidized by a photocatalyst is formed at least on the side surface of the wiring interlayer film 4. In the present embodiment, titanium dioxide that oxidizes when receiving light (ultraviolet rays) is used as the material of the oxidation action film 15. Next, as shown in FIG. 5C, the oxide film 15 is selectively etched so that the oxide film 15 remains only on the side surface of the wiring interlayer film 4. Subsequently, in the same manner as in the first embodiment, according to a normal damascene process, as shown in FIG. 5D, a metal to be the first wiring layer 6 is embedded in the wiring groove.

  Thus, the wiring interlayer film 4 that is vaporized by oxidation, the first wiring layer 6, the oxidizing action that is provided in contact with the wiring interlayer film 4 and the first wiring layer 6 and oxidizes by the photocatalyst on the above-described base layer. The film 15 is formed in the same plane. Subsequently, as shown in FIG. 5E, a diffusion preventing film 7 is formed on the wiring interlayer film 4, the first wiring layer 6, and the oxidation action film 15. As the diffusion preventing film 7, an insulating film that is not vaporized by oxidation is used.

  Here, if the oxidation action film 15 is irradiated with light (ultraviolet rays), the photocatalytic action of titanium dioxide works and the surrounding film is oxidized. In this embodiment, since an insulating film that is vaporized by oxidation is used for the wiring interlayer film 4, the wiring interlayer film 4 is vaporized by the oxidation action of the oxidation action film 15. Therefore, as shown in FIG. 5F, after the diffusion prevention film 7 is formed, the oxidation film 15 is irradiated with light to vaporize the portion of the wiring interlayer film 4 that is in contact with the oxidation film 15. An air gap 8 is formed along the working film 15.

  The method for forming the first wiring layer 6 has been described above. Next, the method for forming the second wiring layer 12 will be described. After the process according to FIG. 5F described above, as shown in FIG. 5G, a via interlayer film 9, a wiring interlayer film 10, and a cap film 11 are sequentially formed on the diffusion prevention film 7. In the present embodiment, the wiring interlayer film 10 is assumed to be an insulating film that is vaporized by oxidation, for example, a carbon film. Then, as shown in FIG. 6A, via grooves and wiring grooves are formed by a normal damascene method.

  Then, the process which concerns on FIG.6 (b) is performed. In this step, first, an oxidation film 16 that is oxidized by a photocatalyst is formed on at least the side surface of the wiring interlayer film 10. Next, the oxide film 16 is selectively etched so that the oxide film 16 remains only on the side surface of the wiring interlayer film 10. Subsequently, according to a normal damascene process, as shown in FIG. 6C, a metal to be the second wiring layer 12 is embedded in the trench.

  Then, the process which concerns on FIG.6 (d) is performed. In this step, first, the diffusion prevention film 13 is formed on the wiring interlayer film 10, the second wiring layer 12, and the oxidation film 16. As the diffusion preventing film 13, an insulating film that is not vaporized by oxidation is used. Then, after forming the diffusion preventing film 13, the air gap 14 is formed along the oxide film 16 by irradiating the oxide film 16 with light and evaporating the portion of the wiring interlayer film 10 in contact with the oxide film 16. Form.

  Since the semiconductor device according to the present embodiment as described above is provided with the air gaps 8 and 14 between the respective wirings of the first and second wiring layers 6 and 12, as in the first embodiment. The capacitance between the wirings can be reduced. Further, in the same plane as the first and second wiring layers 6, 12, wiring interlayer films 4, 10 are formed at locations away from the wirings of the first and second wiring layers 6, 12. Therefore, it is possible to prevent a decrease in mechanical strength.

  Further, according to the semiconductor device manufacturing method according to the present embodiment as described above, the portions of the oxide films 15 and 16 that are in contact with the first and second wiring layers 6 and 12 are vaporized. Thereby, the air gaps 8 and 14 can be formed in the same plane as the first and second wiring layers 6 and 12 substantially along the first and second wiring layers 6 and 12.

1 is a cross-sectional view showing a configuration of a semiconductor device according to a first embodiment. 8 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment. FIG. 8 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment. FIG. FIG. 6 is a cross-sectional view showing a configuration of a semiconductor device according to a second embodiment. FIG. 10 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the second embodiment. FIG. 10 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the second embodiment. It is sectional drawing which shows the manufacturing method of the conventional semiconductor device.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Substrate contact interlayer film, 2 Substrate contact layer, 3 Etching stopper film, 4,10 Wiring interlayer film, 5,11 Cap film, 6 First wiring layer, 7,13 Diffusion prevention film, 8,14 Air gap, 9 Via interlayer film, 12 2nd wiring layer, 15, 16 Oxidation action film.

Claims (4)

A wiring layer formed on the underlying layer;
A first insulating film formed in the same plane as the wiring layer and vaporized at a predetermined temperature;
A second insulating film formed on the wiring layer and on the first insulating film;
An air gap is provided in the plane along the wiring layer;
Semiconductor device. A wiring layer formed on the underlying layer;
A film that is formed on the side surface of the wiring layer and that is oxidized by a photocatalyst;
A first insulating film formed in the same plane as the wiring layer and vaporized by oxidation;
A second insulating film formed on the wiring layer, on the film, and on the first insulating film;
An air gap was provided in the plane along the membrane,
Semiconductor device. (A) forming a first insulating film vaporized at a predetermined temperature and a wiring layer on the base layer in contact with each other and in the same plane;
(B) forming a second insulating film on the first insulating film and on the wiring layer;
(C) After the step (b), the wiring layer is heated to the predetermined temperature, and a portion of the first insulating film in contact with the wiring layer is vaporized, thereby forming an air gap along the wiring layer. Forming a process,
A method for manufacturing a semiconductor device. (A) A first insulating film that is vaporized by oxidation, a wiring layer, and a film that is provided in contact with the first insulating film and the wiring layer and that oxidizes by a photocatalyst are formed in the same plane. Forming, and
(B) forming a second insulating film on the first insulating film, on the wiring layer, and on the film;
(C) after the step (b), irradiating the film with light to vaporize a portion of the first insulating film that contacts the film, thereby forming an air gap along the film. ,
A method for manufacturing a semiconductor device.

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