WO2018125063A1

WO2018125063A1 - Encapsulation of air gaps in interconnects

Info

Publication number: WO2018125063A1
Application number: PCT/US2016/068757
Authority: WO
Inventors: Manish Chandhok; Sudipto NASKAR; Jasmeet S. Chawla
Original assignee: Intel Corporation
Priority date: 2016-12-27
Filing date: 2016-12-27
Publication date: 2018-07-05

Abstract

An apparatus is provided which comprises: a plurality of interconnect layers on different planes on a semiconductor substrate, a plurality of dielectric layers separating the plurality of interconnect layers, a first metal trace and a second metal trace adjacent to the first metal trace in one of the plurality of interconnect layers, and an air gap between the first and the second metal traces, wherein the air gap extends along an entirety of facing surfaces of the first and the second metal traces. Other embodiments are also disclosed and claimed.

Description

ENCAPSULATION OF AIR GAPS IN INTERCONNECTS

BACKGROUND

[0001] As integrated circuit devices continue to scale down in feature sizes and spacing, inter-metal capacitance, from needing to route metal traces so close together, is becoming a limiting factor for device performance. Driving signals at very high speeds through metal traces fractions of a millimeter apart can lead to unacceptable cross talk and power dissipation.

BRIEF DESCRIPTION OF THE DRAWINGS

[0002] The embodiments of the disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure, which, however, should not be taken to limit the disclosure to the specific embodiments, but are for explanation and understanding only.

[0003] Fig. 1 illustrates a cross-sectional view of an integrated circuit device with encapsulation of air gaps in interconnects, according to some embodiments,

[0004] Figs. 2Α-2Ι illustrate cross-sectional views of manufacturing steps of

encapsulation of air gaps in interconnects, according to some embodiments,

[0005] Fig. 3 illustrates a diagram of an example semiconductor manufacturing equipment, according to some embodiments,

[0006] Fig. 4 illustrates a flowchart of a method of forming an integrated circuit device with encapsulation of air gaps in interconnects, in accordance with some embodiments, and

[0007] Fig. 5 illustrates a smart device or a computer system or a SoC (System-on-Chip) which includes an integrated circuit device with encapsulation of air gaps in interconnects, according to some embodiments.

DETAILED DESCRIPTION

[0008] Encapsulation of air gaps in interconnects are generally presented. In this regard, embodiments of the present invention enable opposite surfaces of adjacent interconnects to be free from dielectric material. One skilled in the art would appreciate that these air gaps may enable finer feature sizes compared to typical air gaps lined with dielectric material, due to issues with the latter of inter-metal capacitance. Additionally, these air gaps with clean sidewalls having no deposition may reduce cross talk and power dissipation without the need for lower It- value dielectric.

[0009] In the following description, numerous details are discussed to provide a more thorough explanation of embodiments of the present disclosure. It will be apparent, however, to one skilled in the art, that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring embodiments of the present disclosure.

[0010] Note that in the corresponding drawings of the embodiments, signals are represented with lines. Some lines may be thicker, to indicate more constituent signal paths, and/or have arrows at one or more ends, to indicate primary information flow direction. Such indications are not intended to be limiting. Rather, the lines are used in connection with one or more exemplary embodiments to facilitate easier understanding of a circuit or a logical unit. Any represented signal, as dictated by design needs or preferences, may actually comprise one or more signals that may travel in either direction and may be implemented with any suitable type of signal scheme.

[0011] Throughout the specification, and in the claims, the term "connected" means a direct connection, such as electrical, mechanical, or magnetic connection between the things that are connected, without any intermediary devices. The term "coupled" means a direct or indirect connection, such as a direct electrical, mechanical, or magnetic connection between the things that are connected or an indirect connection, through one or more passive or active intermediary devices. The term "circuit" or "module" may refer to one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function. The term "signal" may refer to at least one current signal, voltage signal, magnetic signal, or data/clock signal. The meaning of "a," "an," and "the" include plural references. The meaning of "in" includes "in" and "on."

[0012] Unless otherwise specified the use of the ordinal adjectives "first," "second," and

"third," etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner. [0013] For the purposes of the present disclosure, phrases "A and/or B" and "A or B" mean (A), (B), or (A and B). For the purposes of the present disclosure, the phrase "A, B, and/or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C). The terms "left," "right," "front," "back," "top," "bottom," "over," "under," and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions.

[0014] Fig. 1 illustrates a cross-sectional view of an integrated circuit device with encapsulation of air gaps in interconnects, according to some embodiments. As shown, device 100 includes interconnect layers 102, circuit substrate 104, metal 106, dielectric 108, air gaps 110, substrate 112, circuits 114, and contacts 116.

[0015] Interconnect layers 102 may provide electrical connections between components of circuit substrate 104 and contacts 116, which may be lands, bumps, pins, etc., to couple device 100 with external substrates, interposers, packages, sockets, etc. Interconnect layers 102 may be formed iteratively on separate planes above circuit substrate 104. In some embodiments, interconnect layers 102 includes metal 106, such as copper, that may be plated into etched trenches and vias, then polished back to create metal trenches, planes, and vias, for example to communicate power and signals to and from circuit substrate 104. Metal 106 in interconnect layers 102 may be interspersed with dielectric 108, which has insulative properties. In some embodiments, dielectric 108 represents an interlay er dielectric (TLD) material, such as carbon doped oxide (CDO), deposited conformally across metal 106 structures to a thickness at least equivalent to a thickness of an interconnect structure including wiring lines and subsequent level conductive vias.

[0016] Circuit substrate 104 may include integrated circuits in a circuits 114 layer on a substrate 112. In some embodiments, circuits 114 include semiconductor transistors, switches, gates, relays, and/or memory components. Circuits 114 may include millions of circuit devices or components that each include an input, an output, and/or a power signal communicated through interconnect layers 102. Substrate 112 may be made of silicon, other semiconductor material, and/or other non-semiconductor material.

[0017] Air gaps 110 may be formed between adjacent metal traces in various

interconnect layers 102 as shown in more detail hereinafter. In some embodiments, air gaps 110, and surrounding metal traces, increase in height and width in interconnect layers 102 further away from circuit substrate 104. In some embodiments, air gaps 1 10 in higher interconnect layers 102 may have widths of up to about 80 nm and heights of up to about 50 nm, while air gaps 1 10 in lower interconnect layers 102 may have widths of as low as about 20 nm and heights of as low as about 15 nm. In other embodiments, different size ranges may be utilized for air gaps 1 10 in any of interconnect layers 102.

[0018] Figs. 2A-2I illustrate cross-sectional views of manufacturing steps of

encapsulation of air gaps in interconnects, according to some embodiments. As shown in Fig. 2A, assembly 200 includes circuit substrate 202, interconnect layers 204, and metal traces 206. Interconnect layers 204 may represent any number of layers, for example interconnect layers 102, that have been built up on circuit substrate 202. Metal traces 206 may have been plated into etched trenches and vias, then polished back to create metal trenches to form adjacent metal traces 206. Metal traces 206 may be electrically coupled with structures in interconnect layers 204 and circuit substrate 202 through vias, not shown. While shown as having straight sides, metal traces 206 may have curved and/or irregular sides.

[0019] Fig. 2B shows assembly 210, which may include dielectric 208 deposited on a

(top) surface of adjacent metal traces 208. Dielectric 208 may be deposited by atomic layer deposition (ALD), chemical vapour deposition (CVD), plasma enhanced CVD (PECVD), or by other means. In some embodiments, dielectric 208 is deposited as described in further detail hereinafter to prevent dielectric 208 from being deposited on other (sidewall) surfaces of metal traces 206.

[0020] As shown in Fig. 2C, assembly 220 has had some of dielectric 208 removed, for example through etching. In some embodiments, dielectric 208 has been removed from over trench 212 between adjacent metal traces 206. In some embodiments, dielectric 208 has edges substantially parallel with edges of metal traces 206.

[0021] Turning now to Fig. 2D, assembly 230 may include additional dielectric 208 that has been deposited on metal traces 206. In some embodiments, an upper portion of dielectric 208 overhangs above trench 212.

[0022] Fig. 2E shows assembly 240, which may have had some of dielectric 208 removed from over trench 212, such that edges of dielectric 208 extend substantially straight beyond edges of metal traces 206. [0023] As shown in Fig. 2F, for assembly 250 the steps of depositing and removing dielectric 208 may have been repeated any number of times to result in dielectric 208 extending a height 214 on metal traces 206. In some embodiments, height 214 can result in adding greater depth to trench 212.

[0024] Turning now to Fig. 2G, assembly 260 may include dielectric 208 deposited on metal traces 206 to form helmets that extend outwardly over the space between metal traces 206.

[0025] Fig. 2H shows assembly 270, which may include dielectric 216 closing off the space between adjacent metal traces 206 and forming air gaps 218. Air gaps 218 may extend, initially, substantially straight beyond the edges of adjacent metal traces 206 adjacent dielectric 216. In some embodiments, In some embodiments, facing surfaces of adjacent metal traces 206 are completely void of dielectric material. In some embodiments, dielectric 216 has edges 222 substantially parallel with, or analogous to, edges of metal traces 206. In some embodiments air gaps 218 may have a height of between about 15 nm and 50 nm. In some embodiments, air gaps 218 may have a width of between about 20 nm and 80 nm.

[0026] As shown in Fig. 21, assembly 280 includes sealing material 224 over dielectric

216. In some embodiments, sealing material 224 may provide a hermetic seal for air gaps 218. In some embodiments, sealing material 224 may include SiCN, AI2O3, or SiN. In some

embodiments, sealing material 224 may include a thickness of between about 4 nm and 25 nm.

[0027] Fig. 3 illustrates a diagram of an example semiconductor manufacturing equipment, according to some embodiments. As shown, equipment 300 includes deposition chamber 302, etch chamber 304, substrate 306, pedestal 308, precursor control 310, etch control 312 and access 314. Substrate 306 may represent intermediary assemblies of an integrated circuit device, such as any of the assemblies depicted in Figs. 2A-2I. Pedestal 308 may support substrate 306 and may be used to transport substrate 306 between deposition chamber 302 and etch chamber 304, for example through access 314, which may represent a sliding door.

[0028] Deposition chamber 302 may be used to deposit dielectric material, such as dielectric 208 or 216, on metal traces 206. Deposition chamber 302 may perform any type of deposition, including, but not limited to, ALD, CVD, PECVD, etc. In some embodiments, precursor control 310 controls the deposition process by controlling the supply of precursor molecules necessary for deposition to occur. In some embodiments, precursor control 310 may provide precursor molecules at a relatively high speed perpendicular to metal traces 206 to prevent dielectric from being deposited in trench 212 along sidewalls of metal traces 206. In some embodiments, pedestal 308 rotates substrate 306 during a deposition to further prevent dielectric from being deposited in trench 212 along sidewalls of metal traces 206.

[0029] Etch chamber 304 may be used to selectively remove dielectric material, for example, dielectric 208 that overhangs trench 212. Etch control 312 may control the etch process by directing etchants, for example chemical etchants, to the material to be removed. In some embodiments, etch control 312 includes masking of material to be preserved.

[0030] Fig. 4 illustrates a flowchart of a method of forming an integrated circuit device with encapsulation of air gaps in interconnects, in accordance with some embodiments. Although the blocks in the flowchart with reference to Fig. 4 are shown in a particular order, the order of the actions can be modified. Thus, the illustrated embodiments can be performed in a different order, and some actions/blocks may be performed in parallel. Some of the blocks and/or operations listed in Fig. 4 are optional in accordance with certain embodiments. The numbering of the blocks presented is for the sake of clarity and is not intended to prescribe an order of operations in which the various blocks must occur. Additionally, operations from the various flows may be utilized in a variety of combinations.

[0031] Method 400 begins with forming (402) interconnects, for example in a plane on a dielectric layer on a substrate, such as metal traces 206. Next, deposition is performed (404). For example dielectric 208 may be formed on metal traces 206 in deposition chamber 302. In some embodiments, precursor control 310 may injected precursor molecules at relatively high velocity while pedestal 308 rotates assembly 210 to prevent dielectric from being deposited along sidewalls of metal traces 206.

[0032] Then, excess material, for example dielectric 208 that overhangs trench 212, may be etched (406) in etch chamber 304 by chemical or other means. Next, as necessary to grow dielectric 208 to an appropriate height 214, any number of iterative depositions and etches may be performed (408) for example as shown in assemblies 230 and 240.

[0033] The method continues with depositing (410) dielectric 216 to close air gaps 218.

In some embodiments, edges 222 of dielectric 216 extending substantially parallel with edges of metal traces 206. Next, a hermetic seal, such as sealing material 224, may be added (412) on dielectric 216. Finally, additional interconnect layers 102 may be formed (414) to further form device 100, for example. [0034] Fig. 5 illustrates a smart device or a computer system or a SoC (System-on-Chip)

500 which includes an integrated circuit device with encapsulation of air gaps in interconnects, according to some embodiments. In some embodiments, computing device 500 represents a mobile computing device, such as a computing tablet, a mobile phone or smart-phone, a wireless-enabled e-reader, or other wireless mobile device. It will be understood that certain components are shown generally, and not all components of such a device are shown in computing device 500. In some embodiments, one or more components of computing device 500, for example processor 510 and/or memory subsystem 560, include an integrated circuit device with encapsulation of air gaps in interconnects as described above.

[0035] For purposes of the embodiments, the transistors in various circuits and logic blocks described here are metal oxide semiconductor (MOS) transistors or their derivatives, where the MOS transistors include drain, source, gate, and bulk terminals. The transistors and/or the MOS transistor derivatives also include Tri-Gate and FinFET transistors, Gate All Around Cylindrical Transistors, Tunneling FET (TFET), Square Wire, or Rectangular Ribbon

Transistors, ferroelectric FET (FeFETs), or other devices implementing transistor functionality like carbon nanotubes or spintronic devices. MOSFET symmetrical source and drain terminals i.e., are identical terminals and are interchangeably used here. A TFET device, on the other hand, has asymmetric Source and Drain terminals. Those skilled in the art will appreciate that other transistors, for example, Bi-polar junction transistors— BJT PNP/NPN, BiCMOS, CMOS, etc., may be used without departing from the scope of the disclosure.

[0036] In some embodiments, computing device 500 includes a first processor 510. The various embodiments of the present disclosure may also comprise a network interface within 570 such as a wireless interface so that a system embodiment may be incorporated into a wireless device, for example, cell phone or personal digital assistant.

[0037] In one embodiment, processor 510 can include one or more physical devices, such as microprocessors, application processors, microcontrollers, programmable logic devices, or other processing means. The processing operations performed by processor 510 include the execution of an operating platform or operating system on which applications and/or device functions are executed. The processing operations include operations related to I/O

(input/output) with a human user or with other devices, operations related to power management, and/or operations related to connecting the computing device 500 to another device. The processing operations may also include operations related to audio I/O and/or display I/O.

[0038] In one embodiment, computing device 500 includes audio subsystem 520, which represents hardware (e.g., audio hardware and audio circuits) and software (e.g., drivers, codecs) components associated with providing audio functions to the computing device. Audio functions can include speaker and/or headphone output, as well as microphone input. Devices for such functions can be integrated into computing device 500, or connected to the computing device 500. In one embodiment, a user interacts with the computing device 500 by providing audio commands that are received and processed by processor 510.

[0039] Display subsystem 530 represents hardware (e.g., display devices) and software

(e.g., drivers) components that provide a visual and/or tactile display for a user to interact with the computing device 500. Display subsystem 530 includes display interface 532, which includes the particular screen or hardware device used to provide a display to a user. In one embodiment, display interface 532 includes logic separate from processor 510 to perform at least some processing related to the display. In one embodiment, display subsystem 530 includes a touch screen (or touch pad) device that provides both output and input to a user.

[0040] I/O controller 540 represents hardware devices and software components related to interaction with a user. I/O controller 540 is operable to manage hardware that is part of audio subsystem 520 and/or display subsystem 530. Additionally, I/O controller 540 illustrates a connection point for additional devices that connect to computing device 500 through which a user might interact with the system. For example, devices that can be attached to the computing device 500 might include microphone devices, speaker or stereo systems, video systems or other display devices, keyboard or keypad devices, or other I/O devices for use with specific applications such as card readers or other devices.

[0041] As mentioned above, I/O controller 540 can interact with audio subsystem 520 and/or display subsystem 530. For example, input through a microphone or other audio device can provide input or commands for one or more applications or functions of the computing device 500. Additionally, audio output can be provided instead of, or in addition to display output. In another example, if display subsystem 530 includes a touch screen, the display device also acts as an input device, which can be at least partially managed by I/O controller 540. There can also be additional buttons or switches on the computing device 500 to provide I/O functions managed by I/O controller 540.

[0042] In one embodiment, I/O controller 540 manages devices such as accelerometers, cameras, light sensors or other environmental sensors, or other hardware that can be included in the computing device 500. The input can be part of direct user interaction, as well as providing environmental input to the system to influence its operations (such as filtering for noise, adjusting displays for brightness detection, applying a flash for a camera, or other features).

[0043] In one embodiment, computing device 500 includes power management 550 that manages battery power usage, charging of the battery, and features related to power saving operation. Memory subsystem 560 includes memory devices for storing information in computing device 500. Memory can include nonvolatile (state does not change if power to the memory device is interrupted) and/or volatile (state is indeterminate if power to the memory device is interrupted) memory devices. Memory subsystem 560 can store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) related to the execution of the applications and functions of the computing device 500.

[0044] Elements of embodiments are also provided as a machine-readable medium (e.g., memory 560) for storing the computer-executable instructions. The machine-readable medium (e.g., memory 560) may include, but is not limited to, flash memory, optical disks, CD-ROMs, DVD ROMs, RAMs, EPROMs, EEPROMs, magnetic or optical cards, phase change memory (PCM), or other types of machine-readable media suitable for storing electronic or computer- executable instructions. For example, embodiments of the disclosure may be downloaded as a computer program (e.g., BIOS) which may be transferred from a remote computer (e.g., a server) to a requesting computer (e.g., a client) by way of data signals via a communication link (e.g., a modem or network connection).

[0045] Connectivity 570 includes hardware devices (e.g., wireless and/or wired connectors and communication hardware) and software components (e.g., drivers, protocol stacks) to enable the computing device 500 to communicate with external devices. The computing device 500 could be separate devices, such as other computing devices, wireless access points or base stations, as well as peripherals such as headsets, printers, or other devices. [0046] Connectivity 570 can include multiple different types of connectivity. To generalize, the computing device 500 is illustrated with cellular connectivity 572 and wireless connectivity 574. Cellular connectivity 572 refers generally to cellular network connectivity provided by wireless carriers, such as provided via GSM (global system for mobile

communications) or variations or derivatives, CDMA (code division multiple access) or variations or derivatives, TDM (time division multiplexing) or variations or derivatives, or other cellular service standards. Wireless connectivity (or wireless interface) 574 refers to wireless connectivity that is not cellular, and can include personal area networks (such as Bluetooth, Near Field, etc.), local area networks (such as Wi-Fi), and/or wide area networks (such as WiMax), or other wireless communication.

[0047] Peripheral connections 580 include hardware interfaces and connectors, as well as software components (e.g., drivers, protocol stacks) to make peripheral connections. It will be understood that the computing device 500 could both be a peripheral device ("to" 582) to other computing devices, as well as have peripheral devices ("from" 584) connected to it. The computing device 500 commonly has a "docking" connector to connect to other computing devices for purposes such as managing (e.g., downloading and/or uploading, changing, synchronizing) content on computing device 500. Additionally, a docking connector can allow computing device 500 to connect to certain peripherals that allow the computing device 500 to control content output, for example, to audiovisual or other systems.

[0048] In addition to a proprietary docking connector or other proprietary connection hardware, the computing device 500 can make peripheral connections 580 via common or standards-based connectors. Common types can include a Universal Serial Bus (USB) connector (which can include any of a number of different hardware interfaces), DisplayPort including MiniDisplayPort (MDP), High Definition Multimedia Interface (HDMI), Firewire, or other types.

[0049] Reference in the specification to "an embodiment," "one embodiment," "some embodiments," or "other embodiments" means that a particular feature, structure, or

characteristic described in connection with the embodiments is included in at least some embodiments, but not necessarily all embodiments. The various appearances of "an

embodiment," "one embodiment," or "some embodiments" are not necessarily all referring to the same embodiments. If the specification states a component, feature, structure, or characteristic "may," "might," or "could" be included, that particular component, feature, structure, or characteristic is not required to be included. If the specification or claim refers to "a" or "an" element, that does not mean there is only one of the elements. If the specification or claims refer to "an additional" element, that does not preclude there being more than one of the additional element.

[0050] Furthermore, the particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment anywhere the particular features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive

[0051] While the disclosure has been described in conjunction with specific

embodiments thereof, many alternatives, modifications and variations of such embodiments will be apparent to those of ordinary skill in the art in light of the foregoing description. The embodiments of the disclosure are intended to embrace all such alternatives, modifications, and variations as to fall within the broad scope of the appended claims.

[0052] In addition, well known power/ground connections to integrated circuit (IC) chips and other components may or may not be shown within the presented figures, for simplicity of illustration and discussion, and so as not to obscure the disclosure. Further, arrangements may be shown in block diagram form in order to avoid obscuring the disclosure, and also in view of the fact that specifics with respect to implementation of such block diagram arrangements are highly dependent upon the platform within which the present disclosure is to be implemented (i.e., such specifics should be well within purview of one skilled in the art). Where specific details (e.g., circuits) are set forth in order to describe example embodiments of the disclosure, it should be apparent to one skilled in the art that the disclosure can be practiced without, or with variation of, these specific details. The description is thus to be regarded as illustrative instead of limiting.

[0053] The following examples pertain to further embodiments. Specifics in the examples may be used anywhere in one or more embodiments. All optional features of the apparatus described herein may also be implemented with respect to a method or process.

[0054] In one example an apparatus is provided comprising: a plurality of interconnect layers on different planes on a semiconductor substrate; a first metal trace and a second metal trace adjacent to the first metal trace in one of the plurality of interconnect layers; and an air gap between the first and the second metal traces, wherein the air gap extends along an entirety of facing surfaces of the first and the second metal traces.

[0055] In some embodiments, the air gap extends substantially straight beyond the edges of the metal traces adjacent dielectric material. Some embodiments also include a third metal trace adjacent the second metal trace and a second air gap between the second and third metal traces. Some embodiments also include a third metal trace adjacent to a fourth metal trace and a second air gap between the third and fourth metal traces in a different plane from the first air gap. In some embodiments, an air gap height comprises between about 15 nm and 50 nm. In some embodiments, an air gap width comprises between about 20 nm and 80 nm.

[0056] In another example, an integrated circuit device is provided comprising: a semiconductor substrate; a plurality of interconnect layers on different planes on the substrate; a plurality of metal traces in one of the plurality of interconnect layers; and a plurality of air gaps between adjacent metal traces, wherein the air gaps extend along an entirety of facing surfaces of the adjacent metal traces.

[0057] In some embodiments, the air gaps extend substantially straight beyond the edges of the metal traces adjacent dielectric material. Some embodiments also include dielectric material adjacent one side of the air gaps, and a layer of sealing material covering the dielectric material. In some embodiments, the sealing material is chosen from the group consisting of: SiCN, AI2O3, and SiN. In some embodiments, an air gap height comprises between about 15 nm and 50 nm. In some embodiments, an air gap width comprises between about 20 nm and 80 nm.

[0058] In another example, a system is provided comprising: a display subsystem; a wireless communication interface; and an integrated circuit device, the integrated circuit device comprising: a semiconductor substrate; a plurality of interconnect layers on different planes on the substrate; a plurality of metal traces in a first of the plurality of interconnect layers; a plurality of metal traces in a second of the plurality of interconnect layers further from the substrate than the first interconnect layer; and a plurality of air gaps in the first and second interconnect layers between adjacent metal traces, wherein the air gaps extend along an entirety of facing surfaces of the adjacent metal traces.

[0059] In some embodiments, the air gaps extend substantially straight beyond the edges of the metal traces adjacent dielectric material. In some embodiments, air gaps in the second interconnect layer are deeper than air gaps in the first interconnect layer. In some embodiments, air gaps in the second interconnect layer are wider than air gaps in the first interconnect layer. In some embodiments, an air gap height comprises between about 15 nm and 50 nm. In some embodiments, an air gap width comprises between about 20 nm and 80 nm.

[0060] In another example, a method is provided comprising: forming a first metal trace and a second metal trace adjacent to the first metal trace on a plane on a semiconductor substrate; and forming an air gap between the first and the second metal traces, wherein the air gap extends along an entirety of facing surfaces of the first and the second metal traces.

[0061] In some embodiments, forming an air gap between the first and the second metal traces comprises: depositing dielectric material on the first and second metal traces; etching dielectric material that was deposited beyond the edges of the first and second metal traces; and depositing further dielectric material to enclose the air gap. In some embodiments, depositing dielectric material comprises performing atomic layer deposition (ALD) while rotating the substrate. In some embodiments, depositing dielectric material further comprises injecting precursor molecules at relatively high velocity.

[0062] Some embodiments also include depositing a layer of material over the dielectric material to form a hermetic seal. In some embodiments, forming an air gap comprises iteratively performing two or more in situ etchs between helmet depositions to remove dielectric material that was deposited beyond the edges of the first and second metal traces. Some embodiments also include forming additional interconnect and dielectric layers on the substrate to form an integrated circuit device.

[0063] In another example, an integrated circuit device with encapsulation of air gaps in interconnects is provided comprising: a plurality of circuit means; a plurality of external contact means; a plurality of interconnect means to conductively couple the circuit means with the external contact means; and a plurality of air gap means between adjacent interconnect means, wherein the air gap means extend along an entirety of facing surfaces of the adjacent

interconnect means.

[0064] In some embodiments, the air gap means extend substantially straight beyond the edges of the interconnect means adjacent dielectric means. Some embodiments also include dielectric means adjacent one side of the air gap means, and a layer of sealing means covering the dielectric means. In some embodiments, the sealing means is chosen from the group consisting of: SiCN, AI2O3, and SiN. In some embodiments, an air gap height comprises between about 15 nm and 50 nm. In some embodiments, an air gap width comprises between about 20 nm and 80 nm.

[0065] An abstract is provided that will allow the reader to ascertain the nature and gist of the technical disclosure. The abstract is submitted with the understanding that it will not be used to limit the scope or meaning of the claims. The following claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment.

Claims

CLAIMS We claim:

1. An apparatus comprising:

a plurality of interconnect layers on different planes on a semiconductor substrate; a first metal trace and a second metal trace adjacent to the first metal trace in one of the plurality of interconnect layers; and

an air gap between the first and the second metal traces, wherein the air gap extends along an entirety of facing surfaces of the first and the second metal traces.

2. The apparatus of claim 1, further comprising wherein the air gap extends substantially straight beyond the edges of the metal traces adjacent dielectric material.

3. The apparatus of claim 2, further comprising a third metal trace adjacent the second metal trace and a second air gap between the second and third metal traces.

4. The apparatus of claim 2, further comprising a third metal trace adjacent to a fourth metal trace and a second air gap between the third and fourth metal traces in a different plane from the first air gap.

5. The apparatus according to any one of claims 1 to 4, wherein an air gap height comprises between about 15 nm and 50 nm.

6. The apparatus according to any one of claims 1 to 4, wherein an air gap width comprises between about 20 nm and 80 nm.

7. An integrated circuit device comprising:

a semiconductor substrate;

a plurality of interconnect layers on different planes on the substrate;

a plurality of metal traces in one of the plurality of interconnect layers; and a plurality of air gaps between adjacent metal traces, wherein the air gaps extend along an entirety of facing surfaces of the adjacent metal traces.

8. The integrated circuit device of claim 7, further comprising wherein the air gaps extend

substantially straight beyond the edges of the metal traces adjacent dielectric material.

9. The integrated circuit device of claim 8, further comprising dielectric material adjacent one side of the air gaps, and a layer of sealing material covering the dielectric material.

10. The integrated circuit device of claim 9, further comprising the sealing material is chosen from the group consisting of: SiCN, AI2O3, and SiN.

11. The integrated circuit device according to any one of claims 7 to 10, wherein an air gap

height comprises between about 15 nm and 50 nm.

12. The integrated circuit device according to any one of claims 7 to 10, wherein an air gap width comprises between about 20 nm and 80 nm.

13. A system comprising:

a display subsystem;

a wireless communication interface; and

an integrated circuit device, the integrated circuit device comprising:

a semiconductor substrate;

a plurality of interconnect layers on different planes on the substrate; a plurality of metal traces in a first of the plurality of interconnect layers;

a plurality of metal traces in a second of the plurality of interconnect layers further from the substrate than the first interconnect layer; and

a plurality of air gaps in the first and second interconnect layers between adjacent metal traces, wherein the air gaps extend along an entirety of facing surfaces of the adjacent metal traces.

14. The system of claim 13, further comprising wherein the air gaps extend substantially straight beyond the edges of the metal traces adjacent dielectric material.

15. The system of claim 14, further comprising wherein air gaps in the second interconnect layer are deeper than air gaps in the first interconnect layer.

16. The system of claim 13, further comprising wherein air gaps in the second interconnect layer are wider than air gaps in the first interconnect layer.

17. The system of any of claims 13 to 16, wherein an air gap height comprises between about 15 nm and 50 nm.

18. The system of any of claims 13 to 16, wherein an air gap width comprises between about 20 nm and 80 nm.

19. A method comprising:

forming a first metal trace and a second metal trace adjacent to the first metal trace on a plane on a semiconductor substrate; and

forming an air gap between the first and the second metal traces, wherein the air gap extends along an entirety of facing surfaces of the first and the second metal traces.

20. The method of claim 19, wherein forming an air gap between the first and the second metal traces comprises:

depositing dielectric material on the first and second metal traces; etching dielectric material that was deposited beyond the edges of the first and second metal traces; and

depositing further dielectric material to enclose the air gap.

21. The method of claim 20, wherein depositing dielectric material comprises performing atomic layer deposition (ALD) while rotating the substrate.

22. The method of claim 21, wherein depositing dielectric material further comprises injecting precursor molecules at relatively high velocity.

23. The method of any of claims 20, further comprising depositing a layer of material over the dielectric material to form a hermetic seal.

24. The method of claim 19 to 23, wherein forming an air gap comprises iteratively performing two or more in situ etchs between helmet depositions to remove dielectric material that was deposited beyond the edges of the first and second metal traces.

25. The method of any of claims 19 to 23, further comprising forming additional interconnect and dielectric layers on the substrate to form an integrated circuit device.