JP2005217371A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device having excellent electrical characteristics and a method of manufacturing the same by preventing the diffusion of barrier-metal material and copper into pores. <P>SOLUTION: A diffusion preventing film 3 and an interlayer insulating film 4 are formed on a lower-layer wiring 1. The interlayer insulating film 4 is a porous low-dielectric-constant insulating film with a dielectric constant of lower than 3.0. A via-plug 17 and a copper wiring layer 18 are provided in the interlayer insulating film 4. Between the interlayer insulating film 4 and the barrier-metal film 14, a reaction-product film 9 containing carbon and fluorine is formed as an intermediate film. The film thickness of the reaction-product film 9 is preferably in the range of 1 nm to 15 nm. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device using a porous low dielectric constant insulating film as an interlayer insulating film and a manufacturing method thereof.

  With the recent miniaturization and speeding up of semiconductor devices, multilayer wiring structures are progressing. However, as such miniaturization, higher speed, and multilayering progress, signal delay due to increase in wiring resistance and parasitic capacitance between wirings and between wiring layers becomes a problem. Since the signal delay T is proportional to the product of the wiring resistance R and the parasitic capacitance C, in order to reduce the signal delay T, it is necessary to reduce the parasitic capacitance as well as the resistance of the wiring layer.

  In order to reduce the wiring resistance R, a wiring material having a lower resistance may be used. Specifically, a transition from a conventional aluminum (Al) wiring to a copper (Cu) wiring is exemplified.

  On the other hand, between the parasitic capacitance C between the wiring layers and the relative dielectric constant ε of the interlayer insulating film provided between the wiring layers, the distance d between the wiring layers, and the side area S of the wiring layer, C = (ε · S ) / D. Therefore, in order to reduce the parasitic capacitance C, it is necessary to use a low dielectric constant insulating film (hereinafter referred to as a low-k film) as an interlayer insulating film.

A conventionally known Low-k film includes a SiOF film formed by a CVD (Chemical Vapor Deposition) method. The relative dielectric constant of the SiOF film is about 3.3, and a lower dielectric constant can be obtained as compared with the SiO ₂ film having a relative dielectric constant of about 3.9. However, when further reducing the relative dielectric constant, the SiOF film is extremely difficult to put into practical use because the film lacks stability.

  In addition, the use of a SOG (Spin on Glass) film, an organic polymer film, or the like as the low-k film is also under study. By making these films porous, it is possible to lower the relative dielectric constant to about 2.0.

  As a method for forming a copper wiring using such a low-k film, there is a damascene method. This is known as a technique for forming a wiring without etching copper, considering that it is difficult to control the etching rate of copper compared to aluminum.

  Specifically, in the damascene method, an opening reaching the lower layer wiring is formed by dry etching of a low-k film, and then a copper wiring layer is formed by embedding a copper layer through a barrier metal film in the opening. Technology. The copper layer is embedded by forming a copper layer so as to embed the opening by plating, and then polishing the surface by CMP (Chemical Mechanical Polishing) so that the copper layer remains only in the opening. Can be realized.

  In a low-k film made porous, the relative permittivity can be lowered as the internal porosity increases. However, when the porosity increases, the film density decreases and the holes are exposed on the side wall of the opening. For this reason, as a result of the barrier metal film material diffusing into the vacancies and partially reducing the barrier properties, there is a problem that copper diffuses into the low-k film. This is shown in FIG.

  FIG. 11 is a cross-sectional view of a conventional semiconductor device, showing a state before planarization by the CMP method. In the figure, a diffusion prevention film 24 and a porous low-k film 25 are formed on a lower wiring 23 having a barrier metal film 21 and a copper layer 22. Further, the diffusion prevention film 24 and the low-k film 25 are provided with a via hole 26 and a wiring groove 27, and a copper layer 30 is embedded in these via a barrier metal film 28 and a seed copper film 29. ing. As shown in the figure, the Low-k film 25 has a region 31 in which barrier metal is diffused, and a region 32 in which copper is partially diffused is formed in the region 31. Such copper diffusion occurs during the manufacturing process and operation of the semiconductor device. The diffused copper forms a leakage current path 33 between the wirings, causing a reduction in manufacturing yield and a malfunction of the semiconductor device.

  In order to solve this problem, a method has been proposed in which diffusion of barrier metal is prevented by shrinking vacancies by performing plasma heat treatment on the surface of the low-k film and via holes (see, for example, Patent Document 1). .)

JP 2003-273216 A

  In the above method, it is necessary to prevent an increase in the dielectric constant due to vacancy shrinkage. For this reason, it is necessary to control the plasma energy so that an extremely thin modified layer is formed only on the surface of the low-k film. However, such control is technically extremely difficult, and there is a problem that an increase in the dielectric constant cannot be avoided.

  The present invention has been made in view of such problems. That is, an object of the present invention is to provide a semiconductor device having excellent electrical characteristics by preventing diffusion of a barrier metal material and copper into pores by a simple method and a method for manufacturing the same.

  Other objects and advantages of the present invention will become apparent from the following description.

  The present invention relates to a diffusion preventing film provided on a lower wiring, a porous interlayer insulating film having a relative dielectric constant of less than 3.0 provided on the diffusion preventing film, a diffusion preventing film, and an interlayer insulating film. A semiconductor device having a copper wiring embedded in an opening provided in a via a barrier metal film, wherein an intermediate film containing carbon and fluorine is formed between the interlayer insulating film and the barrier metal film It is characterized by.

  In the semiconductor device of the present invention, the diffusion barrier film can be made of a material containing carbon.

  In the semiconductor device of the present invention, a cap film made of a material containing carbon can be further provided on the interlayer insulating film.

  In the semiconductor device of the present invention, the intermediate film can be an insulating film, and the thickness of the insulating film can be in the range of 1 nm to 15 nm.

  In the method for manufacturing a semiconductor device of the present invention, the interlayer insulating film can be one of a siloxane inorganic material and an organic polymer organic material.

  The present invention provides a method for manufacturing a semiconductor device having a multilayer wiring structure, the step of forming a porous interlayer insulating film having a relative dielectric constant of less than 3.0 above a semiconductor substrate on which a lower layer wiring is formed; The interlayer insulating film is subjected to dry etching using a resist film processed into a predetermined pattern as a mask and using a fluorocarbon-based gas to form an opening reaching the lower layer wiring, and on the side wall of the interlayer insulating film. A step of forming a reaction product film of carbon and fluorine, a step of removing the resist film under conditions that do not completely remove the reaction product film, a step of forming a barrier metal film on the inner surface of the opening, and the barrier metal And a step of forming a copper layer so as to embed the opening through the film.

  In the semiconductor device manufacturing method of the present invention, the opening can be one of a via hole and a wiring trench.

  In the method for manufacturing a semiconductor device of the present invention, the step of removing the resist film can be an ashing step in a reducing atmosphere.

  In the method for manufacturing a semiconductor device of the present invention, the step of removing the resist film may be an ashing step in a reducing atmosphere and a cleaning step following the ashing step.

  In the method for manufacturing a semiconductor device of the present invention, the thickness of the reaction product film after removing the resist film can be in the range of 1 nm to 15 nm.

  The present invention relates to a method of manufacturing a semiconductor device having a multilayer wiring structure, a step of forming a diffusion prevention film on a lower layer wiring, and a porous material having a relative dielectric constant of less than 3.0 on the diffusion prevention film. The interlayer insulating film is formed, and the interlayer insulating film and the diffusion prevention layer are dry-etched using the first resist film processed into a predetermined pattern as a mask and using a fluorocarbon-based gas to form a lower layer wiring. A step of forming a via hole, a step of removing the first resist film, a second resist film processed into a predetermined pattern as a mask and dry etching the interlayer insulating film using a fluorocarbon-based gas, A step of forming a wiring trench connected to the via hole, a step of removing the second resist film, and a step of forming a barrier metal film on the inner surface of the via hole and the wiring trench Forming a copper layer so as to fill the via hole and the wiring groove through the barrier metal film, and the step of forming the via hole and the step of forming the wiring groove include carbon and carbon on the side wall portion of the interlayer insulating film. It is also a step of forming a fluorine reaction product film, and the step of removing the first resist film and the step of removing the second resist film are performed under conditions that do not completely remove the reaction product film. To do.

  In the method for manufacturing a semiconductor device of the present invention, the thickness of the reaction product film after the removal of the first resist film and the second resist film is preferably in the range of 1 nm to 15 nm.

In the method for manufacturing a semiconductor device of the present invention, the fluorocarbon-based gas is at least one selected from the group consisting of CHF ₃ gas, CH ₂ F ₂ gas, C ₅ F ₈ gas, CF ₄ gas, and C ₄ F ₈ gas. It can be gas.

  According to the present invention, since the intermediate film containing carbon and fluorine is formed between the interlayer insulating film and the barrier metal film, the diffusion of the barrier metal and copper into the vacancies can be easily prevented, and the electrical A semiconductor device having excellent characteristics can be obtained.

  Further, according to the present invention, when forming an opening leading to the lower layer wiring, a reaction product film of carbon and fluorine is formed on the side wall of the interlayer insulating film, and the resist is formed under a condition that the reaction product film is not completely removed. Since the film is removed, the voids exposed on the surface of the interlayer insulating film can be covered with the reaction product film. As a result, diffusion of the barrier metal and copper into the pores can be easily prevented, and a semiconductor device having excellent electrical characteristics can be manufactured.

  Furthermore, according to the present invention, a reaction product film of carbon and fluorine is formed on the side wall portion of the interlayer insulating film together with the formation of the via hole and the wiring trench, and the first reaction is performed under the condition that the reaction product film is not completely removed. Since the resist film and the second resist film are removed, the voids exposed on the surface of the interlayer insulating film can be covered with the reaction product film. As a result, diffusion of the barrier metal and copper into the pores can be easily prevented, and a semiconductor device having excellent electrical characteristics can be manufactured.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  1 to 10 are cross-sectional views showing a method for manufacturing a semiconductor device in the present embodiment. In these drawings, the same reference numerals indicate the same parts.

  First, a diffusion prevention film 3 and an interlayer insulating film 4 are formed in this order on a semiconductor substrate 2 on which a copper wiring layer 1 as a lower layer wiring is formed (FIG. 1). Here, the copper wiring layer 1 has a barrier metal film 5 and a copper layer 6. In the present embodiment, a conductive layer other than the copper wiring layer may be formed. For example, a wiring layer of metal other than copper or an impurity doping region may be formed on the semiconductor substrate.

  As the semiconductor substrate 2, for example, a silicon substrate can be used.

  As the diffusion prevention film 3, for example, a SiN (silicon nitride) film, a SiC (silicon carbide) film, a SiCN (silicon carbonitride) film, or the like can be used. In the present invention, a SiC film, a SiCN film, or the like can be used. It is preferable to use a film made of a material containing carbon (C). In the case where a material having a high etching selectivity with respect to the interlayer insulating film 4 is used as the diffusion preventing film 3, the diffusion preventing film 3 also functions as an etching stopper film.

  As the interlayer insulating film 4, a porous low dielectric constant insulating film (hereinafter referred to as a Low-k film) having a relative dielectric constant of less than 3.0 is used. Here, the method of making the insulating film porous is as follows. (1) After applying an insulating film composition to which an appropriate hole forming material is added on a support, the hole forming material is removed by heat treatment or plasma treatment. , A method of introducing vacancies inside the film, and (2) an insulating film composition not containing a vacancy-forming material is applied on a support, and vacancies are formed in a self-forming manner in the course of a polymerization reaction by heat treatment Either method may be used.

  Examples of the low-k film applied to the interlayer insulating film 4 include siloxane-based inorganic materials and organic polymer-based organic materials. For example, silicon oxycarbide (Carbon Doped Silicon Oxide, SiOC) in which methyl group is introduced into silicon oxide, polyallyl ether derivative, fluorinated arylene, PSG (phosphorus-containing silicate glass), BPSG (boron-phosphorus-containing silicate) SiLK (registered glass), USG (undoped silicate glass), FSG (fluorine doped silicate glass), PE-TEOS (Plasma Enhanced-tetra Ethyl Silicon Silicate) or Dow Chemical Co., Ltd. Trademark) or the like. Further, an SOG (Spin on Glass) film such as HSQ (hydrogen silsesquioxane) or MSQ (methyl silsesquioxane) may be used. These films can be formed by CVD, SOD (Spin on Dielectric Coating), or the like.

In the present embodiment, a cap film (not shown) may be formed on the interlayer insulating film 4. As the cap film, for example, a SiO ₂ (silicon dioxide) film, a SiC (silicon carbide) film, or a SiN (silicon nitride) film can be used. In the present invention, carbon (C) such as a SiC film is used. It is preferable to use a film made of a material containing the same. These films can be formed by, for example, a CVD (Chemical Vapor Deposition) method.

  After the interlayer insulating film 4 is formed, a first resist film 7 having a predetermined pattern is formed (FIG. 2). Specifically, a photoresist (not shown) is applied to the entire surface of the interlayer insulating film 4, and is developed after being irradiated with exposure light through a mask having a predetermined pattern. Thus, the first resist film 7 can be formed by patterning the photoresist.

The type of exposure light can be appropriately selected according to the design rules of the semiconductor device. For example, KrF (krypton fluoride) excimer laser (wavelength: 248 nm) is used in the design rule of 0.25 μm to 0.13 μm, and ArF (argon fluoride) excimer laser (wavelength: 193 nm) is used in the design rule of 90 nm. In the design rule of 65 nm or less, an F ₂ laser (wavelength: 157 nm) is used as the light source of the exposure apparatus.

  In the present embodiment, the first resist film 7 may be formed after an antireflection film (not shown) is provided on the interlayer insulating film 4. The antireflection film serves to eliminate reflection of exposure light at the interface between the photoresist and the antireflection film by absorbing exposure light transmitted through the photoresist when patterning the photoresist. As the antireflection film, a film containing an organic substance as a main component can be used. For example, the antireflection film can be formed by a spin coating method or the like.

Next, first dry etching is performed on the interlayer insulating film 4 and the diffusion prevention film 3 using the first resist film 7 as a mask. For the first dry etching, a gas containing fluorine and carbon is used. For example, CHF ₃ (trifluoromethane), CH ₂ F ₂ (difluoromethane), C ₅ F ₈ (octafluorocyclopentene), CF ₄ (tetrafluoromethane), C ₄ F ₈ (octafluorocyclobutane), C ₅ F ₈ Fluorocarbon-based gases such as (octafluorocyclopentene), C ₂ F ₆ (hexafluoroethane), C ₄ F ₆ (hexafluorobutadiene), or C ₆ F ₆ (hexafluorobenzene) can be used. However, in the case where a film made of a material containing carbon is used for at least one of the diffusion prevention film and the cap film, the gas used for the first dry etching may contain fluorine and does not necessarily contain carbon. There is no need to be.

  As the first dry etching proceeds, a first opening 8 is formed, and a carbon and fluorine reaction product film 9 is formed in the interlayer insulating film 4 exposed from the first opening 8. (Figure 3). The reactive film 9 is a film made of a reaction product of fluorine and carbon in an etching gas.

  When a film made of a material containing carbon is used for either the diffusion prevention film or the cap film, the reaction product film 9 is a reaction product of fluorine in the etching gas and carbon in these films. It may be. Further, when the interlayer insulating film 4 is made of a film containing carbon, the reaction product film 9 may be a reaction product of carbon in the interlayer insulating film 4 and fluorine in the etching gas. For example, when an LKD (trade name, manufactured by JSR Corporation) film, which is an MSQ-based coating film material, is used as a Low-k film, the Si—O—C skeleton that is the base material of the LKD film and the etching gas By reaction with fluorine, a reaction product film containing carbon and fluorine is formed on the side wall of the LKD film. In this case, by changing the conditions of the first dry etching, the composition of the reaction product film may include silicon, oxygen, or the like in addition to carbon and fluorine.

  After the completion of the first dry etching, a via hole 10 is formed as an opening reaching the copper wiring layer 1 as shown in FIG. Here, the interlayer insulating film 4 exposed from the via hole 10 is covered with the reaction product film 9.

  Next, the unnecessary first resist film 7 is removed. Here, the removal of the resist film is generally performed by ashing and subsequent cleaning treatment. At this time, the reaction product film 9 is also removed together with the first resist film 7, but the reaction product film 9 is made into a thin film by weakening the conditions of ashing or cleaning treatment or omitting the cleaning treatment. It is possible to leave. The present invention is characterized in that the reaction product film 9 is left to cover the voids (not shown) exposed on the surface of the interlayer insulating film 4 with the reaction product film 9 (FIG. 5). That is, generally, the diameter of the holes is about 1 nm to 10 nm. On the other hand, it has been found that the reaction product film 9 has a molecular radius of 2 nm or more. Therefore, according to the present invention, it is possible to completely fill (or cover) the exposed holes with the reaction product film 9.

  Here, the reaction product film 9 is a film containing carbon and fluorine as described above. Since such a film has a low relative dielectric constant, even if it adheres to the side wall portion of the interlayer insulating film 4, the overall relative dielectric constant does not increase greatly. Then, the reaction product film 9 is provided as an intermediate film containing carbon and fluorine between the interlayer insulation film 4 and a barrier metal film (to be formed later), and the interlayer insulation is performed by molecules constituting the reaction product film 9. By filling the holes exposed on the surface of the film 4, it is possible to prevent the barrier metal from diffusing into the holes. Therefore, according to the present invention, it is possible to easily provide a semiconductor device having excellent electrical characteristics.

Ashing is preferably performed in a reducing atmosphere in order to reduce damage to the interlayer insulating film 4 and to leave the reaction product film 9. Specifically, H ₂ (hydrogen) gas or inert gas such as N ₂ (nitrogen), He (helium), Ne (neon) and Ar (argon) is used by using one or more kinds. Can do. Also, the H ₂ gas may be performed using one or more of the mixed gas and an inert gas.

  The weaker the conditions for ashing and cleaning treatment, the thicker the remaining reaction product film 9 becomes, and the holes can be effectively covered. However, on the other hand, the first resist film 7 also tends to remain. In the present invention, the thickness of the reaction product film 9 is preferably in the range of 1 nm to 15 nm. When the film thickness of the reaction product film 9 is thinner than 1 nm, the coverage of the holes becomes insufficient. On the other hand, if the thickness of the reaction product film 9 is greater than 15 nm, the first resist film 7 tends to remain.

  After the via hole 10 is formed by the above process, a wiring groove is similarly formed using the photolithography method.

  Specifically, a second resist film 11 having a predetermined pattern is formed on the interlayer insulating film 4 (FIG. 6). The second resist film 11 may be formed after providing an antireflection film (not shown) on the interlayer insulating film 4.

Next, second dry etching is performed on the interlayer insulating film 4 using the second resist film 11 as a mask. Similarly to the first dry etching, the second dry etching is performed using a gas containing fluorine and carbon. For example, CHF ₃ (trifluoromethane), CH ₂ F ₂ (difluoromethane), C ₅ F ₈ (octafluorocyclopentene), CF ₄ (tetrafluoromethane), C ₄ F ₈ (octafluorocyclobutane), C ₅ F ₈ Fluorocarbon-based gases such as (octafluorocyclopentene), C ₂ F ₆ (hexafluoroethane), C ₄ F ₆ (hexafluorobutadiene), or C ₆ F ₆ (hexafluorobenzene) can be used. However, in the case where a film made of a material containing carbon is used for at least one of the diffusion prevention film and the cap film, the gas used for the second dry etching may contain fluorine and does not necessarily contain carbon. There is no need to be.

  As the second dry etching proceeds, a second opening 12 is formed, and a reaction product film 9 of carbon and fluorine is formed in the interlayer insulating film 4 exposed from the second opening 12. (FIG. 7). Then, after the second dry etching is completed, a wiring groove 13 connected to the via hole 10 is formed (FIG. 8). Here, the interlayer insulating film 4 exposed from the wiring trench 13 is covered with the reaction product film 9. The wiring trench 13 can also be expressed as an opening reaching the copper wiring layer 1 through the via hole 10.

  Next, the unnecessary second resist film 11 is removed. Also in this case, the reaction product film 9 is left as a thin film by adjusting the conditions. Specifically, ashing under a reducing atmosphere or ashing under a reducing atmosphere and subsequent cleaning treatment are performed under the condition that the reaction product film 9 is not completely removed. Thus, the voids exposed on the surface of the interlayer insulating film 4 can be covered with the reaction product film 9 (FIG. 9). The film thickness of the reaction product film 9 is preferably in the range of 1 nm to 15 nm.

  Subsequently, after a barrier metal film 14 and a seed copper film 15 are formed on the inner surfaces of the via hole 10 and the wiring groove 13, a copper layer 16 is embedded therein, thereby forming a via plug 17 and a copper wiring layer 18. (FIG. 10). Specifically, this step can be performed as follows.

  First, after a barrier metal film 14 is formed on the entire surface including the via hole 10 and the wiring trench 13, a seed copper film 15 is formed. These films can be formed by a sputtering method.

  As the barrier metal film 14, for example, a tantalum (Ta) film, a tantalum nitride (TaN) film, a tungsten (W) film, a tungsten nitride (WN) film, a titanium (Ti) film, or a titanium nitride (TiN) film is used. be able to.

  After the seed copper film 15 is formed, the copper layer 16 is formed so as to fill the via hole 10 and the wiring groove 13 by plating. Here, the copper layer 16 may be a layer made only of copper, but may be a layer made of an alloy of copper and another metal. Specifically, copper is contained in an amount of 80% by weight or more, preferably 90% by weight or more. Other metals include magnesium (Mg), scandium (Sc), zirconium (Zr), hafnium (Hf), niobium (Nb), and tantalum. A material containing (Ta), chromium (Cr), molybdenum (Mo), or the like can be used. Thus, by using a copper alloy for the wiring layer, it becomes possible to improve the electrical reliability of the semiconductor device.

  After the copper layer 16 is formed, the heat treatment is performed to grow copper grains and to uniformly fill the via holes 10 and the wiring grooves 13 with copper. Thereafter, the surface is flattened by a CMP (Chemical Mechanical Polishing) method, and the copper layer 16, the seed copper film 15 and the barrier metal film 14 are removed except for the inside of the via hole 10 and the wiring trench 13.

  Through the above steps, the via plug 17 and the copper wiring layer 18 as the groove wiring can be formed on the semiconductor substrate 2 having the copper wiring layer 1 (FIG. 10). Here, the copper wiring layer 18 is electrically connected to the copper wiring layer 1 through the via plug 17.

  A multilayer wiring structure can be obtained by repeatedly performing the above-described via plug and groove wiring formation processes. According to the present invention, since the reaction product film (intermediate film) containing carbon and fluorine is formed between the interlayer insulating film and the barrier metal film, diffusion of the barrier metal and copper into the vacancies is prevented. be able to. Therefore, a semiconductor device with excellent electrical characteristics can be manufactured.

It is sectional drawing which shows the manufacturing process of the semiconductor device in this Embodiment. It is sectional drawing which shows the manufacturing process of the semiconductor device in this Embodiment. It is sectional drawing which shows the manufacturing process of the semiconductor device in this Embodiment. It is sectional drawing which shows the manufacturing process of the semiconductor device in this Embodiment. It is sectional drawing which shows the manufacturing process of the semiconductor device in this Embodiment. It is sectional drawing which shows the manufacturing process of the semiconductor device in this Embodiment. It is sectional drawing which shows the manufacturing process of the semiconductor device in this Embodiment. It is sectional drawing which shows the manufacturing process of the semiconductor device in this Embodiment. It is sectional drawing which shows the manufacturing process of the semiconductor device in this Embodiment. It is sectional drawing which shows the manufacturing process of the semiconductor device in this Embodiment. It is sectional drawing of the conventional semiconductor device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1,18 Copper wiring layer 2 Semiconductor substrate 3,24 Diffusion prevention film 4 Interlayer insulating film 5,14 Barrier metal film 6, 16, 22, 30 Copper layer 7 First resist film 8 First opening 9 Reaction product film DESCRIPTION OF SYMBOLS 10, 26 Via hole 11 2nd resist film 12 2nd opening part 13, 27 Wiring groove | channel 15, 29 Seed copper film 17 Via plug 21, 28 Barrier metal film 23 Lower layer wiring 25 Low-k film 31 Barrier metal diffusion region 32 Copper Diffusion area

Claims (13)

A diffusion preventive film provided on a lower wiring; a porous interlayer insulating film having a relative dielectric constant less than 3.0 provided on the diffusion preventive film; and the diffusion preventive film and the interlayer insulating film A semiconductor device having a copper wiring embedded through a barrier metal film in the formed opening,
A semiconductor device, wherein an intermediate film containing carbon and fluorine is formed between the interlayer insulating film and the barrier metal film.   The semiconductor device according to claim 1, wherein the diffusion prevention film is made of a material containing carbon.   The semiconductor device according to claim 1, wherein a cap film made of a material containing carbon is further provided on the interlayer insulating film.   The semiconductor device according to claim 1, wherein the intermediate film is an insulating film, and the thickness of the insulating film is in a range of 1 nm to 15 nm.   The semiconductor device according to claim 1, wherein the interlayer insulating film is one of a siloxane-based inorganic material and an organic polymer-based organic material. In a method for manufacturing a semiconductor device having a multilayer wiring structure,
Forming a porous interlayer insulating film having a relative dielectric constant of less than 3.0 above the semiconductor substrate on which the lower layer wiring is formed;
The interlayer insulating film is subjected to dry etching using a resist film processed into a predetermined pattern as a mask and using a fluorocarbon-based gas to form an opening reaching the lower layer wiring, and a side wall of the interlayer insulating film Forming a carbon and fluorine reaction product film on the part;
Removing the resist film under conditions that do not completely remove the reaction product film;
Forming a barrier metal film on the inner surface of the opening;
And a step of forming a copper layer so as to fill the opening through the barrier metal film.   The method of manufacturing a semiconductor device according to claim 6, wherein the opening is one of a via hole and a wiring groove.   8. The method of manufacturing a semiconductor device according to claim 6, wherein the step of removing the resist film is an ashing step under a reducing atmosphere.   8. The method of manufacturing a semiconductor device according to claim 6, wherein the step of removing the resist film is an ashing step in a reducing atmosphere and a cleaning step subsequent to the ashing step.   The method for manufacturing a semiconductor device according to claim 6, wherein the film thickness of the reaction product film after removing the resist film is in a range of 1 nm to 15 nm. In a method for manufacturing a semiconductor device having a multilayer wiring structure,
Forming a diffusion barrier film on the lower wiring;
Forming a porous interlayer insulating film having a relative dielectric constant of less than 3.0 on the diffusion preventing film;
A step of forming a via hole reaching the lower layer wiring by performing dry etching on the interlayer insulating film and the diffusion prevention layer using the first resist film processed into a predetermined pattern as a mask and using a fluorocarbon-based gas When,
Removing the first resist film;
Using the second resist film processed into a predetermined pattern as a mask and using a fluorocarbon-based gas to dry-etch the interlayer insulating film to form a wiring groove connected to the via hole;
Removing the second resist film;
Forming a barrier metal film on the inner surface of the via hole and the wiring groove;
Forming a copper layer so as to fill the via hole and the wiring groove through the barrier metal film,
The step of forming the via hole and the step of forming the wiring groove are also a step of forming a reaction product film of carbon and fluorine on the side wall portion of the interlayer insulating film,
The method of manufacturing a semiconductor device, wherein the step of removing the first resist film and the step of removing the second resist film are performed under conditions that do not completely remove the reaction product film.   The method of manufacturing a semiconductor device according to claim 11, wherein a film thickness of the reaction product film after the removal of the first resist film and the second resist film is in a range of 1 nm to 15 nm. The fluorocarbon-based gas is at least one gas selected from the group consisting of CHF ₃ gas, CH ₂ F ₂ gas, C ₅ F ₈ gas, CF ₄ gas, and C ₄ F ₈ gas. The manufacturing method of the semiconductor device of description.

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