JP2009026866A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To uniformly form a non-porous protection insulating film on a side wall of a wiring trench or a via hole in a semiconductor device and its manufacturing method. <P>SOLUTION: The semiconductor device has a semiconductor substrate, a first insulating film 3 including a hole, which is formed on the semiconductor substrate, a recess 4 formed in the first insulating film 3, a second insulating film 5 formed on a side wall of the recess 4 and a conductor 7 embedded in the recess 4 through the second insulating film 5. In an interface between the first insulating film 3 and the second insulating film 5, a ratio that a material constituting the second insulating film 5 is chemically coupled with a principal chain is made higher than a ratio that bond on a surface of the first insulating film 3 is terminated by a functional group. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to form a metal barrier layer and a low-k dielectric when forming a single damascene or dual damascene type buried via and / or buried wiring layer. The present invention relates to a semiconductor device characterized by a structure for forming a high-density thin-film protective insulating film therebetween and a manufacturing method thereof.

Conventionally, aluminum has been widely used as an electrode material and wiring material for semiconductor devices. However, in response to recent demands for miniaturization of semiconductor devices and higher processing speeds, the formation of electrodes and wiring should be handled with aluminum. Is getting harder.
Therefore, an attempt is being made to use copper, which is resistant to electromigration and has a specific resistance smaller than that of aluminum, as a next-generation material for aluminum.

  When copper is used as the electrode material or wiring material, copper is a material that is difficult to selectively etch, so the electrodes and wiring are formed as embedded electrodes or embedded wiring by the damascene method. By increasing the aspect ratio of the electrodes and wirings to be formed, it becomes possible to realize miniaturization and higher speed of the semiconductor device.

  On the other hand, in order to increase the speed of semiconductor devices, it is necessary to reduce the dielectric constant of the interlayer insulating film in order to reduce the parasitic capacitance as well as the resistance of the wiring and electrodes. Attempts have been made to employ low dielectric constant organic insulating materials such as ether (for example, Dow Chemical Company registered trademark SiLK) and porous silica (for example, see Patent Document 1).

  However, when a buried wiring layer is formed by using such a low-k film, particularly a porous insulating film such as porous silica, as an interlayer insulating film, migration caused by pores in the porous insulating film, etc. In order to prevent this, a non-porous protective insulating film is provided on the side wall of the trench or via hole provided in the porous insulating film (see, for example, Patent Document 2). I will explain.

See FIG.
Here, only the dual damascene process will be described.
First, after forming an element on a silicon substrate, a W plug connected to the element is formed, and then SiOC is deposited using a plasma CVD method, and then a wiring trench is formed so as to expose the W plug, Next, Cu is buried through the barrier film, and unnecessary portions are removed by a CMP method, thereby forming the lower buried wiring 61.

  Next, the plasma CVD method is used to form a SiCN film 62 having a thickness of, for example, 50 nm, a via forming insulating film 63 made of porous silica having a thickness of, for example, 150 nm, and a SiCN film 64 having a thickness of, for example, 50 nm. Then, a trench insulating film 65 made of porous silica having a thickness of, for example, 250 nm, and a SiCN film 66 having a thickness of, for example, 50 nm are sequentially deposited.

  Next, a recess 68 reaching the SiCN film 64 is formed by plasma etching using a fluorocarbon-based etching gas with the resist pattern 67 as a mask.

  Next, after removing the resist pattern 67, a new resist pattern 69 is provided, and a wiring trench 70 is formed in the trench insulating film 65 again by plasma etching using a fluorocarbon-based etching gas, and also for via formation. A via hole 71 reaching the lower buried wiring 61 is formed in the insulating film 63.

  Next, after removing the resist pattern 69, a nonporous insulating film 72 made of SiOC having a thickness of several nm is deposited on the entire surface by plasma CVD.

See FIG.
Next, by performing anisotropic etching, the nonporous insulating film 72 is left only on the side walls of the via hole 71 and the wiring trench 70, thereby forming the nonporous protective insulating film 73.

  Next, the wiring trench 70 and the via hole 71 are filled with a Cu plating film 75 through a barrier film 74 made of TaN, and unnecessary portions are removed by CMP to bury the wiring made of a Cu via plug 77 and a Cu upper layer buried wiring 78. A conductor 76 is formed.

Thereafter, the semiconductor device is completed by repeating an interlayer insulating film deposition process, a wiring trench and via hole forming process, and a via and buried wiring forming process according to the required number of multilayer wiring layers.
JP 2004-071705 A JP 2005-236285 A

  However, with the miniaturization of wiring and the complexity of patterns, it has become difficult to uniformly form a nonporous protective insulating film on the side wall in a buried wiring structure using a porous insulating film. There is a problem that defects occur in the quality protective insulating film.

  For this reason, a metal component such as Cu used for the barrier metal or the wiring material is diffused into the porous insulating film through this defect, causing an increase in resistance and a short circuit between the wirings.

  Accordingly, an object of the present invention is to uniformly form a nonporous protective insulating film on the sidewalls of wiring trenches or via holes.

FIG. 1 is a diagram illustrating the basic configuration of the present invention. Means for solving the problems in the present invention will be described with reference to FIG.
In order to solve the above-described problem, the present invention is formed in a semiconductor device, a semiconductor substrate, a first insulating film 3 containing vacancies formed on the semiconductor substrate, and the first insulating film 3. And a second insulating film 5 formed on the side wall of the concave portion 4 and a conductor 7 embedded in the concave portion 4 through the second insulating film 5, and the first insulating film 3 and the second insulating film. The ratio of chemically bonding to the main chain of the material constituting the second insulating film 5 is higher than the ratio of bonding of the surface of the first insulating film 3 to the functional group at the interface with the film 5. It is characterized by.

  The surface of the interlayer insulating film 2 in a normal state is terminated with a functional group derived from a manufacturing raw material such as a precursor of the interlayer insulating film 2 or an atmosphere, particularly a methyl group, and this functional group causes the first. The adhesion between the insulating film 3 and the second insulating film 5 is poor, the coverage is reduced, and the uniformity of the second insulating film 5 at the side wall portion is reduced. By chemically bonding the bond on the surface with the main chain of the material constituting the second insulating film 5, the coverage can be improved and the uniformity of the second insulating film 5 in the side wall portion can be improved. The diffusion of the metal component can be prevented.

In this case, the second insulating film 5 is preferably SiOC, and particularly preferably has an initial dielectric constant of 2.5 to 4.5 and a density of 1.5 to 2.5 g / cm ³ .
In addition, it is difficult to form an insulating film having an initial dielectric constant of less than 2.5 with a non-porous structure. On the other hand, when the initial dielectric constant exceeds 4.5, the meaning of adopting a low-k film is reduced.
In addition, it is difficult to form an insulating film having a density of less than 1.5 with a non-porous structure. On the other hand, if the density exceeds 2.5, it cannot be said to be a low-k film.

  The film thickness of the second insulating film 5 is preferably 0.5 to 5 nm. If the thickness is less than 0.5 nm, voids are likely to occur. If the thickness exceeds 5 nm, a fine via hole or a fine buried wiring is formed. It becomes difficult to form.

  Also, the vacancy-containing deposition ratio in the first insulating film 3 is preferably 30 to 50%, and if it is less than 30%, it is difficult to realize an ultra-low-k film having a dielectric constant of 2.3 or less. If it exceeds 50%, the mechanical strength of the first insulating film 3 is lowered, and it becomes difficult to support the wiring structure.

  Further, as a material constituting the portion of the conductor 7 excluding the barrier metal layer, Cu, Al, W, or an alloy of each material is suitable, and in particular, the embedded conductor 8 constituting the upper layer wiring. As Cu, Cu or Cu alloy is preferable.

  Further, according to the present invention, in the method of manufacturing a semiconductor device, a step of depositing an interlayer insulating film 2 having at least a part of a porous insulating film containing pores on a semiconductor substrate, and a recess 4 in the interlayer insulating film 2 are provided. A step of forming, a step of depositing a second insulating film 5 different from the material constituting the porous insulating film on the entire surface while irradiating light 6 having a wavelength of 150 to 500 nm, and a conductor material in the recess 4 And an embedding step.

  As described above, when the second insulating film 5 is formed, by depositing light 6 having a wavelength of 150 to 500 nm having energy exceeding the binding energy of a functional group, particularly a methyl group, it is deposited on the entire surface. The functional group that terminates the bond on the surface of the first insulating film 3 can be liberated, thereby improving the wettability by terminating the surface with an OH group, thereby improving the coverage of the second insulating film 5. As a result, the ratio of chemically bonding to the main chain of the material constituting the second insulating film 5 becomes higher than the ratio of bonding of the surface of the first insulating film 3 to the functional group.

  Further, in the step of forming the second insulating film 5, the light 6 to be irradiated may be light having a plurality of wavelengths, and damage to the insulating film is reduced as compared with the case of irradiating a single wavelength with a high energy density. Can do.

  Further, the interlayer insulating film 2 includes an etching stopper film 8 formed on the semiconductor substrate, a first insulating film 3 formed on the etching stopper film 8, and an etching mask film formed on the first insulating film 3. In this case, the conductor 7 forms one of a via plug or a wiring layer.

  In this case, in the step of forming the recess 4 in the interlayer insulating film 2, a metal hard mask may be provided on the etching mask film, and the light 6 does not pass through the metal hard film. Therefore, the step of forming the second insulating film 5. In this case, the light 6 to be irradiated does not enter the inside of the first insulating film 3 to release the methyl group and bind to the hydrophilic OH group, and the increase in the dielectric constant due to the moisture ingress can be suppressed.

  Alternatively, the interlayer insulating film 2 includes a first etching stopper film formed on the semiconductor substrate, a first insulating film 3 formed on the first etching stopper film, and a first etching film formed on the first insulating film 3. 2 etching stopper film, a third insulating film having a hole formed on the second etching stopper film, and an etching mask film formed on the third insulating film, and in that case The conductor 7 constitutes a via plug and a wiring layer.

  In this case, in the step of forming the recess 4 in the interlayer insulating film 2, an inorganic material hard mask is provided on the etching mask film, and the fine mask reaching the second etching stopper film is formed using the hard mask formed by patterning the etching mask film as a mask. After forming the recess, the exposed portion of the second etching stopper film is removed to form a second hard mask, and then an embedded wiring trench reaching the second etching stopper film is formed using the inorganic material hard mask as a mask. At the same time, a via hole corresponding to the fine recess may be formed while reaching the first etching stopper film using the second hard mask as a mask.

  Also in this case, by using an inorganic material hard mask as a metal hard mask, the light 6 irradiated in the step of forming the second insulating film 5 enters the inside of the first insulating film 3 and releases the methyl group to make it hydrophilic. Since it does not bind to the OH group, increase in dielectric constant due to moisture ingress can be suppressed.

  In the present invention, when the nonporous protective insulating film is formed on the sidewall of the wiring trench and / or via hole formed in the interlayer insulating film including the porous insulating film, light having a wavelength of 150 to 500 nm, typically Since the film is formed by irradiating with ultraviolet rays, the methyl group that terminates the surface of the porous insulating film is liberated to increase the hydrophilicity, and thereby the uniformity of the film thickness of the nonporous protective insulating film and Since adhesion can be improved, migration of the metal constituting the embedded conductor can be suppressed.

In the present invention, after forming a lower layer conductor via a base insulating film on a semiconductor substrate on which an element is formed, a porous insulating film containing a lower layer insulating film and voids on the lower layer conductor, typically a void An interlayer insulating film having at least a portion of a porous insulating film containing 30 to 50% is deposited, and then an interlayer insulating film that forms at least one of a via hole or a buried wiring trench is formed on the interlayer insulating film After the formation of the concave portion reaching, the non-porous insulating film is different from the material constituting the porous insulating film. Typically, the initial dielectric constant is 2.5 to 4.5 and the density is 1.5 to 2. 5 g / cm ³ of SiOC is deposited on the entire surface to a thickness of 0.5 to 5 nm while irradiating light with a wavelength of 150 to 500 nm, for example, 185 nm of ultraviolet rays, and then non-porous insulating film by anisotropic etching On the side wall of the recess. After forming the non-porous protective insulating film and removing the exposed portion of the lower insulating film to form the concave portion reaching the lower conductor, Cu, Al, W, or the like through the barrier metal film such as TaN in the concave portion An embedded conductor constituting at least one of a via plug or a wiring layer is formed by embedding a conductor material made of any of the alloys of the respective materials.

  In the case of a single damascene process, in each of the via plug formation process and the buried wiring layer formation process, as an interlayer insulation film, a lower insulation film serving as an etching stopper and a porous insulation formed on the lower insulation film A film and an upper insulating film serving as a hard mask formed on the porous insulating film are sequentially deposited.

  On the other hand, in the case of the dual damascene process, an interlayer insulating film is formed on the lower insulating film serving as an etching stopper, the first porous insulating film formed on the lower insulating film, and the first porous insulating film. An intermediate insulating film serving as an etching stopper, a second porous insulating film formed on the intermediate insulating film, and an upper insulating film serving as a hard mask formed on the second porous insulating film The via plug and the wiring layer are formed simultaneously.

  In any process, a metal hard mask may be provided on the uppermost layer, and by using the metal hard mask, the incidence of ultraviolet rays is completely blocked, and the destruction of the porous insulating film is completely suppressed. Only the side walls may be treated.

Next, the single damascene process according to the first embodiment of the present invention will be described with reference to FIGS. 2 to 6. First, with reference to FIG. 2, the formation of a nonporous insulating film used in the practice of the present invention will be described. The membrane device will be described.
See Figure 2
FIG. 2 is a conceptual configuration diagram of a nonporous insulating film forming apparatus. The film forming apparatus 10 includes a chamber 11 having an exhaust port 12 and a chiller on which a wafer 14 accommodated in the chamber 11 is placed. A stage 13 equipped with a temperature control device, a blister 17 for discharging a non-porous insulating film, for example, a head 15 having a quartz nozzle 16 in the center, and a recess in the head 15 The light source lamp 18 and the quartz cover 19 that covers the light source lamp 18 are configured.

  The light source lamp 18 in this case is composed of, for example, a low-pressure mercury lamp or a xenon excimer lamp, and irradiates light having a wavelength of 150 to 500 nm, for example, ultraviolet light having a wavelength of 185 nm or 254 nm, and the ultraviolet light is absorbed by the quartz cover 19. The wafer 14 is irradiated without being irradiated.

Next, the single damascene process according to the first embodiment of the present invention will be described with reference to FIGS. 3 to 6. Here, only the buried conductor forming process will be described in order to simplify the description.
See Figure 3
First, after forming an element on a silicon substrate, a W plug connected to the element is formed, and then SiOC is deposited using a plasma CVD method, and then a wiring trench is formed so as to expose the W plug, Next, Cu is embedded through the barrier film, and unnecessary portions are removed by CMP to form the lower buried wiring 21.

Next, after the SiC film 22 having a thickness of, for example, 25 nm and a relative dielectric constant of about 3.5 is formed as a first etching stopper layer, the relative dielectric constant is about 2.2 using a spin-on coating method. Then, a p-MSQ (Porous Methyl Silsesquioxane) film 23 having a thickness of, for example, 150 nm is formed.
In this case, the vacancy-containing deposition ratio in the p-MSQ film 23 is 20 to 50%, for example, 30%. It is controlled by the content of the template as the main component, and thereby the relative dielectric constant is defined.
However, the template-containing type p-MSQ requires a separate step of removing the template after film formation.

Next, on the p-MSQ film 23, a SiOC film 24 having a relative dielectric constant of 2 to 3 and a thickness of, for example, 100 nm is deposited by CVD.
The effective relative dielectric constant of the entire first interlayer insulating film composed of the SiC film 22 / p-MSQ film 23 / SiOC film 24 thus deposited is about 2.5 to 3.0.

Next, using the resist mask 25 having the opening pattern 26 of the via hole as an etching mask, the SiOC film 24 and the p-MSQ film 23 are sequentially dry etched by RIE (reactive ion etching), and the via hole 27 having a diameter of, for example, 80 nm is cross-sectionalized. The side wall is processed to be 90 to 120 °, for example, 95 °.
Here, the SiC film 22 serving as the first etching stopper layer is left unetched.

Next, after removing the resist mask 25 with plasma such as H ₂ gas or He gas, the film thickness at the side wall is set to 0. 0 by plasma CVD method (PE-CVD method) using the film forming apparatus shown in FIG. A first nonporous insulating film 28 made of SiOC is deposited on the entire surface so as to be 5 to 5 nm, for example, 3 nm.
In this case, a first non-porous insulating film 28 having a thickness less than that on the SiC film 22 and a thickness greater than that is deposited on the SiOC film 24.

In this case, for example, a precursor of SiOC, tetramethylcyclotetrasiloxane, and octamethylcyclotetrasiloxane is used as the precursor, and the film is formed at a substrate temperature of 400 ° C. under a pressure of 500 Pa. During the film forming process, for example, the ultraviolet ray 29 having a wavelength of 185 nm (= 6.7 eV) is irradiated, and the ultraviolet ray 29 having a wavelength of 185 nm (= 6.7 eV) has an energy exceeding the binding energy of a functional group, particularly a methyl group. Therefore, the functional group that terminates the bond on the surface of the SiC film 22 / p-MSQ film 23 / SiOC film 24 is released.
In this case, the irradiation energy density of the ultraviolet rays 29 is, for example, 500 mJ / cm ² .

  Since the surface from which the functional group is liberated terminates with an OH group and wettability is improved, the coverage of the first nonporous insulating film 28 is improved and the surface of the SiC film 22 / p-MSQ film 23 / SiOC film 24 is improved. The bond is chemically bonded to the main chain of SiOC constituting the first nonporous insulating film 28.

Next, the first nonporous material deposited on the main surfaces of the SiC film 22 and the SiOC film 24 by performing anisotropic etching by highly anisotropic RIE using a mixed gas composed of fluorine compound gas and nitrogen gas. The insulating film 28 is removed to form the first nonporous protective insulating film 30 only on the side wall portion of the via hole 27, and the exposed portion of the SiC film 22 is also removed so that the via hole 27 reaches the lower buried wiring 21. To penetrate.
At this time, the film thickness of the first nonporous protective insulating film 30 is about 2 nm.

See Figure 4
Next, a TaN film 31 with a thickness of, for example, 15 nm as a barrier material and a Cu seed (not shown) with a thickness of, for example, 50 nm are deposited by sputtering (PVD), and further plated as a wiring material. A Cu film 32 having a film thickness of 300 nm to 500 nm is formed using a method.
In the figure, the Cu seed and the Cu film 32 are collectively shown as a Cu film 32.

Next, by using a CMP (Chemical Mechanical Polishing) method, unnecessary portions of the Cu film 32 and the TaN film 31 on the SiOC film 24 are polished and removed, and the via plug 34 is inserted into the via hole 27 via the first barrier layer 33. Form.
At this time, the SiOC film 24 becomes a polishing stopper.

Next, again, the thickness of the second etching stopper film on the entire surface is, for example, a SiC film 35 with a thickness of 25 nm, a p-MSQ film 36 with a relative dielectric constant of about 2.0 and a thickness of, for example, 200 nm, and A SiOC film 37 having a thickness of 100 nm, for example, is sequentially deposited as the second cap layer.
The effective relative dielectric constant of the entire second interlayer insulating film composed of the SiC film 35 / p-MSQ film 36 / SiOC film 37 thus deposited is about 2 to 2.5.

See Figure 5
Next, using the resist mask 38 having the trench opening pattern 39 as an etching mask, the SiOC film 37 and the p-MSQ film 36 are sequentially dry-etched by RIE, and the trench 40 having a width dimension of, for example, 100 nm has a sidewall taper angle. It forms so that it may become 90-120 degrees, for example, 95 degrees.
Here again, the SiC 35 serving as the second etching stopper layer is left unetched.

Next, after removing the resist mask 38 with plasma such as H ₂ gas or He gas, a cleaning process is performed to remove residues, and then under the same conditions as the film forming step of the first nonporous insulating film 28 described above. A second nonporous insulating film 41 made of SiOC is deposited on the entire surface.
However, in this case, the film formation time is controlled so that the film thickness on the side wall portion of the trench 40 becomes, for example, 5 nm.

See FIG.
Next, the second film deposited on the main surfaces of the SiC film 35 and the SiOC film 37 is again subjected to anisotropic etching by highly anisotropic RIE using a mixed gas composed of a fluorine compound gas and nitrogen gas. The porous insulating film 41 is removed to form the second nonporous protective insulating film 42 only on the side wall portion of the trench 40, and the exposed portion of the SiC film 35 is also removed so that the trench 40 reaches the via plug 34. To penetrate.
At this time, the thickness of the second nonporous protective insulating film 42 is about 4 nm.

Next, a TaN film 43 having a thickness of, for example, 15 nm as a barrier material and a Cu seed (not shown) having a thickness of, for example, 50 nm are deposited by sputtering (PVD), and further plated as a wiring material. A Cu film 44 having a film thickness of 300 nm to 500 nm is formed using a method.
In the figure, the Cu seed and the Cu film 44 are shown together as a Cu film 44.

Next, unnecessary portions of the Cu film 44 and the TaN film 43 on the SiOC film 37 are polished and removed by using a CMP method, and an upper buried wiring 46 is formed in the trench 40 via the second barrier layer 45. .
At this time, the SiOC film 37 serves as a polishing stopper.

  In this way, the two-layer wiring of the damascene wiring structure is completed. Thereafter, the semiconductor device is completed by repeatedly forming the two-layer wiring of the damascene wiring structure according to the required number of multilayer wiring layers. .

  In the first embodiment of the present invention, when the nonporous protective insulating film is formed on the sidewall of the trench or via hole, the film is formed by irradiating with ultraviolet rays. Therefore, the p-MSQ film which is a porous insulating film The methyl group terminating the surface of the porous insulating film containing the metal can be liberated to improve the uniformity and adhesion of the film thickness of the nonporous insulating film. Migration can be suppressed.

  Further, in the step of removing the exposed portion of the SiC film 22 or the SiC film 35 serving as an etching stopper, the sidewall of the via hole 27 or the trench 40 is protected by the first nonporous protective insulating film 30 or the first nonporous protective insulating film 42. Therefore, there is no shape deformation of the sidewall of the via hole 27 or the trench 40, no insulating film void, and no Cu void, and a fine damascene wiring structure can be formed in the semiconductor device.

  Further, by protecting the via holes 27 and the trenches 40 of the damascene structure, the occurrence of cracks due to the reduction of the mechanical strength of the interlayer insulating film including the p-MSQ film which is a porous low dielectric constant film and the damascene There will be no short circuit between wires.

  Further, the first non-porous protective insulating film 30 and the first non-porous protective insulating film 42 prevent intrusion of moisture or Cu of the wiring material film or its barrier metal such as Ta or TaN into the interlayer insulating film. In order to suppress this, the interlayer insulating film of the damascene wiring structure has high reliability, the effective dielectric constant of the interlayer insulating film does not increase, the leakage current between the wiring layers increases, and the connection failure at the via part There will be no such problems.

  Next, a single damascene process according to the second embodiment of the present invention will be described with reference to FIGS. 7 and 8. This second embodiment is made of Ta on the cap layer in each process of the first embodiment. A metal hard mask is formed and removed in the CMP process, and the other processes are the same as those in the first embodiment, so only the main part of the process will be described.

See FIG.
First, after forming an element on a silicon substrate, a W plug connected to the element is formed, and then SiOC is deposited using a plasma CVD method, and then a wiring trench is formed so as to expose the W plug, Next, Cu is embedded through the barrier film, and unnecessary portions are removed by CMP to form the lower buried wiring 21.

  Next, after forming a first interlayer insulating film composed of SiC film 22 / p-MSQ film 23 / SiOC film 24, a Ta film 47 having a thickness of, for example, 5 nm serving as a metal hard mask is deposited thereon, Using the resist mask 25 having the opening pattern 26 of the via hole as an etching mask, the Ta film 47 to the p-MSQ film 23 are sequentially dry etched by RIE to form the via hole 27.

  Next, after removing the resist mask 25, a first non-porous insulating film 28 made of SiOC is deposited on the entire surface while irradiating ultraviolet rays 29, and then anisotropic etching is performed by highly anisotropic RIE. The first nonporous protective insulating film 30 is formed only on the side wall portion of the via hole 27 and the exposed portion of the SiC film 22 is also removed to penetrate the via hole 27 so as to reach the lower buried wiring 21.

Next, after depositing a TaN film, a Cu seed, and a Cu plating film as a barrier material, unnecessary portions of the Cu film and the TaN film on the SiOC film 24 are polished and removed by using the CMP method, and via holes are formed. A via plug 34 is formed in the layer 27 via the first barrier layer 33.
At this time, the Ta film 47 provided on the SiOC film 24 is simultaneously polished and removed.

See FIG.
Next, after a second interlayer insulating film made of SiC film 35 / p-MSQ film 36 / SiOC film 37 is formed again, a Ta film having a thickness of, for example, 5 nm again serving as a metal hard mask is formed thereon. 48 is deposited.

  Next, using the resist mask having the trench opening pattern as an etching mask, the Ta film 48 to the p-MSQ film 36 are sequentially dry-etched by RIE to form the trench 40.

  Next, after removing the resist mask, a cleaning process is performed to remove residues, and then the second nonporous structure made of SiOC is formed on the entire surface under the same conditions as the film forming step of the first nonporous insulating film 28 described above. An insulating film is deposited on the entire surface, and then anisotropic etching by highly anisotropic RIE is performed to form the second nonporous protective insulating film 42 only on the side wall portion of the trench 40, and the SiC film 35 The exposed portion is also removed and the trench 40 is penetrated so as to reach the via plug 34.

Next, after a TaN film, a Cu seed, and a Cu plating film are sequentially deposited as a barrier material, unnecessary portions of the Cu film and the TaN film on the SiOC film 37 are polished and removed by using the CMP method. An upper buried wiring 46 is formed in the layer 40 via the second barrier layer 45.
At this time, the Ta film 48 is simultaneously polished and removed.

  In this way, the two-layer wiring of the damascene wiring structure is completed. Thereafter, the two-layer wiring of the damascene wiring structure is repeatedly formed according to the required number of multilayer wiring layers. The device is completed.

  In the second embodiment of the present invention, since the metal hard mask is provided on the outermost surface of each step, ultraviolet rays do not enter the interlayer insulating film except in the peripheral part of the via hole or trench. The increase in dielectric constant due to the ingress of moisture over time can be suppressed.

Next, a dual damascene process according to the third embodiment of the present invention will be described with reference to FIGS.
See FIG.
First, after forming an element on a silicon substrate, a W plug connected to the element is formed, and then SiOC is deposited using a plasma CVD method, and then a wiring trench is formed so as to expose the W plug, Next, an Al—Cu alloy is embedded through the barrier film, and unnecessary portions are removed by a CMP method to form the lower-layer embedded wiring 21.

Next, after a SiC film 22 having a thickness of, for example, 25 nm and a relative dielectric constant of about 3.5 is formed as a first etching stopper layer, the relative dielectric constant is about 1.8 using a spin-on coating method. Then, a p-MSQ film 49 having a thickness of 200 to 300 nm, for example, 250 nm is formed.
In this case, the vacancy-containing deposition ratio in the p-MSQ film 49 is, for example, 50%.

Next, after a SiOC film 50 having a relative dielectric constant of 2 to 3 and a thickness of, for example, 100 nm is formed on the p-MSQ film 49 by a CVD method, a spin-on coating method is performed again. A p-MSQ film 51 having a relative dielectric constant of about 1.8 and a thickness of, for example, 150 nm is used.
In this case, the vacancy deposition ratio in the p-MSQ film 51 is also 50%, for example.

Next, on the p-MSQ film 51, a SiOC film 24 that is a cap layer having a relative dielectric constant of 2 to 3 and a thickness of, for example, 100 nm is deposited by CVD.
The effective relative dielectric constant of the entire interlayer insulating film composed of the SiC film 22 / p-MSQ film 49 / SiOC film 50 / p-MSQ film 51 / SiOC film 24 thus deposited is about 2 to 2.5. ing.

Then, the thickness of which is a hard mask, for example, after forming the SiO ₂ film 52 of 50 nm, a width dimension corresponding to the trenches in the SiO ₂ film 52 using conventional photolithographic techniques and dry etching techniques, for example, An opening 53 having a pattern of 100 nm is provided, and an opening 54 having a diameter corresponding to a via hole of, for example, 80 nm is formed in the SiOC film 24.

Next, the p-MSQ film 51 is etched by performing RIE using a fluorocarbon-based fluorine compound gas using the SiOC film 24 as a mask, and the via pattern reaching the surface of the SiOC film 50 is transferred.

See FIG.
Next, the SiOC film 24 is etched by performing RIE using a hydrofluorocarbon-based fluorine compound gas with the SiO ₂ film 52 as a mask, and the trench pattern is transferred to the SiOC film 24. At the same time, the SiOC film 50 is also etched. Transfer the via pattern.

Next, the p-MSQ film 51 is etched by performing RIE using a fluorocarbon-based fluorine compound gas with the SiO ₂ film 52 as a mask to form the trench 40, and at the same time, the p-MSQ film with the SiOC film 50 as a mask. 49 is etched to form a via hole 27 having a taper angle of 95 °, for example.
Here again, the SiC film 22 is left unetched.

Next, a non-porous insulating film 55 made of SiO ₂ is deposited on the entire surface so that the film thickness at the side wall portion becomes, for example, 6 nm while irradiating the ultraviolet rays 29 of 185 nm using the CVD method.
In this case, a nonporous insulating film 55 having a thickness less than that on the SiC film 22 and a thickness greater than that on the SiO ₂ film 52 is deposited.

See FIG.
Next, anisotropic etching by highly anisotropic RIE using a mixed gas composed of a fluorine compound gas and nitrogen gas is performed, so that the main surfaces of the SiC film 22, the SiOC film 50, and the SiO ₂ film 52 are formed on the main surfaces. The deposited non-porous insulating film 55 is removed to form a non-porous protective insulating film 56 only on the side walls of the via hole 27 and the trench 40, and the exposed portion of the SiC film 22 is also removed to fill the via hole 27 with a lower layer. It penetrates to reach the lead-in wiring 21.
At this time, the film thickness of the nonporous protective insulating film 56 is about 5 nm.

Next, a TaN film 57 having a thickness of, for example, 15 nm as a barrier material and a Cu seed (not shown) having a thickness of, for example, 50 nm are deposited by sputtering (PVD), and further plated as a wiring material. A Cu film 58 having a thickness of, for example, 500 nm is formed by using this method.
In the figure, the Cu seed and the Cu film 58 are collectively shown as a Cu film 58.

Next, unnecessary portions of the Cu film 58 and the TaN film 57 on the SiO ₂ film 52 are polished and removed by using the CMP method, and via plugs and buried wirings are formed in the via holes 27 and the trenches 40 via the barrier layers 59. Is formed as an integrated upper layer wiring 60.
At this time, the SiO ₂ film 52 is also removed by polishing.

  In this way, a dual damascene structure buried wiring structure is completed. Thereafter, the dual damascene structure buried wiring structure is repeatedly formed according to the required number of multilayer wiring layers. This completes the semiconductor device.

  In the third embodiment of the present invention, as compared with the single damascene structure of the first embodiment, an insulating layer other than the porous low dielectric constant film, that is, an etching stopper layer or a part of the cap layer can be omitted. As a result, it is possible to further reduce the effective dielectric constant of the interlayer insulating film, thereby further increasing the operation speed of the semiconductor device.

Next, a dual damascene process according to the fourth embodiment of the present invention will be described. In the fourth embodiment, the SiO ₂ film 52 serving as the hard mask in the third embodiment is replaced with a metal hard mask made of Ta. Therefore, a specific description is omitted.

That is, in FIG. 9 described above, a Ta film is provided in place of the SiO ₂ film 52, and a trench pattern is formed in the Ta film. In FIG. 10, a trench is formed in the SiOC film 24 using the Ta film formed with the trench pattern as a mask. The pattern is transferred, and the Ta film is polished and removed simultaneously with the Cu film and the TaN film in the CMP process shown in FIG.

  Also in the fourth embodiment of the present invention, a metal hard mask is provided on the outermost surface as in the second embodiment. Therefore, in the non-porous insulating film forming step, the interlayer insulation is formed except for the peripheral portion of the via hole and the trench. Ultraviolet rays do not enter the film, thereby making it possible to prevent the interlayer insulating film from becoming hydrophilic, so that an increase in dielectric constant due to the ingress of moisture over time can be suppressed.

  Although the embodiments of the present invention have been described above, the present invention is not limited to the configurations and conditions described in the embodiments, and various modifications are possible. For example, the size of the via hole and the trench The width and the like are arbitrary, and may be appropriately determined according to the required degree of integration.

  In each of the above embodiments, the via and the embedded wiring are formed of Cu. However, the present invention is not limited to Cu, and is not limited to Cu, but also alloys such as Cu-Al and Cu-Si. Further, it is applied to metals other than Cu such as Al and Ag, or metal nitrides such as TiN and TaN.

Further, it is merely an example of a combination of the wiring insulating film and the via forming insulating film in each of the above embodiments, and it goes without saying that it can be applied to an interlayer insulating film structure using other insulating materials. An SiCN film or an SiN film may be used instead of the SiC film, and an SiO ₂ film, an SiN film, or an SiCN film may be used instead of the SiOC film serving as the cap layer.

  In each of the above embodiments, TaN is used as the barrier metal. However, the barrier metal is not limited to TaN, and a Ta film may be used. Further, a W film, a WN film, and a WSiN film may be used. A Ti film, a TiN film, or a TiSiN film may be used.

  In each of the above embodiments, a p-MSQ film is used as the low dielectric constant film having a porous structure. However, the p-MSQ film is not limited to the p-MSQ film. Other insulating films having an insulating film having an organic polymer as a main skeleton or a porous insulating film can be used.

Note that the insulating film having a siloxane skeleton includes a silica film including at least one of a Si—CH ₃ bond, a Si—H bond, and a Si—F bond, which is a silsesquioxane insulating film.
An insulating film having an organic polymer as a main skeleton includes SiLK (registered trademark) made of an organic polymer.

  Insulating materials well known as insulating films of silsesquioxanes include MSQ, Hydrogen Silsesquioxane (HSQ), and Methylated Hydrogen Silsesquioxane (MHSQ). ) Etc.

  Further, as the low dielectric constant film having a porous structure, a porous SiOCH film and a SiOC film formed by the CVD method can be used in addition to the above-mentioned coating type insulating film.

  Further, in each of the above embodiments, when depositing the nonporous insulating film for protecting the side wall, the ultraviolet ray of 185 nm is irradiated. However, it is not limited to 185 nm, and for example, 254 nm or the like Other wavelengths may be irradiated with ultraviolet rays.

  Furthermore, the ultraviolet light irradiated in the ultraviolet irradiation process does not need to have a single wavelength. For example, ultraviolet light having peaks at two wavelengths of 185 nm and 254 nm may be irradiated. The same effect as in the case of one wavelength can be expected, and the overall energy to be irradiated can be reduced, so that damage caused by irradiation can be reduced.

The detailed features of the present invention will be described again with reference to FIG. 1 again.
Again see Figure 1
(Additional remark 1) It forms in the side wall of the semiconductor substrate, the 1st insulating film 3 containing the void | hole formed on the said semiconductor substrate, the recessed part 4 formed in the said 1st insulating film 3, and the said recessed part 4 A second insulating film 5 and a conductor 7 embedded in the recess 4 via the second insulating film 5, and at the interface between the first insulating film 3 and the second insulating film 5, The ratio of chemically bonding to the main chain of the material constituting the second insulating film 5 is higher than the ratio of bonding of the surface of the first insulating film 3 to the functional group. .
(Supplementary note 2) The supplementary note 1, wherein the second insulating film 5 is made of SiOC, has an initial dielectric constant of 2.5 to 4.5, and a density of 1.5 to 2.5 g / cm ^3. Semiconductor device.
(Additional remark 3) The semiconductor device of Additional remark 1 or 2 characterized by the film thickness of the said 2nd insulating film 5 being 0.5-5 nm.
(Additional remark 4) The semiconductor device of any one of Additional remark 1 thru | or 3 characterized by the containing accumulation ratio of the void | hole in the said 1st insulating film 3 being 30 to 50%.
(Supplementary note 5) The semiconductor according to any one of supplementary notes 1 to 4, wherein the portion of the conductor 7 excluding the barrier metal layer is made of Cu, Al, W, or an alloy of each material. apparatus.
(Additional remark 6) The process of depositing the interlayer insulation film 2 which has the 1st insulation film 3 containing a void | hole at least in part on a semiconductor substrate, the process of forming the recessed part 4 in the said interlayer insulation film 2, The said 1st A step of depositing a second insulating film 5 different from the material constituting the insulating film 3 on the entire surface while irradiating light 6 having a wavelength of 150 to 500 nm; and a step of embedding a conductor material in the recess 4 A method for manufacturing a semiconductor device, comprising:
(Additional remark 7) The manufacturing method of the semiconductor device of Additional remark 6 characterized by the light 6 irradiated in the process of forming the said 2nd insulating film 5 consisting of the light of several wavelengths.
(Supplementary Note 8) The interlayer insulating film 2 includes an etching stopper film 8 formed on the semiconductor substrate, the first insulating film 3 formed on the etching stopper film 8, and the first insulating film 3. The method of manufacturing a semiconductor device according to appendix 6 or 7, wherein the method further comprises an etching mask film formed on the semiconductor device.
(Additional remark 9) The manufacturing method of the semiconductor device of Additional remark 8 characterized by providing a metal hard mask on the said etching mask film in the process of forming the recessed part 4 in the said interlayer insulation film 2. FIG.
(Supplementary Note 10) The interlayer insulating film 2 includes a first etching stopper film formed on the semiconductor substrate, the first insulating film 3 formed on the first etching stopper film, and the first insulating film. A second etching stopper film formed on the second etching stopper film, a third insulating film having holes formed on the second etching stopper film, and the etching mask film formed on the third insulating film. 8. A method for manufacturing a semiconductor device according to appendix 6 or 7, characterized by comprising:
(Supplementary Note 11) In the step of forming the recess 4 in the interlayer insulating film 2, the second etching is performed using a hard mask formed by providing an inorganic material hard mask on the etching mask film and patterning the etching mask film. After forming a fine recess reaching the stopper film, the exposed portion of the second etching stopper film is removed to form a second hard mask, and then the second etching stopper film is formed using the inorganic material hard mask as a mask. 12. The semiconductor device according to claim 10, wherein a via hole corresponding to the fine recess is formed while reaching the first etching stopper film using the second hard mask as a mask simultaneously with forming the buried wiring trench. Manufacturing method.
(Additional remark 12) The said inorganic material hard mask is a metal hard mask, The manufacturing method of the semiconductor device of Additional remark 11 characterized by the above-mentioned.
(Additional remark 13) The process of embedding a conductor material in the said recessed part 4 is a damascene process using the chemical mechanical polishing method, The said etching mask film | membrane acts as a polishing stopper in a damascene process, It is characterized by the above-mentioned. 13. A method for manufacturing a semiconductor device according to any one of items 1 to 12.

  As an application example of the present invention, a multilayer wiring structure of a highly integrated semiconductor device is typical. However, the invention is not limited to a wiring structure in a semiconductor device, and a wiring connection structure of an optical device using a ferroelectric substance. Etc. are also applicable.

It is explanatory drawing of the fundamental structure of this invention. It is a notional block diagram of the film-forming apparatus of a nonporous insulating film. It is explanatory drawing to the middle of the single damascene process of Example 1 of this invention. It is explanatory drawing to the middle after FIG. 3 of the single damascene process of Example 1 of this invention. It is explanatory drawing to the middle after FIG. 4 of the single damascene process of Example 1 of this invention. It is explanatory drawing after FIG. 5 of the single damascene process of Example 1 of this invention. It is explanatory drawing to the middle of the single damascene process of Example 2 of this invention. It is explanatory drawing after FIG. 7 of the single damascene process of Example 2 of this invention. It is explanatory drawing to the middle of the dual damascene process of Example 3 of this invention. It is explanatory drawing to the middle after FIG. 9 of the dual damascene process of Example 3 of this invention. It is explanatory drawing after FIG. 10 of the dual damascene process of Example 3 of this invention. It is explanatory drawing to the middle of the conventional dual damascene process. It is explanatory drawing after FIG. 12 of the conventional dual damascene process.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Lower layer conductor 2 Interlayer insulating film 3 1st insulating film 4 Recess 5 Second insulating film 6 Light 7 Conductor 8 Etching stopper film 10 Film forming apparatus 11 Chamber 12 Exhaust port 13 Stage 14 Wafer 15 Head 16 Nozzle 17 Bricker 18 Light source lamp 19 Quartz cover 21 Lower buried wiring 22 SiC film 23 p-MSQ film 24 SiOC film 25 Resist mask 26 Opening pattern 27 Via hole 28 First nonporous insulating film 29 Ultraviolet 30 First nonporous protective insulating film 31 TaN film 32 Cu Film 33 first barrier layer 34 via plug 35 SiC film 36 p-MSQ film 37 SiOC film 38 resist mask 39 opening pattern 40 trench 41 second nonporous insulating film 42 second nonporous protective insulating film 43 TaN film 44 Cu film 45 Second barrier layer 46 Upper buried wiring 47, 48 Ta film 49 p-MSQ Film 50 SiOC film 51 p-MSQ film 52 SiO ₂ film 53, 54 Opening 55 Nonporous insulating film 56 Nonporous protective insulating film 57 TaN film 58 Cu film 59 Barrier layer 60 Upper wiring 61 Lower buried wiring 62 SiCN Film 63 Via forming insulating film 64 SiCN film 65 Trench insulating film 66 SiCN film 67 Resist pattern 68 Recess 69 Resist pattern 70 Wiring trench 71 Via hole 72 Nonporous insulating film 73 Nonporous protective insulating film 74 Barrier film 75 Cu Plating film 76 Embedded conductor 77 Cu via plug 78 Cu upper layer embedded wiring

Claims (5)

A semiconductor substrate; a first insulating film containing holes formed on the semiconductor substrate; a recess formed in the first insulating film; a second insulating film formed on a sidewall of the recess; A conductor embedded in the recess through a second insulating film, and a bond on the surface of the first insulating film terminates with a functional group at the interface between the first insulating film and the second insulating film. A semiconductor device characterized in that the ratio of chemically bonding to the main chain of the material constituting the second insulating film is higher than the ratio of 2. The semiconductor device according to claim 1, wherein the second insulating film is made of SiOC, has an initial dielectric constant of 2.5 to 4.5, and a density of 1.5 to 2.5 g / cm < ³ >. Depositing an interlayer insulating film having at least a portion of a first insulating film containing holes on a semiconductor substrate; forming a recess in the interlayer insulating film; and a material constituting the first insulating film; Comprises a step of depositing a different type of second insulating film on the entire surface while irradiating light with a wavelength of 150 to 500 nm, and a step of embedding a conductor material in the recess. The interlayer insulating film includes an etching stopper film formed on the semiconductor substrate, the first insulating film formed on the etching stopper film, and an etching mask film formed on the first insulating film. 4. The method of manufacturing a semiconductor device according to claim 3, further comprising: The interlayer insulating film includes a first etching stopper film formed on the semiconductor substrate, the first insulating film formed on the first etching stopper film, and a first etching film formed on the first insulating film. 2. An etching stopper film, a third insulating film having a hole formed on the second etching stopper film, and an etching mask film formed on the third insulating film. 4. A method for manufacturing a semiconductor device according to 3.

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