JP2005223195A - Method for forming interlayer insulating film and method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing an interlayer insulating film having a low relative permittivity and an excellent mechanical characteristic, and to provide a method for manufacturing a semiconductor device using it. <P>SOLUTION: A first insulating film including a vacancy forming material and comprising a low permittivity material is formed on a diffusion protective film 2 formed on a lower layer interconnection 1. In the second place, providing a plasma process to the first insulating film removes a vacancy forming material to make the first insulating film a first porous insulating film 23. Repeating the steps of forming the insulating film and the steps of providing the plasma process enables a second porous insulating film 26 and a third porous insulating film 30 to be laminated on the first porous insulating film 23. This can form the interlayer insulating film 3 having the predetermined film thickness. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a method for forming an interlayer insulating film and a method for manufacturing a semiconductor device, and more particularly to a method for forming an interlayer insulating film made of a porous low dielectric constant insulating film and a method for manufacturing a semiconductor device using this method. .

  With the recent miniaturization and speeding up of semiconductor devices, multilayer wiring structures are progressing. However, as such miniaturization, higher speed, and multilayering progress, signal delay due to increase in wiring resistance and parasitic capacitance between wirings and between wiring layers becomes a problem. Since the signal delay T is proportional to the product of the wiring resistance R and the parasitic capacitance C, in order to reduce the signal delay T, it is necessary to reduce the parasitic capacitance as well as the resistance of the wiring layer.

  In order to reduce the wiring resistance R, a wiring material having a lower resistance may be used. For example, a transition from conventional Al (aluminum) wiring to Cu (copper) wiring can be mentioned.

  On the other hand, between the parasitic capacitance C between the wiring layers and the relative dielectric constant ε of the interlayer insulating film provided between the wiring layers, the distance d between the wiring layers, and the side area S of the wiring layer, C = (ε · S ) / D. Therefore, in order to reduce the parasitic capacitance C, it is necessary to use a low dielectric constant insulating film (hereinafter referred to as a low-k film) as an interlayer insulating film.

  As a method for forming a copper wiring using a low-k film, there is a damascene method (see, for example, Patent Document 1). This is known as a technique for forming a wiring without etching copper, considering that it is difficult to control the etching rate of copper compared to aluminum.

  Specifically, in the damascene method, an etching stopper film, a low-k film, and a cap film are sequentially formed on a lower layer wiring, a wiring groove is formed by dry etching using the resist film as a mask, and a resist film is formed by ashing. This is a method of forming a copper wiring layer by embedding a copper layer in a wiring groove after removing the film. The copper layer is embedded by forming a copper layer by embedding a wiring groove by a plating method and then flattening the surface using a CMP (Chemical Mechanical Polishing) method so that the copper layer remains only inside the wiring groove. Can be realized.

Conventionally, a SiO ₂ (silicon oxide) film has been used as an interlayer insulating film. However, in order to reduce the dielectric constant, recently, a silicon oxide film containing a fluorine atom or an organic group has been used as an interlayer insulating film. In particular, an MSQ (methyl silsesquioxane) film having a methyl group in the skeleton of a silicon oxide film is considered promising as a low-k film because of its low dielectric constant of about 2.7.

  Further, in order to further reduce the relative dielectric constant, the MSQ film is made porous. Specifically, after forming an MSQ film to which an appropriate hole forming material (porogen) is added on a support, the hole forming material is removed by a heat treatment or a plasma treatment, whereby a void is formed inside the MSQ film. Holes can be introduced.

JP 2002-270586 A

  However, this method tends to result in insufficient removal of the pore forming material existing deep in the MSQ film. For this reason, there is a problem that the holes cannot be formed uniformly in the film thickness direction and the relative dielectric constant increases. On the other hand, when the heat treatment time is lengthened or the high energy plasma treatment is performed in order to increase the removal rate of the pore forming material, there is a problem that damage to the MSQ film is increased. .

  Furthermore, when the hole forming material escapes from the MSQ film, a part of the skeleton of the MSQ film is destroyed, resulting in a problem that the mechanical strength of the MSQ film is lowered. Such a phenomenon is considered to become remarkable as the thickness of the MSQ film increases.

  The present invention has been made in view of such problems. That is, an object of the present invention is to provide a method for forming an interlayer insulating film having a low relative dielectric constant and excellent mechanical characteristics, and a method for manufacturing a semiconductor device using the same.

  Other objects and advantages of the present invention will become apparent from the following description.

  The method for forming an interlayer insulating film of the present invention includes a step of forming an insulating film made of a low dielectric constant material including a hole forming material on a semiconductor substrate, and plasma processing the insulating film to form a hole forming material. The step of removing and making the insulating film a porous insulating film, the step of forming the insulating film, and the step of performing the plasma treatment are repeatedly performed to form one or more other porous insulating films on the porous insulating film. And a step of laminating to form an interlayer insulating film having a predetermined thickness.

  In the method for forming an interlayer insulating film of the present invention, the insulating film can be formed by a plasma CVD method, and the plasma treatment is continuously performed in the same chamber as the chamber for forming the insulating film. be able to.

In the method for forming an interlayer insulating film of the present invention, the plasma treatment is performed using at least one gas selected from the group consisting of H ₂ gas, He gas, Ar gas, N ₂ O gas, and NH ₃ gas. Is preferred.

In the method for forming an interlayer insulating film of the present invention, the insulating film is a SiO ₂ film having silicon atoms bonded to at least one atom or organic group selected from the group consisting of a hydrogen atom, an alkyl group, and an allyl group. It is preferable. In this case, the insulating film can be either an MSQ film or an HSQ film.

  Furthermore, in the method for forming an interlayer insulating film of the present invention, the pore forming material preferably has a lower thermal decomposition temperature than the organic group bonded to the silicon atom.

  The method of manufacturing a semiconductor device according to the present invention includes a step of forming a diffusion prevention film on a lower layer wiring formed on a semiconductor substrate, and a method of forming a diffusion prevention film on the diffusion prevention film. A step of forming an interlayer insulating film by any of the above methods, a step of forming a cap film on the interlayer insulating film, and dry etching the cap film, the interlayer insulating film, and the diffusion prevention film to form a lower layer wiring And a step of forming a trench wiring which is embedded in the wiring trench and electrically connected to the lower layer wiring.

  In the method of manufacturing a semiconductor device according to the present invention, the step of forming the wiring groove includes the step of forming a resist film having a predetermined pattern on the cap film, and the cap film and the interlayer insulating film using the resist film as a mask. Performing a first dry etching to form an opening reaching the diffusion barrier film, a step of removing the resist film, a second dry etching to the diffusion barrier film using the cap film as a hard mask, Forming a wiring trench extending to the line.

  In the method for manufacturing a semiconductor device according to the present invention, the step of forming the wiring groove includes the step of forming a resist film having a predetermined pattern on the cap film, and the cap film and interlayer insulation using the resist film as a mask. It is also possible to have a step of dry etching the film and the diffusion prevention film to form a wiring groove reaching the lower layer wiring and a step of removing the resist film.

  As described above, the present invention includes a step of forming an insulating film made of a low dielectric constant material including a hole forming material on a semiconductor substrate, and removing the hole forming material by plasma treatment of the insulating film. The step of forming the insulating film as a porous insulating film, the step of forming the insulating film, and the step of performing the plasma treatment are repeatedly performed to stack one or more other porous insulating films on the porous insulating film. And the step of forming the interlayer insulating film having a predetermined thickness, the removal rate of the pore forming material contained in the insulating film can be increased. In addition, it is possible to suppress the destruction of the molecular structure when the hole forming material escapes from the insulating film. Therefore, an interlayer insulating film having a low relative dielectric constant and excellent mechanical strength can be formed.

  Further, according to the present invention, after forming an insulating film made of a low dielectric constant material including a hole forming material, the hole forming material is removed by plasma treatment of the insulating film, and the insulating film is porous insulated. Make a membrane. By repeating the above steps a plurality of times, one or more other porous insulating films are laminated on the porous insulating film to form an interlayer insulating film having a predetermined thickness, and then wiring grooves are formed in the interlayer insulating film. And a copper wiring layer is embedded. That is, a semiconductor device having a small signal delay and excellent reliability can be manufactured by a combination of an interlayer insulating film having a low relative dielectric constant and excellent mechanical strength and a copper wiring.

  1 to 16 are sectional views showing a method for manufacturing a semiconductor device in the present embodiment. In these drawings, the same reference numerals indicate the same parts.

  First, a semiconductor substrate is prepared. For example, the diffusion prevention film 2 is formed on the semiconductor substrate on which the lower layer wiring 1 (first copper wiring layer) is formed (FIG. 1).

  As the diffusion preventing film 2, for example, a SiN (silicon nitride) film, a SiC (silicon carbide) film, a SiCN (silicon carbonitride) film, or the like can be used. When a material having a high etching selectivity with respect to the interlayer insulating film formed thereon is used as the diffusion preventing film 2, the diffusion preventing film 2 can also function as an etching stopper film. On the other hand, as the lower layer wiring 1, for example, a tungsten plug that reaches the diffusion layer of the MOS transistor can be used. For simplicity, the structure of the lower layer wiring 1 is omitted in the figure.

  Next, an interlayer insulating film 3 is formed on the diffusion preventing film 2 (FIG. 1). Here, the interlayer insulating film 3 is a porous low dielectric constant insulating film having pores 4.

  In the present invention, after forming an insulating film made of a low dielectric constant material including a hole forming material, the insulating film is plasma treated to remove the hole forming material, and the insulating film becomes a porous insulating film. . By repeating the above steps a plurality of times, one or more other porous insulating films are laminated on the porous insulating film to form an interlayer insulating film 3 having a predetermined thickness. The film thickness of the interlayer insulating film 3 is preferably about 200 nm to 250 nm, for example.

  Specifically, after forming a thin film of an insulating film containing a hole forming material, plasma processing is performed on the insulating film. Thereby, it is considered that the pore forming material is decomposed to become a low molecular weight component and then volatilizes and escapes from the insulating film. As a result, the thin insulating film becomes a thin porous insulating film. A similar porous insulating film is formed by forming a thin film of an insulating film containing a pore forming material on the substrate and then performing plasma treatment. In this way, the thin film of the porous insulating film is laminated, and the above process is repeated until the total of these film thicknesses reaches the desired film thickness of the interlayer insulating film. For example, when the thickness of the interlayer insulating film is 600 nm, the thickness of the porous insulating film formed in one sequence is 200 nm, and the sequence may be repeated three times in total. Note that the relative dielectric constant of the finally formed interlayer insulating film is preferably about 2.0 to 2.5.

  10 to 16 are conceptual diagrams showing the steps of forming an interlayer insulating film according to the present invention.

  First, a first insulating film 21 made of a low dielectric constant material including a hole forming material 20 is formed on the diffusion prevention film 2 formed on the lower wiring 1 (FIG. 10). Next, plasma treatment is performed on the first insulating film 21 (FIG. 11), and the hole forming material 20 is removed. As a result, holes 22 are formed in the first insulating film 21 to form the first porous insulating film 23 (FIG. 12).

For example, when the first insulating film 21 is formed by the plasma CVD method, after the first insulating film 21 is formed, the supply of the source gas into the chamber and the application of the high frequency to the electrodes are stopped. The residual gas in the chamber is exhausted. Next, a gas serving as a plasma source is supplied into the chamber, and high frequency is applied to the electrodes to generate plasma. The gas for plasma treatment is selected from the group consisting of H ₂ (hydrogen) gas, He (helium) gas, Ar (argon) gas, N ₂ O (dinitrogen monoxide) gas, and NH ₃ (ammonia) gas. It is preferable to use at least one gas. After the plasma treatment is finished, the supply of gas into the chamber and the application of high frequency to the electrodes are stopped and the residual gas in the chamber is exhausted. Thus, the first porous insulating film 23 can be formed.

  After forming the first porous insulating film 23, a second insulating film 24 having the same composition as the first insulating film 21 is formed thereon (FIG. 13). In FIG. 13, reference numeral 25 denotes a hole forming material included in the second insulating film 24. Next, the same plasma treatment as described above is performed on the second insulating film 24 to change the second insulating film 24 into the second porous insulating film 26 (FIG. 14). In FIG. 14, 27 is a hole formed in the second insulating film 24. Further, a third insulating film 28 having the same composition as the first insulating film 21 and the second insulating film 24 is formed on the second porous insulating film 26 (FIG. 15). In FIG. 15, 29 is a hole forming material included in the third insulating film 28. Then, the third insulating film 28 is changed to the third porous insulating film 30 by performing plasma processing in the same manner (FIG. 16). In FIG. 16, 31 is a hole formed in the third insulating film 28.

  The first porous insulating film 23, the second porous insulating film 26, and the third porous insulating film 30 formed by the above steps constitute the interlayer insulating film 3 in the present embodiment (FIG. 16). According to the present invention, since the plasma treatment is performed on the thin insulating films, the removal rate of the pore forming material contained in these films can be increased. In addition, it is possible to suppress the destruction of the molecular structure when the hole forming material escapes from the insulating film. Therefore, an interlayer insulating film having a low relative dielectric constant and excellent mechanical strength can be formed.

  In the present invention, the film thickness of the porous insulating film formed in one sequence is determined by the film thickness that can sufficiently remove the pore forming material from the insulating film. That is, in the present invention, since the removal rate of the pore forming material is adjusted by the film thickness of the insulating film, it is not necessary to irradiate the insulating film with high-energy plasma in order to increase the removal rate. Here, the thinner the film thickness of the insulating film is, the higher the removal rate of the hole forming material is. Become more. Therefore, in practice, it is preferable to appropriately determine the thickness of the porous insulating film formed in one sequence by comparing and considering the relative dielectric constant and throughput of the interlayer insulating film.

  In general, the pore forming material can be removed by heat treatment instead of plasma treatment. However, for the following reason, in the present invention, the pore forming material is removed not by heat treatment but by plasma treatment.

  First, in the case of heat treatment, there is a concern that the previously formed film is damaged by the thermal history. On the other hand, in the case of plasma treatment, it is possible to suppress damage to the underlying film by controlling the plasma energy.

  Second, in the case of plasma processing, the film forming step and the plasma processing step can be continuously performed in the same chamber. Therefore, the entire processing time required for forming the interlayer insulating film can be shortened, and contamination of foreign matters can be prevented. On the other hand, also in the case of heat treatment, it is possible to perform the step of removing the pore forming material in the same chamber as the film forming chamber. However, in order to remove the pore forming material by heat treatment, the temperature needs to be 400 ° C. or higher (usually 450 ° C. for several minutes). Here, the film formation temperature of the insulating film is about 300 ° C. to 350 ° C., and there is a large temperature difference from the temperature necessary for removing the pore forming material. For this reason, a considerable waiting time is required until the predetermined temperature is reached, leading to a decrease in overall throughput. Furthermore, from the viewpoint of improving the reliability of semiconductor devices, there is a desire to lower the temperature of heat treatment applied in the manufacturing process. Since the temperature of 400 ° C. or higher belongs to a high temperature even in the whole manufacturing process, it is not preferable to perform the heat treatment at such a temperature.

In the present embodiment, as the insulating film constituting the interlayer insulating film 3, an insulating film having a relative dielectric constant lower than that of the SiO ₂ film is used. Specifically, a SiO ₂ film having a silicon atom bonded to a hydrogen atom, an alkyl group such as a methyl group (—CH ₃ ), or an allyl group (CH ₂ ═CHCH ₂ —) can be given. For example, an MSQ (methyl silsesquioxane) film or an HSQ (hydrogen silsesquioxane) film is suitable. These films can be formed by a plasma CVD method or a coating method. However, it is preferable to form by the plasma CVD method from the viewpoint that the film forming process and the plasma treatment process can be continuously performed in the same chamber.

  As the pore forming material, a material having a lower thermal decomposition temperature than an alkyl group or an allyl group bonded to a silicon atom is used. When the thermal decomposition temperature of the pore forming material is higher than the thermal decomposition temperature of these organic groups, the insulating film is decomposed before the pore forming material is decomposed, which is not preferable.

After the interlayer insulating film 3 is formed, a cap film 5 is formed on the interlayer insulating film 3 (FIG. 2). The cap film 5 functions as a protective film for the interlayer insulating film 3 in a CMP (Chemical Mechanical Polishing) process by a damascene method. As the cap film 5, for example, a SiO ₂ (silicon dioxide) film, a SiC (silicon carbide) film, a SiN (silicon nitride) film, or the like can be used. These films can be formed by, for example, a CVD (Chemical Vapor Deposition) method.

  In order to improve the adhesion between the interlayer insulating film 3 and the cap film 5, a surface treatment is performed on the interlayer insulating film 3 to form a modified layer (not shown), and then the cap film 4 is formed. It may be formed. Further, by providing an intermediate film (not shown) between the interlayer insulating film 3 and the cap film 5, the adhesion of these films may be improved.

  After the cap film 5 is formed, a resist film 6 having a predetermined pattern is formed (FIG. 3). Specifically, a photoresist (not shown) is applied to the entire surface of the cap film 5, exposed through a mask having a predetermined pattern, and developed. Thus, the resist film 6 can be formed by patterning the photoresist.

The type of exposure light can be appropriately selected according to the design rules of the semiconductor device. For example, KrF (krypton fluoride) excimer laser (wavelength: 248 nm) is used in the design rule of 0.25 μm to 0.13 μm, and ArF (argon fluoride) excimer laser (wavelength: 193 nm) is used in the design rule of 90 nm. In the design rule of 65 nm or less, an F ₂ laser (wavelength: 157 nm) is used as the light source of the exposure apparatus.

  In the present embodiment, the resist film 6 may be formed after providing an antireflection film (not shown) on the cap film 5. The antireflection film serves to eliminate reflection of exposure light at the interface between the photoresist and the antireflection film by absorbing exposure light transmitted through the photoresist when patterning the photoresist. As the antireflection film, a film containing an organic substance as a main component can be used. For example, the antireflection film can be formed by a spin coating method or the like.

  Next, the cap film 5, the interlayer insulating film 3 and the diffusion prevention film 2 are dry-etched to form a wiring groove reaching the lower layer wiring 1.

  For example, when the diffusion prevention film 2 also functions as an etching stopper film, the first dry etching is performed on the cap film 5 and the interlayer insulating film 3 using the resist film 6 as a mask. This etching is automatically terminated when the diffusion prevention film 2 is reached, and an opening 7 reaching the diffusion prevention film 2 is formed (FIG. 4). In this case, a material having a high etching selection ratio with the interlayer insulating film 3 is used as the diffusion preventing film 2.

  Next, ashing is performed to remove the resist film 6 that is no longer needed. Although ashing can be performed using oxygen, ashing in a reducing atmosphere containing hydrogen is preferable in order not to damage the interlayer insulating film 3.

  After the ashing is completed, the ashing residue is removed by performing a cleaning process. Thereby, the structure shown in FIG. 5 is obtained.

  After removing the resist film 6 by ashing and cleaning treatment, second dry etching is performed on the etching stopper film 2 using the cap film 5 as a hard mask. As a result, a wiring groove 8 reaching the lower layer wiring 1 can be formed (FIG. 6).

  In the present embodiment, the wiring groove 8 may be formed by dry etching of the cap film 5, the interlayer insulating film 3 and the etching stopper film 2 using the resist film 6 as a mask. In this case, the cap film 5 does not need to function as a hard mask. After the dry etching is completed, the resist film 6 that is no longer necessary is removed by ashing, whereby the structure shown in FIG. 6 can be obtained.

  After the wiring trench 8 is formed, the etching residue is removed by a cleaning process. Thereafter, a copper wiring layer is embedded in the wiring groove 8 using a plating method and a CMP method, and a groove wiring electrically connected to the lower layer wiring 1 is formed.

  First, after a barrier metal film 9 is formed on the entire surface including the wiring trench 8, a seed Cu (copper) film 10 is formed (FIG. 7). These films can be formed by a sputtering method.

  As the barrier metal film 9, for example, a Ta (tantalum) film, a TaN (tantalum nitride) film, a W (tungsten) film, a WN (tungsten nitride) film, a Ti (titanium) film, or a TiN (titanium nitride) film is used. be able to.

  After the seed Cu film 10 is formed, a Cu layer 11 is formed by a plating method (FIG. 8). Next, heat treatment is performed to grow copper grains and to uniformly fill the inside of the wiring groove 8 with Cu. Thereafter, the surface is planarized by CMP, and the Cu layer 11, the seed Cu film 10 and the barrier metal film 9 are removed except for the inside of the wiring trench 8.

  Through the above steps, the trench wiring 12 that is electrically connected to the lower layer wiring 1 can be formed (FIG. 9). Thereafter, after forming a via plug electrically connected to the trench wiring 12, a multilayer wiring structure can be formed by repeating the same process.

  According to the present invention, an interlayer insulating film having a low relative dielectric constant and excellent mechanical strength can be formed. By combining this with a copper wiring, signal delay is small and reliability is excellent. It is possible to manufacture a semiconductor device.

  In the present embodiment, an example of a single damascene process has been described, but the present invention is not limited to this. The present invention can be similarly applied to a dual damascene process.

It is sectional drawing which shows the manufacturing method of the semiconductor device by this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device by this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device by this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device by this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device by this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device by this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device by this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device by this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device by this invention. It is sectional drawing which shows the formation method of the interlayer insulation film by this invention. It is sectional drawing which shows the formation method of the interlayer insulation film by this invention. It is sectional drawing which shows the formation method of the interlayer insulation film by this invention. It is sectional drawing which shows the formation method of the interlayer insulation film by this invention. It is sectional drawing which shows the formation method of the interlayer insulation film by this invention. It is sectional drawing which shows the formation method of the interlayer insulation film by this invention. It is sectional drawing which shows the formation method of the interlayer insulation film by this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Lower layer wiring 2 Etching stopper film 3 Interlayer insulating film 4, 22, 27, 31 Void 5 Cap film 6 Resist film 7 Opening 8 Wiring groove 9 Barrier metal film 10 Seed Cu film 11 Cu layer 12 Groove wiring 20, 25, 29 pore forming material 21 first insulating film 23 first porous insulating film 24 second insulating film 26 second porous insulating film 28 third insulating film 30 third porous insulating film

Claims (9)

Forming an insulating film made of a low dielectric constant material including a pore forming material on a semiconductor substrate;
Plasma-treating the insulating film to remove the pore-forming material and making the insulating film a porous insulating film;
By repeatedly performing the step of forming the insulating film and the step of performing the plasma treatment, one or more other porous insulating films are laminated on the porous insulating film to form an interlayer insulating film having a predetermined thickness. A method for forming an interlayer insulating film. The insulating film is formed by a plasma CVD method,
The method for forming an interlayer insulating film according to claim 1, wherein the plasma treatment is performed continuously with the formation of the insulating film in the same chamber as the chamber for forming the insulating film. _3. The interlayer insulating film according to claim 1, wherein the plasma treatment is performed using at least one gas selected from the group consisting of H ₂ gas, He gas, Ar gas, N ₂ O gas, and NH ₃ gas. Forming method. The insulating layer, a hydrogen atom, according to any one of claims 1 to 3 is a SiO ₂ film having a silicon atom bonded to at least one atom or an organic group selected from the group consisting of alkyl groups and aryl groups A method for forming an interlayer insulating film.   The method for forming an interlayer insulating film according to claim 4, wherein the insulating film is one of an MSQ film and an HSQ film.   6. The method for forming an interlayer insulating film according to claim 4, wherein the pore forming material has a lower thermal decomposition temperature than an organic group bonded to the silicon atom. In a method for manufacturing a semiconductor device having a multilayer wiring structure,
Forming a diffusion barrier film on the lower wiring formed on the semiconductor substrate;
Forming an interlayer insulating film on the diffusion barrier film using the method according to any one of claims 1 to 6;
Forming a cap film on the interlayer insulating film;
Dry etching the cap film, the interlayer insulating film and the diffusion barrier film to form a wiring groove reaching the lower layer wiring;
A method of manufacturing a semiconductor device comprising: embedding a copper wiring layer in the wiring groove and forming a groove wiring electrically connected to the lower layer wiring. Forming the wiring groove includes forming a resist film having a predetermined pattern on the cap film;
Performing a first dry etching on the cap film and the interlayer insulating film using the resist film as a mask to form an opening reaching the diffusion prevention film;
Removing the resist film;
The method for manufacturing a semiconductor device according to claim 7, further comprising: performing a second dry etching on the diffusion prevention film using the cap film as a hard mask to form a wiring groove reaching the lower layer wiring. Forming the wiring groove includes forming a resist film having a predetermined pattern on the cap film;
Using the resist film as a mask, dry etching the cap film, the interlayer insulating film, and the diffusion prevention film to form a wiring groove that reaches the lower layer wiring;
The method of manufacturing a semiconductor device according to claim 7, further comprising a step of removing the resist film.

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