JP2003303880A - Wiring structure using insulating film structure between laminated layers and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the yield and reliability of wires of a multi-layered wiring structure using a low-dielectric-constant film. <P>SOLUTION: The wiring structure has a 1st insulating film 710a on a lower- layer Cu wire, a 2nd insulating film 711a which does not have a step due to the lower-layer wire on the 1st insulating film, and a 3rd insulating film 713a which is formed on the 2nd insulating film and is thicker than the 2nd insulating film 711a. A 4th insulating film 714a is formed on the 3rd insulating film, a groove is formed penetrating the 4th insulating film to extend into the 3rd insulating film, and the lower-layer wire and a via hole are connected with each other not through a barrier metal layer. Consequently, a dual-damascene wiring structure using insulating materials with low dielectric constants can easily be formed and sufficiently applied to mass production. Then, a multi- layered wiring structure which has a fine structure, high performance, and high reliability becomes easy to be manufactured. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring structure in a semiconductor device and a manufacturing method thereof, and more particularly to a groove wiring (damascene wiring) structure using a film having a dielectric constant lower than that of a silicon oxide film as an interlayer insulating film. is there.

[0002]

2. Description of the Related Art Conventionally, aluminum (Al) or Al alloy is widely used as a conductive material for semiconductor highly integrated circuits (LSI), and a silicon oxide film (SiO 2 film) is widely used as an insulating film between wirings and between wirings. Has been used.
Then, with the progress of miniaturization of LSIs, copper (Cu) is used as a conductive material to reduce the resistance of the wiring and to reduce the parasitic capacitance between the wirings in order to suppress or reduce the delay of signal transmission in the wirings. Silicon oxide films containing organic substances and holes having a low dielectric constant have come to be used as insulating films between layers and wiring layers. However, in a wiring containing Cu as a main component, since Cu diffuses faster than Al in an insulating film such as silicon (Si) or a silicon oxide film, it penetrates into a semiconductor element portion such as a transistor. In addition, in order to prevent deterioration of withstand voltage between wirings and ensure reliability, it is necessary to form a diffusion prevention (barrier) film around Cu to prevent diffusion.

In the formation of the damascene wiring structure using Cu, it is necessary to simplify the process and reduce the process cost. Practical use of dual damascene wiring and low dielectric constant interlayer insulation using a dual hard mask. Proposals for film processing methods have been made.

A conventional damascene wiring will be described below with reference to the drawings.

[Prior Art 1] The bottom and side surfaces of the Cu film are C
A wiring structure covered with a conductor film serving as a barrier film of u and a manufacturing method thereof will be described with reference to FIGS. FIGS. 10A to 10H show a method of manufacturing a wiring structure using a so-called dual damascene method, in which the conductive material of the conductor is embedded in the wiring groove and the via hole at the same time, which makes it possible to reduce the number of steps and the working time. Is shown.

As shown in FIG. 10A, Cu wiring 801 is formed on a silicon substrate. Then, as shown in FIG. 10B, a silicon nitride film 80 is formed on the Cu wiring 801.
2, silicon oxide film 803, silicon oxynitride film 804,
A silicon oxide film 805 is sequentially deposited. Here, the lower wiring is chemically mechanically polished (Chemical Mechanical).
The step is transferred onto the silicon oxide film 803 by reflecting the step of the lower wiring pattern due to the dishing and erosion at the time of performing the Al polishing (CMP). Therefore, CMP is performed after the formation of the silicon oxide film 803 for forming the via interlayer film to perform flattening, and a flat multi-layer wiring structure is obtained. A via resist pattern 806 is formed thereon (FIG. 10C). Then, the silicon oxide film 805, the silicon oxynitride film 804, and the silicon oxide film 803 are sequentially etched by anisotropic etching using the via resist pattern 806 as a mask, and then the resist pattern 806 is removed to form a via hole 807 (FIG. 10). (D)).

Next, a wiring groove resist pattern 808 is formed on the via hole (FIG. 10E), and the silicon oxide film 805 corresponding to the upper wiring groove is removed by anisotropic etching using the wiring groove pattern as a mask. After removing the resist pattern 808, the silicon nitride film 802 at the bottom of the via hole is removed by etching to form a via hole and a wiring groove 809 in which Cu is exposed at the bottom (FIG. 10F).

Next, a barrier film 810 made of a conductor is formed on this entire surface, and then a Cu film 811 is formed (FIG. 10).
(G)). Excess Cu 811 other than the wiring trench or via hole is removed by CMP, and the excess barrier film 810 is similarly removed. Then, as shown in FIG.
By forming the barrier film 813 made of an insulator, a Cu wiring 812 is formed, the lower surface and side surfaces of which are conductor barrier layers and the upper surface of which is covered with an insulating film barrier layer. In this way, the multi-layer wiring is formed by using the dual damascene method.

[Prior Art 2] In order to reduce wiring resistance and interlayer capacitance, a method has been proposed in which copper is used as a conductive material and a film having a dielectric constant lower than that of a silicon oxide film is used as an interlayer insulating film. In general, a low dielectric constant film having a relative dielectric constant lower than that of a silicon oxide film often contains an organic substance, and resist ashing using oxygen plasma, which has been conventionally used, cannot be performed. Therefore, a so-called dual hard mask process is often used in which a dual damascene wiring groove is formed by transferring a resist pattern to an insulating film having resistance to oxygen ashing as described below.

The details will be described below with reference to FIGS. 11 and 12. First, as shown in FIG. 11A, a silicon nitride film 902, a low dielectric constant film 903, a silicon oxynitride film 904, a low dielectric constant film 905, and a silicon nitride film 906 are formed on a lower wiring 901 made of Cu. Are sequentially formed. The silicon oxynitride film 903 serves as an etching stopper when the low dielectric constant film 905 is etched. The silicon oxide film 906 and the silicon nitride film 907 are the low dielectric constant film 905.
It becomes a dual hard mask when etching. Then, an antireflection film 908 is formed on the upper surface of the silicon nitride film 907.
After forming the photoresist, a photoresist is formed, and a resist pattern for wiring grooves is further formed on the photoresist 909 by using the photolithography technique.

Subsequently, as shown in FIG. 11B, a photoresist 909 having a wiring groove pattern is formed.
Using the as a mask, the silicon nitride film 908 is etched using plasma such as CH2F2 / Ar / O2 gas system. Subsequently, as shown in FIG. 11C, after etching the silicon nitride film 907, the photoresist 909 and the antireflection film 908 are removed by oxygen ashing plasma to form a wiring groove transfer pattern 910. The silicon oxide film 906 described above is formed to protect the low dielectric constant film 904 from oxygen plasma that strips the photoresist 909. When the photoresist 909 is peeled off, the silicon oxide film 906 exists at the bottom of the wiring groove pattern formed in the silicon nitride film 907. The low dielectric constant 905 is not exposed to oxygen plasma and is not etched.

Subsequently, as shown in FIG. 11D, an antireflection film 911 and a photoresist 912 are formed on the formed wiring groove transfer pattern 910, and a via hole pattern 913 is formed.

Subsequently, as shown in FIG. 12A, the silicon oxide film 905 is etched by using plasma containing polymer fluorocarbon such as C4F8 or C5F8. After that, the low dielectric constant film 906 is etched mainly with a fluorocarbon gas. Further, the silicon nitride film 902 is etched using plasma. As a result, a contact between the lower layer wiring and the upper layer wiring is formed.

After that, a Ta / TaN film 915 is formed,
Cu film 916 is embedded by plating method, and further CM
The excess Ta / TaN film and the copper film are removed by the P method, and the copper wiring 916 embedded in the low dielectric constant film 904 is formed (FIG. 12B).

As described above, in the known copper-embedded wiring technique, the organic film 9 having a low dielectric constant is used as the interlayer insulating film for the purpose of reducing the interwiring capacitance of the ULSI multilayer wiring.
04 has been introduced.

[0016]

The above-mentioned conventional techniques have the following problems.

In Conventional Example 1, in order to reduce the effective capacitance between wirings, an interlayer insulating film (in this case, a silicon oxide film (relative dielectric constant k = 4.2), a silicon nitride film (k = 7.
1) and the silicon oxynitride film (k = 6.5)) have been required to have a low dielectric constant.

In the conventional example 2, the capacitance between wirings is reduced by introducing a low dielectric constant interlayer film.
In the technique known from Japanese Patent Application Laid-Open No. 0105, it is difficult to perform the interlayer film CMP because a low dielectric constant film is used for the via interlayer film, and as a result, the step due to the lower layer wiring cannot be reduced, Polishing residue was generated at the time of CMP of the upper layer wiring, which caused a short circuit between the wirings, which was a cause of lowering the yield.

Although development of a low dielectric constant film capable of CMP for an interlayer film and development of a CMP technique for a low dielectric constant insulating film are underway, a low dielectric constant film (ratio to an oxide film ratio of about 1) is inferior in mechanical strength.
The polishing technique of (10 to 1/20) has many problems such as increase of particles and generation of scratches, and is not generally easy in the technical field at present.

On the other hand, in order to solve these problems, a low dielectric constant film is introduced only in the wiring portion, and CMP is performed in the via interlayer film portion.
A so-called hybrid structure has been proposed in which an interlayer insulating film CMP is performed by using a possible insulating film, for example, a silicon oxide film to improve processing controllability (Japanese Patent Laid-Open No. 10-
112503, etc.).

However, when the silicon oxide film is used as the via interlayer film, firstly, the relative permittivity k of the silicon oxide film is as high as 4.2, which causes an increase in inter-wiring capacitance. Even if the low dielectric constant film is introduced into the inter-wiring portion, there is a problem that the effective dielectric constant cannot be reduced.

Second, by using a silicon oxide film for the via connection portion (contact portion between the conductive material and the via interlayer insulating film), stress applied to the conductive material of the connection portion, that is, the connection portion between the upper layer wiring and the via is applied. There is a problem that Cu, which is a conductive material, is disconnected due to stress migration.

Therefore, it is difficult to reduce the dielectric constant of the insulating material between the via layers, to achieve both planarization treatment, and to obtain a wiring having high resistance to via stress migration, and there has been a strong demand for a solution.

The main object of the present invention is to solve the above-mentioned problems, to reduce the effective wiring capacity of the damascene wiring structure and to improve the reliability of stress migration, and also to improve the yield by improving the processing controllability of fine wiring. It is to achieve improvement easily.

[0025]

To this end, in the present invention,
In the structure of the grooved wiring formed in the insulating film on the semiconductor substrate, the via interlayer film for forming the via hole connecting the different layer wirings has a multilayer structure.

That is, in the wiring structure of the present invention, in the structure of the multilayer wiring formed in the insulating film on the semiconductor substrate, the first insulating film which is in direct contact with the lower conductive material and the first insulating film are provided. And a third insulating film which is a flat insulating film which does not depend on the unevenness of the lower layer wiring and which is a stress relaxation layer of a low dielectric constant provided on the second insulating film. And a wiring groove penetrating the fourth insulating film formed on the third insulating film and reaching the inside of the third insulating film are formed, and the wiring groove and the via hole are formed. It is characterized in that a conductive material is embedded.

Further, in the wiring structure of the present invention, a fifth insulating film is formed on the fourth insulating film, penetrates the fourth insulating film and the fifth insulating film, and the second insulating film is formed. A feature is that a groove reaching the inside of the insulating film is formed and a conductive material is embedded in the inside of the groove.

Further, in the wiring structure of the present invention, the relative permittivity of the third insulating film is smaller than that of the second insulating film,
Further, it is characterized in that it is larger than the relative dielectric constant of the fourth insulating film.

Furthermore, the wiring structure of the present invention is characterized in that the thickness of the third insulating film is not less than the minimum wiring interval of the upper wiring.

Further, the wiring structure of the present invention does not have an interface layer containing a metal other than Cu as a main component at the connecting portion between the lower wiring and the via hole when the main component of the conductive material is Cu, and The third insulating film has resistance to Cu diffusion.

By applying the present invention including the above-mentioned (multilayer) wiring structure and the method of forming the wiring structure, the following technical improvements are made.

(1) By forming a laminated structure of the first insulating film having excellent Cu diffusion resistance, the planarizing second insulating film, and the third insulating film serving as the stress relaxation layer having a low dielectric constant, The yield can be improved without causing a short circuit of the wiring formed in the groove which penetrates the fourth insulating film to reach the inside of the third insulating film or an increase in variation in resistance.

(2) A groove that penetrates the fourth insulating film and reaches the inside of the third insulating film that is a stress relaxation layer having a low dielectric constant is provided, and the conductive material is embedded in the groove. Then, the connection portion between the upper wiring and the via is formed inside the third insulating film which is the stress relaxation layer. Therefore, the stress on the upper layer wiring and the via portion can be relaxed, and the stress migration resistance of the conductive material can be improved.

(3) The thickness of the third insulating film is thicker than that of the second insulating film, and in addition, a groove is formed which penetrates the fourth insulating film and reaches the inside of the third insulating film. The effective wiring capacitance can be reduced by setting the wiring spacing to be equal to or larger than the wiring spacing.

(4) In the wiring in which Cu is used as the conductive material, the third insulating film has resistance to Cu diffusion, so that a metal other than Cu is used as a main component in the connection between the lower wiring and the via hole. A wiring structure having no interface layer can be provided, and stress migration and electromigration resistance of Cu wiring can be improved.

As described above, according to the present invention, a dual damascene wiring structure using an insulating material having a low dielectric constant can be easily formed and can be sufficiently applied to mass production.
Then, it becomes easy to manufacture a multilayer wiring structure having a fine structure, high performance, and high reliability.

[0037]

DESCRIPTION OF THE PREFERRED EMBODIMENTS [Embodiment 1] An embodiment of the present invention will be described with reference to FIG. Here, FIG.
(A)-(f) is sectional drawing which shows the manufacturing process sequence of a dual damascene wiring structure.

First, as shown in FIG. 1A, a contact interlayer film 102 is formed on the upper surface of a lower semiconductor device structure 101 including a diffusion layer (not shown), a gate oxide film (not shown), a gate electrode (not shown) and the like. , Plug 103
Is formed, and the lowermost layer wiring is formed on the interlayer insulating film composed of the etching stopper film 104 and the low dielectric constant film 105, and Cu 107 which is a conductive material is formed on the barrier metal 106, for example, a laminated film of Ta / TaN to form a bottom surface and side walls. It is formed to be enclosed.

Here, the low dielectric constant film 105 is, for example, HS.
Q (Hydrogen Silse
squioxane) membrane, MSQ (Methylsilsesquioxane (M
ethyl Silsesquioxane)) film, BCB (divinylsiloxane bisbenzocyclobutene) film, a film in which an aromatic-containing organic polymer film is made porous. More specifically, there is a porous organic silica film such as an ALCAP-STM (registered trademark) film, which has Si-H bond and Si-CH.
It may be formed of a porous silica film containing at least one bond of 3 bond and Si—F bond.

The conductive material forming the wiring is Cu, Ag,
Al, Ni, Co, W, Si, Ti, Ta, and compounds thereof are preferable, and the case where Cu is the main component is shown here. Then, the etching stopper film 104
May be BCB, SiC, SiN, SiCN, SiOC, or an insulating thin film containing an organic substance therein.

When the CMP of Cu is performed on the formed lower layer Cu wiring under the general conditions in the art, the width of the wiring and the distance between the wirings are increased by the dishing 116 and erosion (not shown). It depends on 200Å-10
Generally, a step difference of about 00Å occurs.

Subsequently, as shown in FIG. 1B, a first insulating film 108 (generally called an insulating barrier film) and a second insulating film 109 (generally called a via interlayer film) are formed. The first insulating film 108 is formed of BCB, SiC, Si.
It is made of N, SiCN, SiOC or an insulating thin film containing an organic substance, and has a thickness of 100Å to 1000Å
Is good, and preferably 150Å to 500Å.

At this time, the step of the lower layer Cu wiring is transferred to the second insulating film as it is, and the step 117 is formed. The second insulating film 109 is a silicon oxide film or a relatively high-strength low-dielectric-constant film containing siloxane as a main component, and is a material that can easily perform the interlayer film CMP by a general polishing technique in the technical field. is necessary.

Then, as shown in FIG. 1C, a flattening C
MP is performed to alleviate the step due to dishing and erosion by CMP when the lower Cu wiring is formed. The film thickness of the second insulating film 9 to be deposited is preferably about 1.5 to 2 times the film thickness after polishing. For example, in order to obtain a film thickness of 2000Å after flattening, it is preferable to deposit about 4000Å and perform 2000Å polishing.

Subsequently, as shown in FIG. 1 (d),
A third insulating film 110 (generally called an etching stopper film) and a fourth insulating film 111 (generally called a wiring interlayer insulating film) are deposited. Here, the third insulating film 11
0 needs to have a low dielectric constant and low stress at the same time as functioning as an etching stopper. Second relative permittivity
Is preferably smaller than the insulating film of, for example, BCB
A (divinylsiloxane bisbenzocyclobutene) film, an organic film, an organic polymer film containing aromatic or siloxane, or an organic siloxane film is preferable.

Here, the thinner the second insulating film and the thicker the third insulating film, the more the inter-wiring capacitance can be reduced. However, the thickness of the second insulating film is not less than the maximum step difference of the lower conductive material. It is preferable that Generally, the maximum step difference of the lower conductive material is 1000 Å, so that the thickness of the second insulating film after planarization is preferably 1000 Å or more. Also,
The thickness of the third insulating film is preferably larger than the minimum wiring interval of the upper layer wiring, and particularly preferably 1000 Å or more.

The fourth insulating film is required to have a low dielectric constant. For example, HSQ (Hydrogen Silsesquioxane) film, MSQ (Methyl Silsesquioxane) film, BC
B (divinylsiloxane bisbenzocyclobutene) film,
For example, it is a film in which an organic polymer film containing aromatic is made porous. More specifically, ALCAP-STM (registered trademark)
There is a porous organic silica film such as a film, Si-H
It may be formed of a porous silica film containing at least one of a bond, a Si-CH3 bond, and a Si-F bond.

Further, when the strength of the fourth insulating film is poor, in order to secure the strength of the film, a fifth insulating film (not shown) is formed on the fourth insulating film, and the fourth insulating film is formed. It is also effective to improve workability by forming a wiring penetrating the insulating film and the fifth insulating film.

Subsequently, as shown in FIG. 1 (e),
Fine processing is performed using photoresist and reactive ion etching to form the dual damascene groove 112.

A feature of the present invention is that a wiring groove that penetrates through the fourth insulating film and reaches the inside of the third insulating film is formed, and a conductive material is provided through the wiring groove bottom and the wiring sidewall. And a third insulating film are in contact with each other. The depth of the groove formed inside the third insulating film is 50Å to 1000Å, preferably about 300Å to 500Å.

Subsequently, as shown in FIG. 1F, the conductive barrier film 113 and the Cu film 114 are buried in the dual damascene wiring groove 112, and the conductive material is polished by the CMP method. Thus, the dual damascene wiring 115 connected to the lower layer wiring is formed.

According to the present invention, it becomes possible to easily form a dual damascene wiring structure using an insulating material having a low dielectric constant, and it is possible to simultaneously reduce the capacitance between wirings and control the workability of fine wirings. become.

[Embodiment 2] An embodiment of the present invention will be described with reference to FIG. Here, FIGS. 2A to 2H are sectional views showing the order of manufacturing steps of the dual damascene wiring structure.

First, as shown in FIG. 2A, a contact interlayer film 202 is formed on the upper surface of a lower semiconductor device structure 201 including a diffusion layer (not shown), a gate oxide film (not shown), a gate electrode (not shown) and the like. The plug 203
Is formed, and the lowermost layer wiring is formed on the interlayer insulating film including the etching stopper film 204 and the low dielectric constant film 205, and Cu207 as a conductive material is formed on the barrier metal 206, for example, a bottom film and a side wall on a Ta / TaN laminated film. It is formed to be enclosed.

Here, the low dielectric constant film 205 is, for example, HS.
Q (Hydrogen Silse
squioxane) membrane, MSQ (Methylsilsesquioxane (M
ethyl Silsesquioxane)) film, BCB (divinylsiloxane bisbenzocyclobutene) film, a film in which an aromatic-containing organic polymer film is made porous. More specifically, there is a porous organic silica film such as an ALCAP-STM (registered trademark) film, which has Si-H bond and Si-CH.
It may be formed of a porous silica film containing at least one bond of 3 bond and Si—F bond.

The conductive material forming the wiring is Cu, Ag,
Al, Ni, Co, W, Si, Ti, Ta, and compounds thereof are preferable, and the case where Cu is the main component is shown here. Then, the etching stopper film 204
May be BCB, SiC, SiN, SiCN, SiOC, or an insulating thin film containing an organic substance therein.

When the CMP of Cu is performed under the general conditions in the technical field, the formed lower layer Cu wiring has a width of the wiring and an interval of the wiring due to dishing 216 and erosion (not shown). It depends on 200Å-10
Generally, a step difference of about 00Å occurs.

Then, as shown in FIG. 2B, a first insulating film 208 (generally called an insulating barrier film) and a second insulating film 209 (generally a via interlayer film) are formed. The first insulating film 108 is formed of BCB, SiC, Si.
It is made of N, SiCN, SiOC or an insulating thin film containing an organic substance, and has a thickness of 100Å to 1000Å
Is good, and preferably 150Å to 500Å.

The step of the lower Cu wiring is directly transferred to the second insulating film to form a step 217. The second insulating film 209 is a silicon oxide film or a relatively high-strength low-dielectric-constant film containing siloxane as a main component, and is a material that can easily perform the interlayer film CMP by a general polishing technique in the technical field. is necessary.

Then, as shown in FIG. 2C, a flattening C
MP is performed to alleviate the step due to dishing and erosion by CMP when the lower Cu wiring is formed. The film thickness of the deposited second insulating film 209 is 1.5 to the film thickness after polishing.
About twice is preferable. For example, in order to obtain a film thickness of 2000 Å after flattening, about 4000 Å is deposited,
Å It is preferable to carry out polishing.

Then, as shown in FIG. 2D, a third insulating film 210 (generally called an etching stopper film) and a fourth insulating film 211 (generally called a wiring interlayer insulating film). ) Is deposited. Here, the third insulating film 210 must function as an etching stopper, and at the same time have a low dielectric constant and a low stress, and further have excellent resistance to Cu diffusion. The relative dielectric constant is preferably smaller than that of the second insulating film. As an insulating film satisfying such a condition, for example, a BCB (divinylsiloxanebisbenzocyclobutene) film is preferable, and it can be formed by a plasma polymerization method, a coating firing method, or the like.

Here, as the second insulating film is thinner and the third insulating film is thicker, the inter-wiring capacitance can be reduced. However, the thickness of the second insulating film is not less than the maximum step difference of the lower conductive material. It is preferable that Generally, the maximum step difference of the lower conductive material is 1000 Å, so that the thickness of the second insulating film after planarization is preferably 1000 Å or more. Also,
The thickness of the third insulating film is preferably larger than the minimum wiring interval of the upper layer wiring, and particularly preferably 1000 Å or more.

The fourth insulating film is required to have a low dielectric constant. For example, HSQ (Hydrogen Silsesquioxane) film, MSQ (Methyl Silsesquioxane) film, BC
B (divinylsiloxane bisbenzocyclobutene) film,
For example, it is a film in which an organic polymer film containing aromatic is made porous. Specifically, there is a porous organic silica film such as an ALCAP-STM (registered trademark) film, and a porous film containing at least one bond of Si-H bond, Si-CH3 bond, and Si-F bond. It may be formed of a silica film.

Further, when the strength of the fourth insulating film is poor, in order to secure the strength of the film, a fifth insulating film (not shown) is formed on the fourth insulating film, and the fourth insulating film is formed. It is also effective to improve workability by forming a wiring penetrating the insulating film and the fifth insulating film.

Subsequently, as shown in FIG. 2E, fine processing is performed by using a photoresist and reactive ion etching to form a dual damascene groove 212. At this time, it is important that the dual damascene trench 212 penetrates the fourth insulating film and reaches the inside of the third insulating film.

Subsequently, as shown in FIG. 2F, the conductive barrier film 213 is embedded in the dual damascene wiring groove 212. Here, the conductive barrier film means Ta, Ti, W, Si,
Alternatively, it is made of a material whose main component is its nitride. Then, as shown in FIG. 2G, the conductive barrier film 213 deposited on the bottom of the via hole is removed by RIE or R.
Selectively removed by F etching. Here, when the conductive barrier metal film at the bottom of the via hole is removed, the barrier metal at the bottom of the wiring groove is also removed at the same time, and the conductive barrier metal film remains only on the sidewall of the via hole and the sidewall of the wiring groove. Subsequently, as shown in FIG. 2H, the Cu film 214 is embedded and the conductive material is polished by the CMP method. In this way, the connection 215 between the lower wiring and the via hole without the barrier metal layer is obtained.

The feature of the present invention is that the third insulating film has resistance to Cu diffusion and the wiring groove is formed so as to reach the inside of the third insulating film. The conductive barrier film 213 deposited on the RIE
Alternatively, even if the conductive barrier metal film is selectively removed by RF etching and does not exist at the bottom of the wiring groove,
It is possible to prevent Cu from diffusing from the bottom of the wiring groove. With such a structure, it is possible to prevent the diffusion of Cu even when the barrier metal at the bottom of the trench is etched back, and obtain a dual damascene wiring in which the lower layer wiring and the via hole are connected without the barrier metal layer. Is possible.

According to the present invention, a dual damascene wiring structure using an insulating material having a low dielectric constant can be easily formed, the capacitance between wirings can be reduced, and the workability of fine wiring can be controlled.
The wiring reliability can be improved at the same time.

[Comparative Example 1] Next, the effect of performing the planarizing CMP on the second insulating film will be described in detail with reference to FIG. Here, FIG. 3A is a sectional view of the dual damascene wiring structure formed based on the first embodiment, and FIG. 3B is a sectional view of the wiring structure when the planarization CMP is not performed.

A contact interlayer film 302 and a plug 303 are formed on the upper surface of a lower semiconductor device structure 301 including a diffusion layer (not shown), a gate oxide film (not shown), a gate electrode (not shown), and the like, and a contact interlayer film 302 and a plug 303 are formed thereon. The lower wiring is the etching stopper film 304 and the low dielectric constant film 3.
Cu 307, which is a conductive material, is formed on the interlayer insulating film made of 05 in a form in which the bottom surface and the side wall are surrounded by a barrier metal 306, for example, a laminated film of Ta / TaN. The first insulating film 308 (insulating barrier film) and the second insulating film 3 are provided between the wiring layers.
09 (via interlayer film) and a third insulating film 310. The upper wiring is composed of the fourth insulating film 311, the conductive barrier film 312,
It consists of a Cu film 313.

Lower layer C formed according to the first embodiment
For the u wiring, Cu is formed by a method commonly used in this technical field.
When the CMP is performed, a step difference of about 200Å to 800Å due to dishing or erosion occurs. When the CMP of the interlayer film is performed (FIG. 3A), it is possible to reduce the step caused by the lower layer wiring and form the multilayer wiring with good controllability regardless of the step of the lower layer. it can. On the other hand, when the flattening CMP of the interlayer film is not performed (FIG. 3B), the polishing residue 314 is generated on the upper layer wiring due to the step of the lower layer wiring, and the wiring short circuit is likely to occur. Become. Therefore, flattening of the interlayer film is indispensable for forming multilayer and fine wiring. According to the present invention, reduction in inter-wiring capacitance and improvement in processing controllability of fine wiring can be achieved at the same time.

[Comparative Example 2] Next, the required thickness of the third insulating film (low dielectric constant etching stopper) will be described using calculation results. Assuming an adjacent 9 wiring structure in the three-layer wiring as shown in FIG. 4A, the capacitance of the wiring at the center of each wiring was calculated. The effect of the thickness of the second insulating film (the film thickness of the etching stopper) was verified when the wiring height and the wiring depth were constant. FIG. 4B shows the calculation result. As the wiring pitch becomes narrower, the capacity can be reduced even with a thin stopper film thickness. FIG. 4C shows a value obtained by normalizing the thickness of the second insulating film based on these values with the minimum wiring interval. In any of the wiring intervals, the effect of sharply reducing the inter-wiring capacitance is exerted by the time the thickness of the second insulating film reaches the minimum wiring spacing, and when the wiring spacing is more than the minimum wiring spacing, the capacity of 50% or more is obtained. The effect of reduction can be obtained. For example, 0.28
In the case of wiring of um pitch, it is effective to set the stopper film thickness to 0.14 um or more.

[Comparative Example 3] Next, improvement in wiring reliability by increasing the thickness of the third insulating film (low dielectric constant etching stopper) will be described with reference to FIGS. 5 (a) and 5 (b). .

A contact interlayer film 502 and a plug 503 are formed on the upper surface of a lower semiconductor device structure 501 composed of a diffusion layer (not shown), a gate oxide film (not shown), a gate electrode (not shown) and the like, and a contact interlayer film 502 and a plug 503 are formed thereon. Cu 507, which is a conductive material, is formed on the interlayer insulating film composed of the etching stopper film 404 and the fourth insulating film 505 as the lower wiring.
Is formed so that the bottom surface and the side wall are surrounded by a barrier metal 506, for example, a laminated film of Ta / TaN. The wiring layers are composed of a first insulating film 508 (insulating barrier film), a second insulating film 509 (via interlayer film), and a third insulating film 510.
The upper layer wiring is composed of a second low dielectric constant insulating film 511, a conductive barrier film 512, and a Cu film 513.

FIG. 5A shows a defective wiring portion 515 caused by the stress generated in the wiring structure. In particular, stress is likely to be concentrated on the isolated via connection portion connecting the wide wiring, and the probability of disconnection becomes extremely high. The second insulating film is porous, has a low relative dielectric constant, and has a low density.
The fourth insulating film has a relatively high strength, a higher relative dielectric constant than the second insulating film, and a high density. Therefore, the difference in the coefficient of thermal expansion between the second insulating film and the fourth insulating film is large, and the stress in the wiring is strongly generated due to the difference in the coefficient of thermal expansion. That is, the stress is concentrated at the connection portion between the conductive material and the via due to the difference in the expansion coefficient. Since the stress is concentrated in this way, it is necessary to lower the free energy of the system, and it is considered that Cu, which is a conductive material, migrated in search of a more stable structure. Here, the third insulating film has a higher relative dielectric constant than the second insulating film and a lower relative dielectric constant than the fourth insulating film.
By inserting this insulating film between the second insulating film and the fourth insulating film, it becomes possible to reduce the occurrence of disconnection. This is because the difference in the coefficient of thermal expansion becomes stepwise by inserting the third insulating film, the stress is relieved, and the Cu
This is because Cu migration was suppressed by keeping the free energy related to the film low. FIG. 4B shows a cross-sectional view of the wiring when the stress is relieved to the maximum by thickening the insulating film of the third film. A wiring groove is formed inside the third insulating film, which has a lower stress than that of the second insulating film, and the wiring via connection portion is surrounded by the third insulating film, so that concentrated stress is relieved and a disconnection occurs. Can be hardened.

[Embodiment] [Embodiment 1] An embodiment of the present invention will be described with reference to FIG. Here, FIGS. 6 (a) to 6 (g) and FIG. 7 (a)
3B to FIG. 3B are cross-sectional views showing the structure of the semiconductor device and the method of manufacturing the semiconductor device according to the embodiment.

First, as shown in FIG. 6A, the upper surface of a lower semiconductor device structure including a diffusion layer 601 (not shown), a gate oxide film (not shown), a gate electrode (not shown) and the like. A contact interlayer film 602 and a plug 603 are formed on the contact interlayer film 602, a lowermost layer wiring is formed on the contact interlayer film 602, a plug 603, a low dielectric constant insulating film 605, and a silicon oxide film 606.
u608 is formed in a barrier metal, for example, in a laminated film 607 of Ta / TaN so as to surround the bottom surface and side walls.

Here, the low dielectric constant insulating material 605 is organic polysilazane, BCB, polyimide, plasma CF polymer, plasma CH polymer, SiLK (registered trademark),
Teflon (registered trademark) AF, Parylene N (registered trademark),
A parylene AF4 (registered trademark), a film obtained by making polynaphthalene N or the like porous may be used, and for example, ALCAPTM.
There are porous organic silica membranes such as the ™ membrane.
Here, a case where a porous organic silica film ALCAP ™ (registered trademark) film is used is shown.

The conductive material forming the lower layer wiring is Cu, A
It may be g, Al, Ni, Co, W, Si, Ti, Ta and compounds thereof. Here, the case where a conductive material containing Cu as a main component is used is shown. The etching stopper film 604 is made of BCB, SiC, SiN,
It may be SiCN, SiOC, or an insulating thin film containing an organic substance in them.

When the CMP of Cu is performed under general conditions in the art, dishing 609 or erosion (not shown) of about 200Å to 500Å occurs on the formed lower layer Cu wiring.

Subsequently, as shown in FIG. 6B, a first insulating film 61 made of SiCN having a thickness of 500 Å.
0 (insulating barrier film) and a second insulating film 611 (via interlayer film) made of a silicon oxide film having a thickness of 4000Å
PE-CVD (Plasma Enhan
sed Chemical Vapor Deposi
formation) method. At this time, the step 609 of the lower layer wiring is directly transferred and formed on the second insulating film,
A step 612 is formed on the interlayer insulating film.

Then, as shown in FIG. 6 (c),
Subsequently, the second insulating film 611 is flattened and polished. Here, 2500 Å is polished to leave 1500 Å. Since the polishing is for flattening the silicon oxide film, it can be easily performed using a standard polishing liquid based on colloidal silica or the like which is generally used in the art.

Then, as shown in FIG. 6 (d),
A third insulating film (etching stopper film) 613 made of BCB having a thickness of 2000 Å is deposited, and further thereon,
The fourth insulating film 614, the first hard mask 615, the second
Of hard mask 616 is deposited.

At this time, the first hard mask 615 and the second hard mask
Hard mask 616 must be made of different materials, eg SiO2 (second hard mask) / BCB.
(First hard mask), SiN / BCB, SiN / S
Any combination of iO2, SiO2 / SiCN, SiN / SiC, etc. may be used, preferably SiN / SiO.
2, SiO2 / BCB, etc. Further, since the first hard mask 615 also functions as a CMP stopper for Cu, it is desirable that the first hard mask 615 has a low dielectric constant in consideration of the low dielectric constant of the wiring, and SiO2, BCB, or a laminated structure thereof. And so on.

Here, the fourth insulating film 614 is made of a low dielectric constant insulating film material, for example, 2500 Å ALCAP-S.
TM and the first hard mask film 615 is S of 500Å
The iO 2 film and the second hard mask film 616 are 1000 Å SiN films.

Subsequently, as shown in FIG. 6 (e),
The wiring groove pattern is patterned using photoresist, and CH2F2 / Ar is used with the photoresist as a mask.
The second hard mask film 616 made of SiN is etched by using plasma such as / O 2 gas system. After etching the second hard mask film made of SiN, the photoresist is removed by oxygen ashing plasma. At this time, since the first and second hard masks are made of a material having oxygen plasma resistance, deterioration due to damage due to oxygen ashing and shoulder drop of the shape of the hard mask does not occur. In this way, the wiring groove pattern 617 is formed on the hard mask.

Subsequently, as shown in FIG. 6F, a via hole pattern 619 is patterned on the wiring groove pattern 617 by using a photoresist 618. You may expose using an antireflection film as needed.

Subsequently, the via hole pattern is etched, but in order to avoid the thinning of the via diameter which occurs when misalignment occurs between the wiring groove pattern 617 transferred to the SiN film 616 and the via hole pattern 619, First of all, it is very important to etch the second hard mask film 12. The etching conditions at this time are, for example, etching using a gas system composed of CH2F2 / Ar / O2. Then, etching of the first hard mask film 11 made of SiO2 is performed by C5F8 / Ar / O.
Perform at 2.

Subsequently, the second low dielectric constant film 614 is etched. For example, in the case of a porous organic silica film, it can be etched using a gas system composed of C5F8 / Ar / O2. Subsequently, the third insulating film (etching stopper) is etched. Since it is composed of BCB here, it can be etched in a gas system composed of N2 / H2 / CH2F2.

Subsequently, ashing of the via-patterned photoresist 618 is performed with a gas system made of N2 / H2.

Subsequently, as shown in FIG. 6G, a first hard mask film 615 made of a SiO 2 film,
By continuously etching the fourth insulating film 614 and the first hard mask 615 and the fourth insulating film 61.
A groove penetrating 4 and reaching the inside of the third insulating film is formed, and at the same time, the second insulating film (via interlayer film) is also etched. Subsequently, the first insulating film (insulating barrier film) 610 is etched to form the dual damascene wiring (DDI) wiring groove 6
Form 20.

As shown in FIG. 7A, a conductive barrier metal film 621 and a Cu film 621 having a Ta / TaN laminated structure of, for example, 300 liters are deposited, and excess Cu and the barrier metal film are polished by the CMP method. Remove by. In this way, the dual damascene wiring connected to the lower layer wiring is formed.

After that, as shown in FIG. 7B, the above-described steps are repeated for the required wiring layers to obtain a multilayer wiring structure. [Embodiment 2] An embodiment of the present invention will be described with reference to FIG. Here, FIGS. 8A to 8G and FIGS. 9A to 9D are cross-sectional views showing the structure of the semiconductor device and the method of manufacturing the semiconductor device according to the embodiment.

First, as shown in FIG. 8A, an upper surface of a lower semiconductor device structure including a diffusion layer 701 (not shown), a gate oxide film (not shown), a gate electrode (not shown), and the like. A contact interlayer film 702 and a plug 703 are formed on the contact interlayer film 702, and the lowermost layer wiring is formed on the contact interlayer film 702, the low dielectric constant insulating film 705, and the silicon oxide film 706 as a conductive material.
u708 is formed in a barrier metal, for example, in a laminated film 707 of Ta / TaN so as to surround the bottom surface and side walls.

Here, the low dielectric constant insulating material 705 is organic polysilazane, BCB, polyimide, plasma CF polymer, plasma CH polymer, SiLK (registered trademark),
Teflon (registered trademark) AF, Parylene N (registered trademark),
A parylene AF4 (registered trademark), a film obtained by making polynaphthalene N or the like porous, or the like may be used. The conductive material forming the lower layer wiring is Cu, Ag, Al, Ni, Co, W, Si, T
i, Ta and these compounds may be used, and here C
The case where u is the main component is shown. The etching stopper film 704 is composed of BCB, SiC, SiN, SiCN,
It may be SiOC or an insulating thin film containing an organic substance.

When the CMP of Cu is performed under the general conditions in the art, dishing 709 and erosion (not shown) of about 200Å to 500Å occur on the formed lower layer Cu wiring.

Then, as shown in FIG.
The first insulating film 710 (insulating barrier film) made of 00Å SiCN and the second insulating film 711 (via interlayer film) made of a silicon oxide film having a thickness of 4000Å are both PE-CVD (Plasma Enhanced Che).
It is formed by the method of "Metal Vapor Deposition". At this time, the step 709 of the lower wiring is directly transferred and formed on the second insulating film, and the step 712 on the interlayer insulating film is formed.

Subsequently, as shown in FIG. 8 (c),
Subsequently, the second insulating film 711 is flattened and polished. Here, 2500 Å is polished to leave 1500 Å. Since the polishing is for flattening the silicon oxide film, it can be easily performed using a standard polishing liquid based on colloidal silica or the like which is generally used in the art.

Then, as shown in FIG. 8 (d),
A third insulating film (etching stopper film) 713 made of BCB having a thickness of 2000 Å is deposited, and further thereon.
The fourth insulating film 714, the first hard mask 715, the second
Of hard mask 716 is deposited.

At this time, the first hard mask 715 and the second hard mask 715
Hard mask 716 must be made of a different material, eg SiO 2 (second hard mask) / BCB.
(First hard mask), SiN / BCB, SiN / S
Any combination of iO2, SiO2 / SiCN, SiN / SiC, etc. may be used, preferably SiN / SiO.
2, SiO2 / BCB, etc. Further, since the first hard mask 715 also functions as a CMP stopper for Cu, it is desirable that the first hard mask 715 has a low dielectric constant in consideration of the low dielectric constant of the wiring, and SiO2, BCB, or a laminated structure thereof. And so on.

Here, the fourth insulating film 714 is made of a low dielectric constant insulating film material, for example, 2500 Å ALCAP-S.
TM and the first hard mask film 715 is S of 500Å
The iO 2 film and the second hard mask film 716 are 1000 Å SiN films.

Then, as shown in FIG. 8 (e),
The wiring groove pattern is patterned using photoresist, and CH2F2 / Ar is used with the photoresist as a mask.
The second hard mask film 716 made of SiN is etched by using plasma such as / O 2 gas system. After etching the second hard mask film made of SiN, the photoresist is removed by oxygen ashing plasma. At this time, since the first and second hard masks are made of a material having oxygen plasma resistance, the deterioration due to damage due to oxygen ashing and the shoulder drop of the hard mask shape does not occur. In this way, the wiring groove pattern 717 is formed on the hard mask.

Then, as shown in FIG. 8F, a via hole pattern 719 is patterned on the wiring groove pattern 717 by using a photoresist 718. If necessary, an antireflection film may be used for exposure.

Subsequently, the via hole pattern is etched, but in order to avoid the thinning of the via diameter, which occurs when misalignment occurs between the wiring groove pattern 717 transferred to the SiN film 716 and the via hole pattern 719, First of all, it is very important to etch the second hard mask film 716. The etching conditions at this time are, for example, etching using a gas system composed of CH2F2 / Ar / O2. Then the first made of SiO2
Of the hard mask film 715 of C5F8 / Ar
/ O2.

Subsequently, the second low dielectric constant film 714 is etched. For example, in the case of porous MSQ, C5F is used.
It can be etched using a gas system composed of 8 / Ar / O 2. Subsequently, the third insulating film (etching stopper) is etched. Since it is composed of BCB here, it can be etched in a gas system composed of N2 / H2 / CH2F2.

Subsequently, the photoresist 716 subjected to the via patterning is ashed by a gas system composed of N2 / H2.

Subsequently, as shown in FIG. 8G, a first hard mask film 715 made of a SiO 2 film,
By continuously etching the fourth insulating film 714 and the fourth insulating film 714, the first hard mask 715 and the fourth insulating film 71 are formed.
A groove penetrating 4 and reaching the inside of the third insulating film is formed, and at the same time, the second insulating film (via interlayer film) is also etched. Subsequently, the first insulating film (insulating barrier film) 713 is etched, and the dual damascene wiring (DDI) wiring groove 7 is formed.
Form 20.

As shown in FIG. 9A, after depositing a conductive barrier metal film 721 of, for example, 300 Å having a Ta / TaN laminated structure, then, as shown in FIG. 9B,
The conductive barrier metal film deposited on the bottom of the via is removed by RF etching. At the same time, the barrier metal at the bottom of the wiring groove is also removed, and the conductive barrier metal film remains only on the side wall of the via hole and the side wall of the wiring groove. Continuing with FIG.
As shown in (c), the dual damascene wiring 72 is formed by embedding Cu in the dual damascene wiring groove and polishing it.
Form 2. Thus, the connection 723 in which the lower layer wiring and the via hole are Cu / Cu-connected without the barrier metal layer interposed is obtained.

After that, as shown in FIG. 9D, a multilayer wiring structure can be obtained by repeating the above-mentioned steps for necessary wiring layers. According to the present invention, a dual dielectric material having a low dielectric constant is used. The damascene wiring structure can be easily formed, and it is possible to simultaneously reduce the capacitance between wirings and control the workability of fine wiring.

Further, the wiring structure according to the present invention does not necessarily have to be used for all layers as long as it is used for at least one layer in a multilayer wiring structure.

The present invention is not limited to the above-described embodiment (or example), and the semiconductor integrated circuit of the embodiment according to the present invention can be appropriately modified within the scope of the technical idea of the present invention. In the above, a silica-based film having organic and pores is illustrated as an interlayer film, but if a similar structure can be obtained, it can be used without being limited to any process. Further, the low dielectric constant film serving as the wiring interlayer film does not necessarily have to be a single layer film, and may be a different type of multilayer film.

Further, according to the present invention, since it is possible to reduce the dielectric constant of the via portion and flatten the via interlayer film, the organic and vacant regions having a relative dielectric constant of 2.5 or less can be provided especially to the wiring portion. It is very effective to form an integrated circuit with high precision in a finer multilayer wiring using a so-called porous material having As the film having a dielectric constant lower than that of the silicon oxide film, ALCAP (trade name of a chemical substance manufactured by Asahi Kasei Co., Ltd.) composed of an organic silica compound can be used. ALCAPTM is A
advanced Metallization Conf
It can be formed using a publicly known technique such as that described in the erence (AMC) 2000.171 page. A mixed solution of silica sol in which a polymer and a solvent are mixed is obtained and spin-on coated on a silicon wafer at room temperature. Then, the solvent is removed at 120 to 200 ° C. to cause the reaction of the sol. The spacer is removed by further heating to 400 ° C. The ALCAPTM film is formed through such a process. The thickness of the ALCAP ™ film is determined by the spin speed and spin coating process. Final permittivity is 1.7-2.7
It will be about.

[0113]

As described above, according to the present invention,
In a multi-layer wiring structure using a low dielectric constant film as an interlayer insulating film, a dual damascene wiring structure using a low dielectric constant insulating material can be easily formed, reducing inter-wiring capacitance and improving wiring reliability. In addition, the yield of fine wiring can be improved at the same time.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a wiring structure for explaining a first embodiment of the present invention in the order of manufacturing steps.

FIG. 2 is a cross-sectional view in order of manufacturing steps of a wiring structure for explaining a second embodiment of the present invention.

FIG. 3 is a cross-sectional view of a wiring structure for explaining Comparative Example 1 of the present invention.

FIG. 4 is a sectional view of a wiring structure for explaining a comparative example 2 of the present invention.

FIG. 5 is a sectional view of a wiring structure for explaining a comparative example 3 of the present invention.

FIG. 6 is a cross-sectional view in order of the manufacturing steps of the multilayer wiring structure for explaining the first embodiment of the present invention.

FIG. 7 is a cross-sectional view in the manufacturing process order of the multilayer wiring structure for explaining the continuation of the above process.

FIG. 8 is a cross-sectional view in order of manufacturing steps of a multilayer wiring structure for explaining a second embodiment of the present invention.

FIG. 9 is a cross-sectional view in the manufacturing process order of the multilayer wiring structure for explaining the continuation of the above process.

FIG. 10 is a cross-sectional view in order of manufacturing steps of a wiring structure in Conventional Example 1 for explaining a conventional technique.

FIG. 11 is a cross-sectional view in order of manufacturing steps of a wiring structure in Conventional Example 2 for explaining a conventional technique.

FIG. 12 is a cross-sectional view of the wiring structure in Conventional Example 2 in order of manufacturing steps for explaining the continuation of the above steps.

[Explanation of symbols]

101 Lower semiconductor device structure 102 Contact interlayer film 103 plug 104 Etching stopper film 105 Low dielectric constant film 106 barrier metal 107 Cu 108 First insulating film 109 second insulating film 110 Third insulating film 111 Fourth insulating film 112 dual damascene wiring groove 113 conductive barrier film 114 Cu film 115 dual damascene wiring

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Kenichiro Tateoka             5-7 Shiba 5-1, Minato-ku, Tokyo NEC Corporation             Inside the company (72) Inventor Hiroto Otake             5-7 Shiba 5-1, Minato-ku, Tokyo NEC Corporation             Inside the company (72) Inventor Yoshihiro Hayashi             5-7 Shiba 5-1, Minato-ku, Tokyo NEC Corporation             Inside the company F term (reference) 5F033 HH03 HH11 HH18 HH19 HH21                       HH32 HH33 HH34 JJ03 JJ11                       JJ18 JJ19 JJ21 JJ32 JJ33                       JJ34 KK03 KK07 KK08 KK11                       KK14 KK15 KK18 KK19 KK21                       KK32 MM01 MM02 MM10 MM12                       MM13 NN05 NN06 NN07 QQ02                       QQ08 QQ09 QQ10 QQ25 QQ28                       QQ37 QQ48 RR01 RR03 RR05                       RR06 RR21 RR23 RR24 RR29                       SS15 SS22 TT02 TT03 TT04                       XX01 XX15 XX24 XX28

Claims (5)

[Claims] 1. In a structure of a multi-layer wiring formed on an insulating film on a semiconductor substrate, a first insulating film that is in direct contact with a lower conductive material, and unevenness of the lower wiring provided on the first insulating film. A via hole formed in a via insulating film formed of a flat independent second insulating film and a third insulating film which is a stress relaxation layer having a low dielectric constant provided on the second insulating film; A wiring groove that penetrates the fourth insulating film formed on the third insulating film and reaches the inside of the third insulating film is formed, and a conductive material is embedded in the wiring groove and the via hole. Wiring structure characterized by 2. A groove in which a fifth insulating film is formed on the fourth insulating film, the groove penetrating the fourth insulating film and the fifth insulating film and reaching the inside of the third insulating film. Is formed,
The wiring structure according to claim 1, wherein a conductive material is embedded in the groove. 3. The relative dielectric constant of the third insulating film is smaller than the relative dielectric constant of the second insulating film and larger than the relative dielectric constant of the fourth insulating film. The wiring structure according to claim 2. 4. The thickness of the third insulating film is equal to or more than the minimum wiring interval of the upper layer wiring.
The wiring structure according to claim 2 or 3. 5. The connecting portion between the lower layer wiring containing Cu as a main component of the conductive material and the via hole does not have an interface layer containing a metal other than Cu as a main component, and the third insulating film has a function of Cu against Cu.
The wiring structure according to claim 1, which has diffusion resistance.