JP2003303880A5 - - Google Patents

Claims (8)

In a multilayer wiring structure formed on an insulating film on a semiconductor substrate, a first insulating film that is in direct contact with a lower layer conductive material and a flat first layer that is provided on the first insulating film and does not depend on the unevenness of the lower layer wiring. A via hole formed in a via insulating film formed from the insulating film of 2 and a third insulating film that is a low dielectric constant stress relaxation layer provided on the second insulating film; and a third insulating film A wiring groove that penetrates through the fourth insulating film formed above and reaches the inside of the third insulating film is formed, and a conductive material is embedded in the wiring groove and the via hole. Wiring structure.   A fifth insulating film is formed on the fourth insulating film, and a groove that penetrates the fourth insulating film and the fifth insulating film and reaches the inside of the third insulating film is formed. The wiring structure according to claim 1, wherein a conductive material is embedded in the groove.   3. The relative dielectric constant of the third insulating film is smaller than that of the second insulating film and larger than that of the fourth insulating film. Wiring structure. The second insulating film is a low dielectric constant insulating film mainly composed of siloxane;
  The third insulating film is an insulating film selected from a divinylsiloxane benzocyclobutene (BCB) film, an aromatic or siloxane-containing organic polymer film, or an organic siloxane film;
  The fourth insulating film is a hydrogen silsesquioxane (HSQ) film, a methyl silsesquioxane (MSQ) film, a BCB film, an aromatic porous polymer film, a porous organic silica film, or an Si-H film. Bond, Si-CH ₃ The wiring structure according to claim 3, wherein the wiring structure is an insulating film selected from a porous silica film containing either a bond or a Si—F bond. 5. The wiring structure according to claim 4, wherein the third insulating film is a BCB film. 6. The wiring structure according to claim 1, wherein the thickness of the third insulating film is equal to or greater than the minimum wiring interval of the upper layer wiring. In the connection portion between the lower wiring and the via hole whose main component is Cu as a conductive material, there is no interface layer whose main component is a metal other than Cu, and the third insulating film has resistance to diffusion against Cu. The wiring structure according to claim 1, wherein the wiring structure is a wiring structure. A semiconductor device having a multilayer wiring on a semiconductor substrate, wherein at least a part of the multilayer wiring has the wiring structure according to claim 1.