JP2003243503A - Method of forming through hole and method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To form through holes with a good shape and low electric resistance without deteriorating a lower interconnection layer and an insulation film. <P>SOLUTION: A method of forming the through holes comprises processes of (a) forming a resist pattern on the insulation film by photolithography, (b) forming the through holes by dry-etching the insulation film according to the resist pattern, (c) removing the resist pattern by dry-etching, and (d) removing a polymer residue in the through holes by dry-etching. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a through hole for electrically connecting multi-layer wiring in a semiconductor device having multi-layer wiring and a method of manufacturing a semiconductor device using the method.

[0002]

2. Description of the Related Art A conventional semiconductor device having multilayer wiring is
Usually, a structure in which a wiring layer is sandwiched by a plasma oxide film is adopted. The process flow of such a semiconductor device will be described in detail below with reference to FIG. The first plasma TEOS oxide film 32 and the first plasma TEOS oxide film 32 are formed on the semiconductor substrate 31.
The aluminum-based metal wiring 33 is sequentially formed. Next, the second plasma TEOS oxide film 3 is formed on the obtained substrate.
4 is formed to a thickness of about 1000Å, and the organic SOG film 35 is further applied and baked to form a thickness of about 4000Å.
Next, a third plasma TEOS oxide film 36 is formed on the organic SOG film 35 to a thickness of about 8000Å, and then chemical mechanical polishing is performed on the surface of the organic SOG film 35 for about 5000Å.

Next, in order to open the through hole, a photoresist is applied, exposed and developed to perform patterning, and then the through hole is etched using a fluorocarbon gas with the photoresist pattern as a mask. . Next, the photoresist pattern is removed by using oxygen plasma. The conditions are as follows: gas flow rate O ₂ : ₂ slm, power: 1000 W, processing temperature: 25
Adjusted to 0 ℃, lamp power: 25%, peeling speed: 1
Get 2000Å / min.

Next, as the first connecting metal, the thickness is about 50.
0Å titanium film 37, 500Å thick titanium nitride film 3
8. Blanket tungsten film 3 with a thickness of about 5000Å
After forming 9 sequentially, etch back. Next, the second aluminum-based metal wiring 30 is connected to the third plasma TEOS.
It is formed on the oxide film 36 in a region including a through hole. In the manufacturing process of such a semiconductor device, since oxygen plasma is used in the step of removing the photoresist pattern at the time of processing the through hole, the Si—CH ₃ bond of the organic SOG film 35 is easily broken by O ₂ and Si— O
Form H-bonds. Since the Si—OH bond becomes a source of moisture absorption, the electric resistance in the through hole becomes high, which also causes a rise in the dielectric constant. Therefore, the first and second aluminum-based metal wirings have a problem of poor connection.

An example of using a fluororesin as an interlayer insulating film having a low dielectric constant is a monthly paper "Semiconductor Worl".
d "(February 1997), pages 82-84. Here, it is stated that "the etching property for lowering the dielectric constant by the fluororesin is clear, and the problem is oxygen plasma resistance." The process flow of the semiconductor device when fluororesin is used as the interlayer insulating film will be described below with reference to FIG.

First, a first plasma TEOS oxide film 42 and a first aluminum-based metal wiring 43 are sequentially formed on a semiconductor substrate 41. The second plasma T is formed on the obtained substrate.
An EOS oxide film 44 is formed to a thickness of about 500Å, and a fluororesin 45 is further applied and baked to form a thickness of about 5000Å. Next, a third plasma TEOS oxide film 46 is formed on the fluororesin 45 to a thickness of about 8000 Å, and then chemical mechanical polishing is performed on the 5,000 Å for planarization.

Next, for opening a through hole, a photoresist is applied, exposed and developed to perform patterning. Then, using the photoresist pattern as a mask, a sandwich film composed of the second plasma TEOS oxide film 44, the fluororesin film 45, and the third plasma TEOS oxide film 46 is etched using a fluorocarbon-based gas to form a through hole. To do. Next, the photoresist pattern is removed by oxygen plasma under the same conditions as in the conventional example. In the manufacturing process of such a semiconductor device, the hole 47 in the second plasma TEOS oxide film 44 is processed into a straight linear shape, but the hole 48 in the fluororesin film 45 is processed into a bowing shape. It is considered that the reason why the hole 48 has a bowing shape is that carbon of the fluororesin film 45 and oxygen of oxygen plasma are combined and released in the form of CO ₂ gas.

On the other hand, JP-A-11-150101
In the publication, there is proposed a method of removing the photoresist pattern by plasma using NxHy (x = 1, 2, y = 2-4) gas. According to this method,
Since oxygen plasma is not used, it is possible to prevent the insulating film from becoming hygroscopic and prevent the holes in the insulating film from becoming bowed. In any of the above methods, after removing the photoresist pattern, the polymer remaining on the upper part of the hole and inside the hole is removed with a cleaning liquid for semiconductor devices (hereinafter, referred to as “chemical liquid”), and the chemical liquid is rinsed with pure water. Is being done.

However, in such a method, the polymer residue inside the hole is not sufficiently removed by the chemical treatment, or the chemical inside the hole is not sufficiently removed by pure water, so that the high electric resistance component is present at the bottom of the hole. Will remain. As a result, there is a problem that the electric resistance in the through hole becomes high. In addition, the chemicals used so far have high costs required for purchase and disposal, which poses a problem for cost reduction of semiconductor devices.

Further, in recent years, the gap between adjacent gates (polysilicon) has become smaller and smaller with the further miniaturization of semiconductor elements. As a result, the dimensional accuracy of lithography for forming the contact hole opening is further required. However, because the dimensional accuracy of lithography is limited,
There is an increasing demand for through hole formation processes that can tolerate misalignment. In addition, misaligned through holes (hereinafter referred to as "borderless through holes")
Usually has a problem that the electric resistance in the through hole increases and the resistance value varies up to about 5 to 10 times.

[0011]

As described above, regarding the method of removing the photoresist pattern in forming the through hole, there have been improvements to prevent the deterioration of the insulating film. Regarding the cleaning method, various problems such as side reaction between the chemical solution and the wiring pattern and insufficient removal of the chemical solution after cleaning remain unresolved. Further, as the miniaturization of semiconductor integrated circuits progresses, the miniaturization of the hole size also progresses, and when new interlayer insulating films, wiring materials and etching gases are used, there will be a new cleaning method inside holes using chemicals. It is expected that various problems will occur.

For example, a fluorine-doped silicon oxide film (hereinafter referred to as “FHDP film”) is used as an interlayer insulating film,
The FHDP film is dry-etched using the photoresist pattern as a mask to form a through hole, the photoresist pattern is removed by dry etching using oxygen plasma, and the polymer remaining on the top and inside of the hole is washed with a chemical solution. If so, there are many possibilities that borderless through holes are formed. As a result of earnest studies in view of such a situation, the present inventor removes the polymer remaining on the upper part and the inside of the hole by dry etching with a plasma containing carbon fluoride and a trace amount of hydrogen without using a chemical solution. By the method, it was found that the electric resistance in the through hole can be suppressed to be low even when the borderless through hole is formed, and the present invention has been completed.

[0013]

Thus, according to the present invention, (a) the step of forming a resist pattern on the insulating film by photolithography, and (b) the dry etching of the insulating film based on the resist pattern are performed. Provided is a method of forming a through hole, which includes the steps of forming a through hole, (c) removing a resist pattern by dry etching, and (d) removing a polymer residue in the through hole by dry etching. It Further, according to the present invention, there is provided a method of manufacturing a semiconductor device using the above method.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, the present invention will be described more specifically with reference to Examples, but the present invention is not limited thereto. Example A manufacturing process of a semiconductor device according to the method of the present invention will be described with reference to FIG. First, the semiconductor substrate 1
As the first insulating film 5 on the silicon substrate as a substrate, for example, a SiOC film, a SiOF film, a Si film by a thermal oxidation method, a CVD method or the like
An N film or the like is appropriately selected and formed.

The semiconductor substrate is not particularly limited as long as it is usually used in a semiconductor device. For example, an elemental semiconductor substrate of silicon, germanium or the like, G
Various substrates such as a substrate made of a compound semiconductor such as aAs or InGaAs, an SOI substrate, or a multi-layer SOI substrate can be used. Of these, a silicon substrate is preferable.
Further, the semiconductor substrate may be formed by combining semiconductor elements such as transistors and capacitors, circuits, wiring layers, element isolation regions, insulating films, etc. on the surface thereof. Further, the semiconductor substrate is usually doped with p-type impurities such as boron or n-type impurities such as phosphorus and arsenic, and one or more n-type or p-type impurity diffusion regions (wells) are formed on the surface thereof. Are formed. The impurity concentration, size, depth, etc. of the well can be appropriately adjusted in consideration of the performance of the semiconductor device to be obtained. As a result, the semiconductor substrate has regions of both the first conductivity type and the second conductivity type. A second conductivity type channel MOS transistor may be formed on the first conductivity type region, and a first conductivity type channel MOS transistor may be formed on the second conductivity type region.

In this embodiment, a device isolation film 2, a source / drain region 3 and a gate electrode 4 are formed on a silicon substrate to form a MOSFET. As the first insulating film,
The film formed of a silicon oxide film, a silicon nitride film, or a laminated film of these films with a film thickness of about 20 to 50 Å can be cited. The method for forming the first insulating film is appropriately selected according to the material, and examples thereof include a thermal oxidation method, a CVD method, a sputtering method, a vapor deposition method and the like. A contact hole 6 is formed in the first insulating film so that the gate electrode 4 and the source / drain region 3 are electrically connected to a lower wiring layer 7 described later.
Is formed.

Next, a titanium nitride film as the lower wiring layer 7 is formed on the first disconnection film 5. In addition to the titanium nitride film, the lower wiring layer is, for example, a metal such as gold, platinum, silver, copper, or aluminum; a refractory metal such as titanium, tantalum, or tungsten; a silicide with a refractory metal, a single-layer film such as polycide. Alternatively, a laminated film can be formed to have a film thickness of about 100 to 500 Å. The lower wiring layer is formed of, for example, a conductive material by a CVD method, a sputtering method, an evaporation method, or the like.
It is formed by forming a film on the entire surface of the insulating film and then patterning it into a desired shape by a known method such as photolithography and etching.

Next, the second insulating film 8 is formed on the obtained wafer.
As a result, a fluorine-doped silicon insulating film (FHDP film) is formed. The second insulating film may be, for example, a silicon oxide film [low temperature oxide film: LTO film, high temperature oxide film: other than the FHDP film.
HTO film, plasma TEOS (Tetra-Ethoxy Silane)
Film], silicon nitride film or plasma nitride film, PSG film,
BSG film, BPSG film, SOG film, fluororesin film, HS
Q film, amorphous carbon film, fluorinated amorphous carbon film, porous film, etc.
It is formed to about 10,000 Å. The method for forming the second insulating film is appropriately selected according to the material thereof, and examples thereof include a thermal oxidation method, a CVD method, a sputtering method, and a vapor deposition method.

Next, by photolithography, the second
A photoresist is formed on the insulating film 8 and patterned (step a). The photoresist pattern is not particularly limited as long as it has a shape having an opening above the lower wiring layer to form a through hole, and can be formed in a desired shape. Then, based on the photoresist pattern,
A through hole is formed by dry etching the second insulating film 8 (step b). The dry etching performed in step b may be any of vapor phase etching, plasma etching, sputter etching, reactive ion etching (RIE), ion beam etching and photo etching. Among them, RIE, sputter etching, and ion beam etching, which have anisotropy, are preferable because the through holes are formed in a straight line shape.

The apparatus used for dry etching may be a batch type or a single wafer type, and an ECR plasma apparatus, an inductively coupled plasma apparatus, and a helicone excitation type plasma apparatus can be used. As the etching gas,
It is appropriately selected depending on the material to be etched. For example, in the case of silicon oxide, CHF ₃ , CF ₄ , C ₂ F ₆ , C ₄ F ₈ ,
Examples include C ₅ F _{8 and the} like, CHF ₃ and CF ₄ and the like in the case of silicon nitride, and Cl ₂ , HBr, BCl _{3 and the} like in the case of polycide. Further, the etching gas is CO, O ₂ , Ar.
Other gases, such as, may be added.

In this embodiment, the wafer obtained in the previous step is set on the wafer mounting electrode of the dry etching apparatus. The electrode has a built-in cooling pipe, and by supplying and circulating a suitable refrigerant from a cooling facility such as a chiller installed outside the apparatus to the cooling pipe, the wafer being etched can be maintained at a predetermined temperature. It
Here, the electrode is maintained at 20 ° C. next,
Based on the photoresist pattern, C ₅ F ₈ flow rate: 16
sccm, CO flow rate: 50 sccm, O ₂ flow rate: 17 s
ccm, Ar flow rate: 330 sccm, gas pressure: 15 m
T, upper electrode power: 1800W, lower electrode power: 1
The FHDP film is dry-etched under the condition of 800 W. The supply amount of each gas and its mixing ratio are appropriately adjusted by a controller (not shown) and a mass flow controller.

In this step, F radicals are generated in the plasma by the discharge dissociation of C ₅ F ₈ . Then, the F radicals cause etching to proceed by a mechanism in which radical reactions are assisted by ions such as CFx +, C +, and FSG.
Are removed in the form of SiFx, CO ₂ , COF, etc. At this time, the etching rate is about 600 nm / min.
Next, the photoresist pattern is removed by dry etching (step c). The dry etching performed in step c is gas phase etching, plasma etching,
Any of sputter etching, RIE, ion beam etching and photo etching may be used. Among them, since it is easy to remove the photoresist pattern formed in a wide range by etching, it has isotropic vapor phase etching,
Plasma etching and photo etching are preferred, and isotropic plasma etching is more preferred.

The apparatus used for dry etching may be either a batch type or a single-wafer type, and an ECR plasma apparatus, an inductively coupled plasma apparatus, a helicone excitation type plasma apparatus can be used. As the etching gas,
Examples thereof include O ₂ gas and hydrogen nitride-based gas. Further, other gases such as CO and Ar may be added to the etching gas.

In this embodiment, the wafer obtained in the previous step is transferred to the plasma ashing apparatus shown in FIG. 2 and the photoresist pattern is removed by using O ₂ plasma ashing. Removal of the photoresist pattern is primarily based on decomposition by burning and heating. Here, for the purpose of relaxing the thermal curing of the polymer component, the treatment was carried out at a lower temperature (20 to 100 ° C.) as compared with the usual O ₂ plasma ashing condition.

Next, the polymer residue in the through hole is removed by dry etching (step d). The dry etching performed in step d is vapor phase etching,
Any of plasma etching, sputter etching, RIE, ion beam etching and photo etching may be used. Among them, RIE, sputter etching, and ion beam etching having anisotropy are preferable because the polymer residue in the through hole is easily removed and the side wall of the through hole is not etched, and anisotropic RIE is more preferable.

The apparatus used for dry etching may be either a batch type or a single wafer type, and an ECR plasma apparatus, an inductively coupled plasma apparatus, and a helicone excitation type plasma apparatus can be used. As the etching gas,
It is appropriately selected depending on the material to be etched. For example, in the case of silicon oxide, CHF ₃ , CF ₄ , C ₂ F ₆ , C ₄ F _8, etc .; in the case of silicon nitride, CHF ₃ , CF ₄ etc .; , Cl ₂ , HBr, BCl _{3 and the} like.
Further, other gases such as H ₂ , N ₂ , O ₂ and Ar may be added to the etching gas. Above all, it is preferable to use an etching gas containing CF ₄ and H ₂ .

In this embodiment, CF ₄ flow rate: 125
sccm (gas flow ratio to the total etching gas 31
%), N ₂ gas containing 3 vol% H ₂ : flow rate 275 scc
Dry etching is performed under the conditions of m, gas pressure: 0.2 Torr, and electrode power: 260 W to completely remove the residual polymer on the upper part of the hole and inside the hole. The removal of the residual polymer is based on the ionization of the polymer component by applying energy by RIE.

By changing the CF ₄ gas flow rate ratio from 12% to 38% with respect to the total gas flow rate, the reduction amount of the titanium nitride film as the lower wiring layer and the presence / absence of the polymer residue on the upper part of the hole were determined. Was observed. As a result, CF ₄
When the gas flow rate ratio was 12% to 25%, it was observed that the polymer component on the upper portion of the hole remained, but the film reduction of the lower wiring layer was not observed. Further, it was observed that the polymer component on the upper part of the hole was completely removed by increasing the flow rate ratio of CF ₄ gas, but the lower wiring layer was etched by about 200Å when the flow rate ratio became 38%.

From the above results, the CF ₄ gas flow rate ratio is preferably between 26 and 37% with respect to the total gas flow rate because there is no polymer residue and the film loss of the lower wiring layer can be suppressed. More preferably about 27-35%. Next, the wafer is washed with deionized water to form through holes in the FHDP film. next,
A thickness of about 500 is formed as a first connecting metal on the second insulating film 8.
Å Titanium film 9, approximately 500 Å Titanium Nitride film 10,
After a tungsten film 11 having a thickness of about 3000 Å is sequentially formed, it is etched back.

Examples of the connecting metal include a titanium film, a titanium nitride film, and a tungsten film, as well as a single layer film or a laminated film of the material used for the lower wiring layer. Next, as the upper wiring layer 12, for example, a titanium film, a titanium nitride film,
A laminated film of Al—Cu curtain is formed on the second insulating film 8 in a region including the through hole. The material and forming method of the upper wiring layer are the same as those of the lower wiring layer, and the upper wiring layer is formed to have a film thickness of about 3000 to 10000Å. A semiconductor wafer having through holes formed by the above method is shown in FIG. According to this example, a high selection ratio of 50 with respect to the lower wiring layer when the FHDP film as the second insulating film was etched was obtained.

Comparative Example A photoresist pattern was formed into a conventional (for example, high temperature (about 250 ° C.) / Single oxygen gas as compared with the present invention) O ₂ gas.
A semiconductor wafer is manufactured in the same manner as in the example except that it is removed by dry etching using plasma and the polymer residue is removed using a chemical solution containing an alkaline aqueous solution and an organic solvent.

<Comparison between Example and Comparative Example> The electrical characteristics in the through holes formed in the example and the comparative example were compared. 5 and 6 show the electric resistance in the through holes formed in the examples and the comparative examples. FIG. 5 shows the electric resistance in the through hole when the through hole completely overlaps the lower wiring layer. In this case, the examples and comparative examples showed similar electrical resistance.

FIG. 6 shows the electric resistance in the through hole (borderless through hole) when the through hole does not completely overlap the lower wiring layer. In this case, the electrical resistance of the comparative example is 1.
It has a high resistance of 5 to 5 times. For this cause,
In the case of the through hole formed in the comparative example, since the residual polymer component inside the through hole is not completely removed,
It is considered that this residual polymer component increases the electric resistance. Further, regarding the through holes formed in the examples and the comparative examples, after removing the residual polymer, S from the upper surface is removed.
As a result of measuring the hole diameter by EM observation, no difference was observed between the two hole diameters. From this, it was found that the insulating film was not deteriorated by the removal of the residual polymer in the method of the present invention.

[0034]

As described above, according to the method of the present invention,
By removing the polymer residue in the through hole by dry etching, the electric resistance in the through hole can be suppressed low. Further, a through hole having a good shape can be formed without causing deterioration in the lower wiring layer and the insulating film. These effects are particularly noticeable when a borderless through hole is formed. Also,
According to the method of the present invention, since the polymer residue in the through hole is removed by dry etching without using a chemical, it is expected that the amount of harmful substances used can be suppressed and the cost can be reduced.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view of a semiconductor wafer manufactured by the method of the present invention.

FIG. 2 is a schematic cross-sectional view of a plasma ashing device used in an example.

FIG. 3 is a schematic cross-sectional view of a semiconductor wafer manufactured by a conventional method.

FIG. 4 is a schematic cross-sectional view of a semiconductor wafer manufactured by a conventional method.

FIG. 5 is a graph showing electric resistance in through holes formed in Examples and Comparative Examples.

FIG. 6 is a graph showing the electric resistance in the borderless through hole formed in the example and the comparative example.

[Explanation of symbols]

1 Semiconductor substrate 2 element isolation film 3 Source / drain region 4 gate electrode 5 First insulating film 6 contact plugs 7 Lower wiring film 8 Second insulating film 9 Titanium film 10 Titanium nitride film 11 Tungsten film 12 Second metal wiring layer 31 Semiconductor substrate 32 First TEOS oxide film 33 First Aluminum Metallic Wiring 34 Second TEOS oxide film 35 Organic SOG film 36 Third TEOS oxide film 37 Titanium film 38 Titanium nitride film 39 Blanket tungsten film 30 Second aluminum-based metal wiring 41 Semiconductor substrate 42 First TEOS oxide film 43 First Aluminum Metal Wiring 44 Second TEOS oxide film 45 Fluororesin film 46 Third TEOS oxide film 47 Through hole linearly formed 48 Through hole formed in the shape of a bow

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Claims (6)

[Claims] 1. A process of forming a resist pattern on an insulating film by photolithography, a process of forming a through hole by dry etching the insulating film based on the resist pattern, and a process of forming a through hole. A method of forming a through hole, comprising: a step of removing a resist pattern by dry etching; and (d) a step of removing a polymer residue in the through hole by dry etching. 2. The dry etching in step d is C
The method for forming a through hole according to claim 1, wherein the method is performed using an etching gas containing F ₄ and H ₂ . 3. CF ₄ is contained in the etching gas in an amount of 26 to
The method of forming a through hole according to claim 2, wherein the gas flow rate ratio is 37%. 4. The method of forming a through hole according to claim 1, wherein the dry etching in step c is performed by isotropic plasma etching, and the dry etching in step d is performed by anisotropic RIE. 5. The method for forming a through hole according to claim 1, wherein the insulating film is a fluorine-doped silicon oxide film. 6. A method of manufacturing a semiconductor device, which uses the method of forming a through hole according to claim 1. Description: