JP4745370B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method of manufacturing a semiconductor device including upper and lower wirings connected to each other through contact holes and an interlayer insulating film that insulates the wirings from each other.

  In order to realize a high-speed device in a logic device after the sub-quarter micron generation, it is important to reduce the signal delay of the device. The signal delay of the device is represented by the sum of the delay in the transistor and the delay in the wiring. However, as the wiring pitch is reduced, the influence of the signal delay in the wiring is larger than the signal delay in the transistor. Since the signal delay in the wiring is proportional to the product of the resistance of the wiring and the capacitance of the interlayer insulating film, to reduce this, it is necessary to reduce the wiring resistance or the interlayer insulating film capacitance.

  As one of attempts to achieve the object, for example, research on the formation of copper wiring has been actively conducted. This is because a further decrease in wiring resistance can be expected by using copper as the wiring material.

  At present, such wiring is multi-layered and is often formed by a buried wiring process. In the buried wiring process, first, a layer to be an interlayer insulating film is formed, and a wiring groove and a contact hole are formed in that layer in advance, and then a metal is embedded in the wiring groove and the contact hole to flatten the surface. This is a method of forming a wiring by performing a conversion process.

  Further, as other attempts to reduce signal delay, research on low dielectric constant interlayer insulating films (hereinafter abbreviated as low dielectric constant films) has been actively conducted. For example, when a silicon fluorinated oxide film is employed as an interlayer insulating film instead of a silicon oxide film that is a typical typical interlayer insulating film, the relative dielectric constant of the interlayer insulating film decreases. Then, since the capacitance value of the interlayer insulating film is reduced, signal delay can be reduced. Currently, various materials are being studied as candidates for such low dielectric constant films.

  An example in which the embedded wiring process and the low dielectric constant film are applied to the formation of a multilayer wiring will be described below.

  FIG. 10 shows a semiconductor device D3 including a multilayer wiring structure composed of the first layer metal wiring 105 and the second layer metal wiring 110 and the low dielectric constant films 103 and 107. The semiconductor device D3 includes a substrate 101, and a lower insulating layer 102 is formed on the surface of the substrate 101. Note that elements such as transistors and wirings on the substrate are formed on the surface of the substrate 101 and inside the lower insulating layer 102, but are not shown. A first low dielectric constant film 103 is formed on the surface of the lower insulating layer 102.

  Inside the first low dielectric constant film 103, the first layer metal wiring 105 is exposed to the surface of the first low dielectric constant film 103 while being in contact with the surface of the lower insulating layer 102, and is spaced horizontally. A plurality are formed. On the surface of the first layer metal wiring 105 and the first low dielectric constant film 103, there is an interlayer insulating film (hereinafter referred to as an anti-etching film, the need for an anti-etching film will be described later) 106 having an anti-etching function. Is formed.

  A second low dielectric constant film 107 is formed on the surface of the etching prevention film 106, and a contact hole 111A and a groove 111B extending in the direction perpendicular to the paper surface are formed in the second low dielectric constant film 107 and the etching prevention film 106. Is formed. A metal plug 109 and a second-layer metal wiring 110 are formed in the contact hole 111A and the groove 111B, respectively, and both are continuous. For miniaturization, the width W5 of the first layer metal wiring 105 and the width W9 of the metal plug 109 are designed to be approximately the same, and the width W5 cannot be made sufficiently larger than the width W9. Further, in FIG. 10, the position of the metal plug 109 does not coincide with the position of the first-layer metal wiring 105 in the in-plane direction of the etching prevention film 106, and the contact hole 111A is formed in a misaligned state. This is because the convenience of explaining the problem of the semiconductor device D3 later is intended.

  A method for forming the structure shown in FIG. 10 will be described with reference to FIGS. First, after forming each element (not shown) on the surface of the substrate 101, the lower insulating layer 102 is formed. Next, a first low dielectric constant film 103 is formed on the surface of the lower insulating layer 102 (FIG. 11). Then, a portion of the first low dielectric constant film 103 where the first layer metal wiring 105 is to be formed is etched by photolithography. Thereafter, a metal film as a material of the first layer metal wiring 105 is formed on the surface of the first low dielectric constant film 103, and the etched portion of the first low dielectric constant film 103 is sufficiently filled. Further, the metal surface is flattened and left only on the etched portion of the first low dielectric constant film 103 to form the first layer metal wiring 105 (FIG. 12).

  Next, an insulating film having etching selectivity with respect to the second low dielectric constant film 107 (that is, functioning as a stopper for the etching of the second low dielectric constant film 107) is used as the first anti-etching film 106. A second low dielectric constant film 107 is formed on the dielectric constant film 103 and the surface of the first layer metal wiring 105 (FIG. 13). Then, a contact hole 111A is formed in the second low dielectric constant film 107 by a photolithography technique. At this time, since the etching prevention film 106 has etching selectivity with respect to the second low dielectric constant film 107, the etching rate is automatically performed when the etching proceeds to the etching prevention film 106 when the contact hole 111A is formed. Decreases, and etching can be stopped.

  If there is no etching prevention film 106 here, there is a possibility that the etching does not stop and even the first low dielectric constant film 103 is etched. With the progress of miniaturization of semiconductor devices, it is difficult to form a wide range of lower layer wirings and obtain a sufficient alignment margin for upper layer wirings. Therefore, at present, as described above, the wiring width and the contact hole diameter are often designed to have the same size. Then, if the photomask is misaligned when forming a contact hole by photolithography, the position of the lower layer wiring and the position of the contact hole do not completely overlap, and the interlayer insulation around the lower layer wiring is in the contact hole. The film will be exposed. Then, not only the second low dielectric constant film 107 but also the first low dielectric constant film 103 may be etched.

  When copper or the like is used for the first layer metal wiring 105, the first layer metal wiring 105 may be oxidized when the second low dielectric constant film 107 is deposited or etched. However, such a situation can be prevented if the anti-etching film 106 exists.

  The above is the reason why the etching prevention film 106 is necessary. For example, a silicon nitride film is used as the material of the etching prevention film 106.

  Thereafter, the groove 111B is similarly formed by photolithography (FIG. 14). Also at this time, since the etching prevention film 106 exists, the first low dielectric constant film 103 and the first layer metal wiring 105 are not affected.

  Subsequently, the etching preventive film 106 exposed in the contact hole 111A is etched to expose the first layer metal wiring 105 in the contact hole 111A (FIG. 15). Then, a metal film serving as a material for the metal plug 109 and the second layer metal wiring 110 is formed on the surface of the second low dielectric constant film 107 to sufficiently fill the contact hole 111A and the groove 111B. Then, the metal surface is flattened and left only in the contact hole 111A and the groove 111B, and the metal plug 109 and the second layer metal wiring 110 are formed (FIG. 16).

  The low dielectric constant film has the following problems.

  (1) Since the low dielectric constant film generally has a low film density, when its surface is exposed to an atmosphere containing moisture, it tends to absorb moisture in the atmosphere. Since the water molecules are slightly polarized even in the normal state, if they are incorporated into the film, the relative dielectric constant of the low dielectric constant film is increased.

  (2) In general, a low dielectric constant film has a higher etching rate than a silicon oxide film, and etching control is difficult.

  In the semiconductor device D3 shown in FIG. 10 and the manufacturing method of the semiconductor device D3 shown in FIGS.

  First, regarding the problem (1), according to the manufacturing method of the semiconductor device D3, the time during which the surface of the first low dielectric constant film 103 and the surface of the second low dielectric constant film 107 are exposed to the atmosphere (first low dielectric constant In the case of the dielectric film 103, the time until the anti-etching film 106 is formed, and in the case of the second low dielectric film 107, the time until a film is formed on the surface after the stage of FIG. It is long and easy to absorb moisture. Incidentally, since the silicon oxide film, the silicon oxynitride film, the silicon nitride film, and the like hardly transmit moisture, the first low dielectric constant film 103 can be obtained by adopting any one of them as the etching prevention film 106. It is possible to prevent subsequent moisture absorption.

  Further, when the CMP method is used as a method for planarizing the surface when forming the first layer metal wiring 105 or the second layer metal wiring 110, moisture is supplied to the first low dielectric constant film 103 or the second low dielectric constant film 103. Since the low dielectric constant film 107 is exposed, the problem (1) also becomes a problem in that case.

  Also, the problem (2) is problematic in that the first low dielectric constant film 103 may be over-etched when the etching prevention film 106 is removed during the process of manufacturing the semiconductor device D3. Become. FIG. 17 is a sectional view showing the problem. When the contact hole 111A and the trench 111B are formed, the first low dielectric constant film 103 is not affected by the etching because of the presence of the etching prevention film 106. However, when removing the etching prevention film 106 itself, as shown in FIG. This is because the first low dielectric constant film 103 is easily etched, and the depression 103A is easily formed by overetching. When such a depression 103A is generated, a defective filling of the metal film is likely to occur when the metal plug 109 is formed in the contact hole 111A, resulting in a decrease in the yield of the semiconductor device. For example, when a barrier metal (not shown) is formed inside the contact hole 111A, the formation of the barrier metal becomes incomplete due to poor filling, and the wiring metal generates a spike in the interlayer insulating film, thereby inhibiting the insulation. Because it is easy to do.

  As a technique that can solve these problems, there is a technique disclosed in Japanese Patent Laid-Open No. 6-13470. This technique will be described as a semiconductor device D4 with reference to FIGS. 18 shows the structure of the semiconductor device D4. The semiconductor device D4, like the semiconductor device D3, has a substrate 101, a lower insulating layer 102, a first interlayer insulating film 203, a first layer metal wiring 105, a second layer, and the like. The interlayer insulating film 207, the contact hole 111A, the groove 111B, the metal plug 109, and the second-layer metal wiring 110 are provided (this technique does not employ a low dielectric constant film as the interlayer insulating film). In order to make a distinction, the first low dielectric constant film 103 in the semiconductor device D3 is changed to the first interlayer insulating film 203, and the second low dielectric constant film 107 is changed to the second interlayer insulating film 207, respectively. ) However, unlike the semiconductor device D3, the etching prevention film 106 is not formed in the semiconductor device D4. Instead, a first etching prevention film 104 having a surface in the same plane as the surface of the first layer metal wiring 105 is formed on the second interlayer insulation film 207 on the first interlayer insulation film 203. A second etching prevention film 108 having a surface in the same plane as the surface of the second layer metal wiring 110 is formed respectively.

  19 to 23 show a method for manufacturing the semiconductor device D4. First, as in FIG. 11, each element (not shown) is formed on the surface of the substrate 101, and then the lower insulating layer 102 and the first interlayer insulating film 203 are formed. Then, a first etching prevention film 104 is formed on the surface of the first interlayer insulating film 203 (FIG. 19). Then, portions of the first interlayer insulating film 203 and the first etching prevention film 104 where the first layer metal wiring 105 is to be formed are etched by photolithography. Thereafter, a metal film as a material of the first layer metal wiring 105 is formed on the surface of the first etching prevention film 104, and the etched portion is sufficiently filled. Further, the surface of the metal is planarized, and the first layer metal wiring 105 is formed by leaving the metal only in the etched portion (FIG. 20).

  Next, a second interlayer insulating film 207 is formed, and further a second etching prevention film 108 is formed on the surface (FIG. 21). Then, a contact hole 111A and a groove 111B are formed in the second interlayer insulating film 207 and the second etching prevention film 108 by a photolithography technique (FIG. 22). Then, a metal film as a material for the metal plug 109 and the second layer metal wiring 110 is formed on the surface of the second etching prevention film 108 to sufficiently fill the contact hole 111A and the groove 111B. Then, the metal surface is flattened and left only in the contact hole 111A and the groove 111B, and the metal plug 109 and the second layer metal wiring 110 are formed (FIG. 23).

  When such a semiconductor device D4 is used, the surface of the first etching prevention film 104 exists in the same plane as the surface of the first layer metal wiring. Therefore, when the contact hole 111A is formed as in the semiconductor device D3. In addition, the first interlayer insulating film 203 is not exposed. Therefore, the recess 103A that has been generated when the etching prevention film 106 is removed in the case of the semiconductor device D3 is hardly generated.

  Further, according to the manufacturing method of the semiconductor device D4, the first etching prevention film 104 is formed following the formation of the first interlayer insulating film 203, and the second etching is performed following the formation of the second interlayer insulating film 207. Since the etching prevention film 108 is formed on the surface, the time during which the surface of the first interlayer insulating film 203 and the surface of the second interlayer insulating film 207 are exposed to the atmosphere is short, and it is difficult to absorb moisture. Further, when the CMP method is used as a method of planarizing the surface when forming the first layer metal wiring 105 or the second layer metal wiring 110, the first etching prevention film 104 or the second etching prevention film 108 is formed. Therefore, moisture does not directly touch the first interlayer insulating film 203 or the second interlayer insulating film 207, and the first interlayer insulating film 203 and the second interlayer insulating film 207 are difficult to absorb moisture.

  However, even in the semiconductor device D4, although the recess 103A is less likely to be generated than in the semiconductor device D3, the interface 104A between the first layer metal wiring 105 and the first etching prevention film 104 is exposed when the contact hole 111A is formed. Thus, since it is exposed to the etchant, the generation of the depression 103A cannot be sufficiently suppressed. Usually, the contact holes are widely distributed in the semiconductor device D4, and there are subtle differences in the height of the surface depending on each region. Therefore, when forming the contact hole 111A, the etching time is long to ensure the contact. It is often set to. Then, even if the etching prevention film 104 is formed, since the etching time is long, the etchant actually permeates the interface 104A and the depression 103A is likely to be generated. This is a problem that is difficult to solve even if the etching prevention film 104 is formed thick.

  The present invention has been made to solve the above problems, and prevents a low dielectric constant film from being exposed in a contact hole and overetching in a semiconductor device including a low dielectric constant film and a multilayer wiring. The purpose is to do.

A first aspect of a method for manufacturing a semiconductor device according to the present invention includes a step of forming a first interlayer insulating film on a substrate, and a second interlayer insulating film that is a single layer film on the first interlayer insulating film. Forming a film, forming a third interlayer insulating film on the second interlayer insulating film, and forming a first groove extending through the third interlayer insulating film into the second interlayer insulating film And a step of embedding the first metal in the first groove and a chemical mechanical polishing method to stop the polishing process on the third interlayer insulating film, and the above on the third interlayer insulating film Removing the first metal and leaving the first metal in the first groove to form a first wiring in the first groove; and forming a first wiring on the third interlayer insulating film and on the first wiring. A step of forming one insulating film, a step of forming a fourth interlayer insulating film which is a single layer film on the first insulating film, and the above A step of forming a fifth interlayer insulating film on the fourth interlayer insulating film and a first anisotropic etching so as to penetrate the fourth interlayer insulating film and the fifth interlayer insulating film and expose the first insulating film Forming a first via hole and a second anisotropic etching process to pass through the fifth interlayer insulating film and provide a bottom surface in the fourth interlayer insulating film so as to communicate with the first via hole. Forming a groove; etching the exposed first insulating film by first etching to expose the surface of the first wiring at the bottom of the first via hole; and in the second groove and the second A step of embedding a second metal in one via hole and a chemical mechanical polishing method to stop the polishing process on the fifth interlayer insulating film and remove the second metal on the fifth interlayer insulating film; In and above the second groove Leaving the second metal in the first via hole, the second wiring formed in the second groove, and a step of forming a first via within the first via hole. In the first anisotropic etching, the etching rate of the first insulating film is smaller than the etching rate of the fourth interlayer insulating film, and in the first etching, the third interlayer insulating film is in the first via hole. The etching rate of the third interlayer insulating film is lower than the etching rate of the first insulating film. Each of the second interlayer insulating film and the fourth interlayer insulating film is a low dielectric constant film having a dielectric constant lower than that of the silicon oxide film . The first wiring and the second wiring are connected by the first via.

A second aspect of the method for manufacturing a semiconductor device according to the present invention includes a step of forming a first interlayer insulating film on a substrate, and a second interlayer insulating that is a single layer film on the first interlayer insulating film. Forming a film, forming a third interlayer insulating film on the second interlayer insulating film, and forming a first groove extending through the third interlayer insulating film into the second interlayer insulating film And a step of embedding the first metal in the first groove and a chemical mechanical polishing method to stop the polishing process on the third interlayer insulating film, and the above on the third interlayer insulating film Removing the first metal and leaving the first metal in the first groove to form a first wiring in the first groove; and forming a first wiring on the third interlayer insulating film and on the first wiring. A step of forming one insulating film, a step of forming a fourth interlayer insulating film which is a single layer film on the first insulating film, and the above Forming a fifth interlayer insulating film on the fourth interlayer insulating film, and a second groove that penetrates the fifth interlayer insulating film and has a bottom surface on the fourth interlayer insulating film by first anisotropic etching; And a second anisotropic etching to pass through the fourth interlayer insulating film and the fifth interlayer insulating film, expose the first insulating film, and communicate with the second groove. A step of forming a via hole; a step of etching the exposed first insulating film by first etching to expose a surface of the first wiring at a bottom of the first via hole; A step of embedding a second metal in one via hole and a chemical mechanical polishing method to stop the polishing process on the fifth interlayer insulating film and remove the second metal on the fifth interlayer insulating film; , In the second groove and the first Leaving the second metal in the hole, the second wiring formed in the second groove, and a step of forming a first via within the first via hole. In the first anisotropic etching, the etching rate of the first insulating film is smaller than the etching rate of the fourth interlayer insulating film, and in the first etching, the third interlayer insulating film is in the first via hole. The etching rate of the third interlayer insulating film is lower than the etching rate of the first insulating film. Each of the second interlayer insulating film and the fourth interlayer insulating film is a low dielectric constant film having a dielectric constant lower than that of the silicon oxide film . The first wiring and the second wiring are connected by the first via.

  Preferably, the materials of the second interlayer insulating film and the fourth interlayer insulating film are the same, and the materials of the third interlayer insulating film and the fifth interlayer insulating film are the same.

More preferably, the second interlayer insulating film is hydrogenated silsesquioxane, methylsilsesquioxane, polyallyl ether, benzocyclobutene, polytetrafluoroethylene, xerogel as porous silica, aerogel as porous silica, or fluorination. wherein the silicon oxide film, and a fluorinated amorphous carbon emissions or we selected one material, the third interlayer insulating film is a silicon oxide film.

  More preferably, the relative dielectric constant of the second interlayer insulating film is in the range of 1.8 to 3.0, and the first insulating film is an insulating film composed of a compound of silicon and nitrogen.

Or desirably, between the step of forming the first groove and the step of embedding the first metal, a step of performing a first heat treatment to remove moisture from the surface of the first groove, and exposing the surface of the first wiring A step of performing a second heat treatment to blow moisture from the surface of the second groove and the surface of the first via hole between the step of forming and the step of embedding the second metal.

  Alternatively, preferably, the materials of the second interlayer insulating film and the fourth interlayer insulating film are the same, the materials of the third interlayer insulating film and the fifth interlayer insulating film are the same, and the third interlayer insulating film and The first insulating film has a higher moisture permeation preventing function than the second interlayer insulating film.

  According to the method for manufacturing a semiconductor device according to the present invention, after forming the first via hole and the second groove, the first insulating film exposed at the bottom of the first via hole is subjected to the first etching to form the first wiring surface. Since it is exposed, the first insulating film can be thinned to shorten the first etching time. Therefore, it is possible to avoid the problem that the second interlayer film is largely overetched by overetching due to the first etching when the misalignment of the first via hole in which the second metal is embedded in the second groove and the first via hole occurs. .

Embodiment 1 FIG.
FIG. 1 is a cross-sectional view showing the structure of the semiconductor device D1 according to the present embodiment. The semiconductor device D1 includes a multilayer wiring structure including a first layer metal wiring 5 and a second layer metal wiring 10 connected via a metal plug 9. For example, copper is used as the metal constituting the multilayer wiring structure. The semiconductor device D1 further includes a substrate 1, and a lower insulating layer 2 is formed on the surface of the substrate 1. Although elements such as transistors and wirings on the substrate are formed on the surface of the substrate 1 and inside the lower insulating layer 2, illustration thereof is omitted.

  A first low dielectric constant film 3 is formed on the surface of the lower insulating layer 2. Examples of the material for the low dielectric constant film include hydrogen silsesquioxane, methyl silsesquioxane, polyarylether, benzocyclobutene, polytetrafluoroethylene ( Polytetrafluoroethylene), porous silica such as Xerogel, Aerogel, and other materials formed by spin coating, and CVD (Chemical Vapor) such as fluorinated silicon oxide film, fluorinated amorphous carbon, and Parylene A material formed by the Deposition method is applicable. The relative dielectric constant of such a low dielectric constant film is about 1.8 to 3.0. In the present embodiment, for example, polyallyl ether (hereinafter referred to as PAE) is used for the first low dielectric constant film 3. PAE is an organic substance mainly composed of carbon, oxygen, and hydrogen.

  Further, in the present embodiment, the first etching prevention film 4 is formed on the surface of the first low dielectric constant film 3. The first etching prevention film 4 is a film that prevents the permeation of moisture, and has a function of preventing the first low dielectric constant film 3 from absorbing moisture from the outside. For example, a silicon oxide film is used as the material of the first etching prevention film 4. Further, the first layer metal wiring 5 is in contact with the surface of the lower insulating layer 2 inside the first low dielectric constant film 3 and the first etching prevention film 4, and the surface of the first etching prevention film 4. A plurality are formed at intervals in the horizontal direction.

  A second etching prevention film 6 is formed on the surfaces of the first layer metal wiring 5 and the first etching prevention film 4. That is, in the present invention, the etching prevention film is provided twice. The second etching prevention film 6 is made of a material that has etching selectivity with respect to the material of the first etching prevention film 4 and prevents the permeation of moisture. When a silicon oxide film is used for the first etching prevention film 4, for example, a silicon nitride film is used for the second etching prevention film 6.

  A second low dielectric constant film 7 is formed on the surface of the second etching prevention film 6, and a third etching prevention film 8 is formed on the surface of the second low dielectric constant film 7. As the material of the second low dielectric constant film 7, for example, PAE is adopted as in the case of the first low dielectric constant film 3. The third etching prevention film 8 has a function of preventing the permeation of moisture. For example, a silicon oxide film is used for the third etching prevention film 8, as in the case of the first etching prevention film 4.

  A metal plug 9 is formed in the contact hole 11A formed in the second low dielectric constant film 7 and the second etching prevention film 6. A second-layer metal wiring 10 is formed in a groove 11B formed in the second low dielectric constant film 7 and the third etching prevention film 8 and extending in the direction perpendicular to the paper surface.

  In the semiconductor device according to the present embodiment, the first etching prevention film 4 and the second etching prevention film 6 are formed to form a double etching prevention film. Therefore, when the contact hole 11A is formed, even if the etching time is long, the etching of the second low dielectric constant film 7 can be temporarily stopped because the second etching prevention film 6 is formed. . At this time, the interface 4A between the first-layer metal wiring 5 and the first etching prevention film 4 and the first low dielectric constant film 3 are covered with the second etching prevention film 6, so that the contact hole 11A is in the contact hole 11A. The possibility of exposure is low. Further, when the second etching prevention film 6 in the contact hole 11A is removed for contact, there is an etching selectivity between the first etching prevention film 4 and the second etching prevention film 6. Further, unlike the case where the second low dielectric constant film 7 is etched, it is not necessary to lengthen the etching time of the second etching prevention film 6, so even if the interface 4 A is exposed, the semiconductor device D 3 is used. As described above, it is unlikely that the first low dielectric constant film 3 is over-etched to generate a depression. Therefore, the metal plug 9 is less likely to be embedded in the contact hole 11A, and the reliability of the semiconductor device is high.

  Further, the first low dielectric constant film 3 has a first etching prevention film 4 and a second etching prevention film 6 formed on its surface in a double manner, and each of them functions to prevent moisture permeation. Because it is equipped with, there is little possibility of moisture absorption. The second low dielectric constant film 7 is also less likely to absorb moisture because the third etching prevention film 8 that prevents the permeation of moisture is formed on the surface thereof. Therefore, the relative dielectric constant of the first low dielectric constant film 3 and the second low dielectric constant film 7 is not increased.

  Although not shown in the drawing, a fourth etching prevention film similar to the second etching prevention film 6 and a second low dielectric constant are further formed on the surfaces of the second layer metal wiring 10 and the third etching prevention film 8. A third low dielectric constant film similar to the film 7, a fifth etching preventive film similar to the third etching preventive film 8, a metal plug similar to the metal plug 9, and a third similar to the second layer metal wiring 10 Each layer metal wiring may be formed.

  In this case, the etching selectivity relationship between the third etching prevention film 8 and the fourth etching prevention film is the etching selectivity between the first etching prevention film 4 and the second etching prevention film 6. Therefore, the possibility of generating a depression in the second low dielectric constant film 7 is low. Also, the third etching prevention film 8 and the fourth etching prevention film are formed in a double manner on the surface of the second low dielectric constant film 7, and each of them has a function of preventing moisture permeation. Therefore, the second low dielectric constant film 7 is less likely to absorb moisture. In addition, the third low dielectric constant film is also less likely to absorb moisture because the surface thereof is provided with the fifth anti-etching film that prevents the permeation of moisture.

  Of course, such a layer structure may be repeatedly formed. In this case, the same effect is obtained for each layer. In general terms, the surface of the Nth (N ≧ 1) layer metal wiring and the surface of the (2N−1) th anti-etching film are further provided with the (2N) th anti-etching film and the (N + 1) th low-thickness. A dielectric film and a (2N + 1) th anti-etching film may be formed in this order, and a metal plug and a (N + 1) th layer metal wiring may be formed inside them.

  FIG. 2 is a cross-sectional view showing the structure of the semiconductor device D2 according to the modification of the present embodiment. In this way, if the first etching prevention film 4 and the third etching prevention film 8 are formed as the thicker first etching prevention film 14 and third etching prevention film 18, respectively, the etching prevention effect is enhanced. The possibility of generating a depression due to over-etching in the low dielectric constant film immediately below each film is further reduced. Further, the possibility that the first low dielectric constant film 3 and the second low dielectric constant film 7 absorb moisture is also reduced.

  As an example of forming the anti-etching film double, there is a technique described in, for example, Japanese Patent Application Laid-Open No. 8-264644. FIG. 3 shows a case where this technique is applied to the semiconductor device D3 (however, since this technique does not employ a low dielectric constant film, the first and (Instead of the second low dielectric constant films 103 and 107, they are shown as first and second interlayer insulating films 203 and 207). However, according to this technique, the present invention is different from the present invention in that an etching prevention film 204 made of the same material as that of the etching prevention film 106 is provided on the surface of the first layer metal wiring 105 instead of on the surface of the first interlayer insulating film 203. The configuration is different. Such a difference is that when this technique removes the etching prevention film 106 in the contact hole 111A, the etching prevention film 204 is removed at the same time, and the contact between the first layer wiring 105 and the metal plug 109 is made in a self-aligning manner. This is due to the purpose of taking. That is, the purpose is not to protect the first interlayer insulating film 203, and the purpose is different from that of the present application.

Embodiment 2. FIG.
In the present embodiment, a method for manufacturing the semiconductor device D1 according to the first embodiment will be described. A method for manufacturing the semiconductor device D1 will be described with reference to FIGS. First, after each element (not shown) is formed on the surface of the substrate 1, the lower insulating layer 2 is formed thereon. Next, a PAE film is formed as a first low dielectric constant film 3 on the surface of the lower insulating layer 2 by, for example, spin coating, and then a silicon oxide film is formed as the first etching prevention film 4 by, for example, plasma CVD. It is formed on the surface of the first low dielectric constant film 3 (FIG. 4).

Then, a photolithography technique is applied to a portion of the etching prevention film 4 and the first low dielectric constant film 3 where the first layer metal wiring 5 is to be formed. That is, a resist is formed on the surface of the first etching prevention film 4 and patterned, and the first etching prevention film 4 is etched. Since the material of the first etching prevention film 4 is a silicon oxide film, for example, plasma etching using a mixed gas of C ₄ F ₈ and Ar may be performed. After the first low dielectric constant film 3 is exposed, the etching gas is changed, and the first low dielectric constant film 3 is etched using the first etching prevention film 4 as a mask until the lower insulating layer 2 is exposed. Since the material of the first low dielectric constant film 3 is PAE, for example, any one of a mixed gas of oxygen and nitrogen, a mixed gas of oxygen, nitrogen and Ar, or a mixed gas of nitrogen and hydrogen may be used as an etching gas. . Since any of these mixed gases can etch organic matter, the resist initially formed on the first anti-etching film 4 can be removed at the same time. Since the silicon oxide film, the silicon nitride film, etc. are hardly etched by these mixed gases, the first etching prevention film 4 is hardly affected by the etching.

  Thereafter, the first layer metal wiring 5 is formed. Before that, the first low dielectric constant film 3 may absorb moisture from the etched side wall. Let it go.

  Then, a metal film as a material for the first layer metal wiring 5 is formed on the surface of the first etching prevention film 4, and the etched portion of the first etching prevention film 4 and the first low dielectric constant film 3. Fill up enough. In the present embodiment, for example, copper is embedded by a plating method. Thereafter, an unnecessary metal film on the first etching prevention film 4 is removed by using, for example, a chemical mechanical polishing (CMP) method, and the metal surface is flattened to planarize the first layer metal wiring. 5 is formed (FIG. 5). In addition to the plating method, the process for embedding the metal film includes a reflow method in which the metal film is softened by a heat treatment after being deposited by a sputtering method, a CVD method, or the like. In addition to copper, an Al alloy or the like may be employed as the material for the metal film.

  Next, a silicon nitride film is formed as a second etching prevention film 6 on the surfaces of the first etching prevention film 4 and the first layer metal wiring 5 by, for example, a plasma CVD method. Further, a PAE film is formed as the second low dielectric constant film 7 on the surface of the etching preventing film 6 by, for example, a spin coating method. Further, a third etching prevention film 8 having etching selectivity with respect to the second etching prevention film 6 is formed on the surface of the second low dielectric constant film 7, and a silicon oxide film is formed by, for example, a plasma CVD method. An anti-etching film 8 is formed (FIG. 6).

  Then, contact holes 11A and grooves 11B are formed in the second low dielectric constant film 7 and the third etching prevention film 8 by photolithography. At this time, there are a method of forming the groove 11B after forming the contact hole 11A first, and a method of forming the contact hole 11A after forming the groove 11B first, either of which may be used. Below, the case where the former method is employ | adopted is described, for example.

First, a resist is formed on the surface of the third etching prevention film 8, the contact hole 11A is patterned, and the third etching prevention film 8 is etched. Since the material of the third etching prevention film 8 is a silicon oxide film, plasma etching using, for example, a mixed gas of C ₄ F ₈ and Ar may be performed in the same manner as the first etching prevention film 4. After the second low dielectric constant film 7 is exposed, the etching gas is changed and the second low dielectric constant film 7 is etched until the second etching prevention film 6 is exposed. Since the material of the second low dielectric constant film 7 is PAE, as with the first low dielectric constant film 3, for example, a mixed gas of oxygen and nitrogen, or a mixed gas of oxygen, nitrogen and Ar, or a mixed gas of nitrogen and hydrogen Any gas may be used as the etching gas. Since any of these mixed gases can etch organic matter, the resist initially formed on the third anti-etching film 8 can be removed at the same time. On the other hand, since these mixed gases can hardly etch the silicon nitride film which is the second etching prevention film 6, the formation of the contact hole 11A is stopped when the second etching prevention film 6 is exposed.

Next, the trench 11B is also etched in the same manner as the contact hole 11A, and is formed so as to communicate with the contact hole 11A and to have a bottom in the first low dielectric constant film 3. That is, a resist is formed on the surface of the third etching prevention film 8 and patterned so as to cross the contact hole 11A in which the groove 11B has been formed, and the third etching prevention film 8 is plasma etched. However, at this time, since the silicon nitride film that is the second etching prevention film 6 is already exposed, the second etching prevention film 6 is etched when the silicon oxide film that is the third etching prevention film 8 is etched. You must not do it. Therefore, the etching conditions are adjusted so that the ratio between the etching rate of the silicon oxide film and the etching rate of the silicon nitride film is, for example, 10: 1. For example, the previously used mixed gas of C ₄ F ₈ and Ar can be adjusted so as to satisfy the above-described conditions for the silicon nitride film, and plasma etching using this gas may be performed similarly.

  After the second low dielectric constant film 7 is exposed, the etching gas is changed to either a mixed gas of oxygen and nitrogen, a mixed gas of oxygen, nitrogen and Ar, or a mixed gas of nitrogen and hydrogen. Then, the second low dielectric constant film 7 is etched until a desired width and depth are obtained, thereby forming a groove 11B (FIG. 7).

  Subsequently, etching is performed under the condition that only the second etching prevention film 6 in the contact hole 11 </ b> A is etched without etching the third etching prevention film 8. Therefore, the etching conditions are adjusted so that the ratio between the etching rate of the silicon oxide film and the etching rate of the silicon nitride film is, for example, 1:10. For example, if a mixed gas of chlorine and oxygen is used, it can be adjusted so as to satisfy the above conditions, and plasma etching using this gas may be performed. In this way, the first layer metal wiring 5 is exposed in the contact hole 11A (FIG. 8). If a mixed gas of chlorine and oxygen is used, the second low dielectric constant film 7 is somewhat etched, so that the width of the groove 11B is widened and the height of the bottom surface is reduced. Therefore, the width and depth of the groove 11B may be determined in advance in consideration of the etching time of the second etching prevention film 6 and the etching speed of the second low dielectric constant film 7 at that time. .

  The above description is about the case where the groove 11B is formed after the contact hole 11A is formed first. However, when the contact hole 11A is formed after the groove 11B is formed first, the following points are described. This makes the process a little easier. That is, first, since the second etching prevention film 6 is not exposed at the time of forming the groove 11B, the etching selection is performed so that the second etching prevention film 6 is not etched while the third etching prevention film 8 is etched. Second, in order to form the contact hole 11A, it is only necessary to pattern and etch the second low dielectric constant film 7 in the groove 11B. This is because there is no need to etch 8.

  However, in this case, since it is necessary to perform photolithography while aligning the mask pattern of the contact hole 11A with the formed groove 11B, the mask alignment must be carefully adjusted. In that respect, a slight misalignment is allowed when the contact hole 11A is formed first.

  After this, the metal plug 9 and the second layer metal wiring 10 are formed. Before that, the second low dielectric constant film 7 may absorb moisture from the side walls of the contact hole 11A and the groove 11B. Therefore, heat treatment is performed to release moisture.

  Then, a metal film as a material of the metal plug 9 and the second layer metal wiring 10 is formed on the surface of the third etching prevention film 8 to sufficiently fill the contact hole 11A and the groove 11B, and the metal surface is filled with, for example, The metal is planarized by the CMP method, leaving the metal only in the contact hole 11A and the groove 11B, and the metal plug 9 and the second layer metal wiring 10 are formed (FIG. 9).

  Note that in the case of manufacturing a semiconductor device having a repeated layer structure, the above steps may be repeated.

  If the manufacturing method of the semiconductor device according to the present embodiment is used, the etching of the second low dielectric constant film 7 can be temporarily stopped because the second etching prevention film 6 is formed. At this time, even when the contact hole 11A is formed in a state where the alignment of the photomask is shifted, the interface 4A between the first layer metal wiring 5 and the first etching prevention film 4 and the first low dielectric constant. Since the film 3 is covered with the second etching preventive film 6, the possibility of being exposed in the contact hole 11A is low. Further, when the second etching prevention film 6 in the contact hole 11A is removed for contact, there is an etching selectivity between the first etching prevention film 4 and the second etching prevention film 6. Unlike the case where the second low dielectric constant film 7 is etched, it is not necessary to lengthen the etching time of the second etching prevention film 6, so that the first low dielectric constant as in the semiconductor device D3 is not required. The possibility of over-etching the rate film 3 to generate dents is low.

  Further, the first etching prevention film 4 is formed following the formation of the first low dielectric constant film 3, and the second etching prevention film 8 is formed on the surface following the formation of the second low dielectric constant film 7. Since it is formed, the time during which the surface of the first low dielectric constant film 3 and the surface of the second low dielectric constant film 7 are exposed to the atmosphere is short, and it is difficult to absorb moisture. Further, when the first layer metal wiring 5 or the second layer metal wiring 10 is formed, even if the CMP method is used as a method for planarizing the surface, the first etching prevention film 4 or the third etching is performed. Since the prevention film 8 is present, moisture does not directly contact the first low dielectric constant film 3 or the second low dielectric constant film 7, and the first low dielectric constant film 3 and the second low dielectric constant film 7 7 is difficult to absorb moisture.

  Further, when the contact hole 11A is formed first, the third etching prevention film 8 has etching selectivity with respect to the second etching prevention film 6, so that the third etching can be performed by adjusting the etching conditions. When the surface of the prevention film 8 is patterned for forming the groove 11B, the second etching prevention film 6 can be prevented from being etched while the third etching prevention film 8 is etched. On the other hand, when the second etching prevention film 6 is etched to expose the first layer metal wiring 5, the second etching prevention film 6 is etched while the third etching prevention film 8 is not etched. be able to.

  Even when copper or the like is used for the first layer metal wiring 5, the second etching prevention film 6 exists, so that the oxidation of the first layer metal wiring 5 can be prevented.

1 is a cross-sectional view illustrating a structure of a semiconductor device according to a first embodiment. FIG. 10 is a cross-sectional view showing a modification of the semiconductor device of First Embodiment. It is sectional drawing which shows the structure of the conventional semiconductor device. 11 is a cross-sectional view showing each step of the manufacturing method of the semiconductor device of Embodiment 2. FIG. 11 is a cross-sectional view showing each step of the manufacturing method of the semiconductor device of Embodiment 2. FIG. 11 is a cross-sectional view showing each step of the manufacturing method of the semiconductor device of Embodiment 2. FIG. 11 is a cross-sectional view showing each step of the manufacturing method of the semiconductor device of Embodiment 2. FIG. 11 is a cross-sectional view showing each step of the manufacturing method of the semiconductor device of Embodiment 2. FIG. 11 is a cross-sectional view showing each step of the manufacturing method of the semiconductor device of Embodiment 2. FIG. It is sectional drawing which shows the structure of the conventional semiconductor device. It is sectional drawing which shows each process of the manufacturing method of the conventional semiconductor device. It is sectional drawing which shows each process of the manufacturing method of the conventional semiconductor device. It is sectional drawing which shows each process of the manufacturing method of the conventional semiconductor device. It is sectional drawing which shows each process of the manufacturing method of the conventional semiconductor device. It is sectional drawing which shows each process of the manufacturing method of the conventional semiconductor device. It is sectional drawing which shows each process of the manufacturing method of the conventional semiconductor device. It is sectional drawing which shows the problem of the conventional semiconductor device. It is sectional drawing which shows the structure of the conventional semiconductor device. It is sectional drawing which shows each process of the manufacturing method of the conventional semiconductor device. It is sectional drawing which shows each process of the manufacturing method of the conventional semiconductor device. It is sectional drawing which shows each process of the manufacturing method of the conventional semiconductor device. It is sectional drawing which shows each process of the manufacturing method of the conventional semiconductor device. It is sectional drawing which shows each process of the manufacturing method of the conventional semiconductor device.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Substrate, 2 Lower insulating layer, 3 First low dielectric constant film, 4 First etching prevention film, 5 First layer metal wiring, 6 Second etching prevention film, 7 Second low dielectric constant film, 8 3rd etching prevention film, 9 metal plug, 10 2nd layer metal wiring, 11A contact hole, 11B groove | channel.

Claims (7)

Forming a first interlayer insulating film on the substrate;
Forming a second interlayer insulating film which is a single layer film on the first interlayer insulating film;
Forming a third interlayer insulating film on the second interlayer insulating film;
Forming a first groove extending into the second interlayer insulating film and penetrating through the third interlayer insulating film;
Embedding a first metal in the first groove;
By performing a chemical mechanical polishing method, the polishing process is stopped with the third interlayer insulating film, the first metal on the third interlayer insulating film is removed, and the first metal is placed in the first groove. Leaving a step of forming a first wiring in the first groove;
Forming a first insulating film on the third interlayer insulating film and the first wiring;
Forming a fourth interlayer insulating film which is a single layer film on the first insulating film;
Forming a fifth interlayer insulating film on the fourth interlayer insulating film;
Forming a first via hole through the fourth interlayer insulating film and the fifth interlayer insulating film and exposing the first insulating film by first anisotropic etching;
Forming a second groove penetrating the fifth interlayer insulating film by the second anisotropic etching, providing a bottom surface in the fourth interlayer insulating film, and communicating with the first via hole;
Etching the exposed first insulating film by first etching to expose the surface of the first wiring at the bottom of the first via hole;
Burying a second metal in the second groove and the first via hole;
By performing a chemical mechanical polishing method, the polishing process is stopped on the fifth interlayer insulating film, the second metal on the fifth interlayer insulating film is removed, and the second groove and the first via hole are removed. And forming the second wiring in the second groove, and forming the first via in the first via hole.
In the first anisotropic etching, the etching rate of the first insulating film is smaller than the etching rate of the fourth interlayer insulating film,
In the first etching, the third interlayer insulating film is exposed at the bottom of the first via hole, and the etching rate of the third interlayer insulating film is smaller than the etching rate of the first insulating film,
Each of the second interlayer insulating film and the fourth interlayer insulating film is a low dielectric constant film having a lower dielectric constant than a silicon oxide film ,
A method of manufacturing a semiconductor device, wherein the first wiring and the second wiring are connected by the first via. Forming a first interlayer insulating film on the substrate;
Forming a second interlayer insulating film which is a single layer film on the first interlayer insulating film;
Forming a third interlayer insulating film on the second interlayer insulating film;
Forming a first groove extending into the second interlayer insulating film and penetrating through the third interlayer insulating film;
Embedding a first metal in the first groove;
By performing a chemical mechanical polishing method, the polishing process is stopped with the third interlayer insulating film, the first metal on the third interlayer insulating film is removed, and the first metal is placed in the first groove. Leaving a step of forming a first wiring in the first groove;
Forming a first insulating film on the third interlayer insulating film and the first wiring;
Forming a fourth interlayer insulating film which is a single layer film on the first insulating film;
Forming a fifth interlayer insulating film on the fourth interlayer insulating film;
Forming a second groove through the fifth interlayer insulating film by the first anisotropic etching so that a bottom surface is provided in the fourth interlayer insulating film;
Forming a first via hole through the fourth interlayer insulating film and the fifth interlayer insulating film by second anisotropic etching, exposing the first insulating film, and communicating with the second groove; ,
Etching the exposed first insulating film by first etching to expose the surface of the first wiring at the bottom of the first via hole;
Burying a second metal in the second groove and the first via hole;
By performing a chemical mechanical polishing method, the polishing process is stopped on the fifth interlayer insulating film, the second metal on the fifth interlayer insulating film is removed, and the second groove and the first via hole are removed. And forming the second wiring in the second groove, and forming the first via in the first via hole.
In the second anisotropic etching, the etching rate of the first insulating film is smaller than the etching rate of the fourth interlayer insulating film,
In the first etching, the third interlayer insulating film is exposed at the bottom of the first via hole, and the etching rate of the third interlayer insulating film is smaller than the etching rate of the first insulating film,
Each of the second interlayer insulating film and the fourth interlayer insulating film is a low dielectric constant film having a lower dielectric constant than a silicon oxide film ,
A method of manufacturing a semiconductor device, wherein the first wiring and the second wiring are connected by the first via. The materials of the second interlayer insulating film and the fourth interlayer insulating film are the same,
3. The method of manufacturing a semiconductor device according to claim 1, wherein the third interlayer insulating film and the fifth interlayer insulating film are made of the same material. The second interlayer insulating film includes hydrogenated silsesquioxane, methylsilsesquioxane, polyallyl ether, benzocyclobutene, polytetrafluoroethylene, xerogel as porous silica, aerogel as porous silica, and fluorinated silicon oxide film. , and comprises a fluorinated amorphous carbon emissions or we selected one material,
4. The method of manufacturing a semiconductor device according to claim 3, wherein the third interlayer insulating film is a silicon oxide film. The relative dielectric constant of the second interlayer insulating film is in the range of 1.8 to 3.0,
5. The method of manufacturing a semiconductor device according to claim 4, wherein the first insulating film is an insulating film made of a compound of silicon and nitrogen. Between the step of forming the first groove and the step of embedding the first metal, performing a first heat treatment to blow moisture from the surface of the first groove;
A step of performing a second heat treatment to remove moisture from the surface of the second groove and the surface of the first via hole between the step of exposing the surface of the first wiring and the step of embedding the second metal. The method for manufacturing a semiconductor device according to claim 1, wherein the method is a semiconductor device manufacturing method.   4. The method of manufacturing a semiconductor device according to claim 3, wherein the third interlayer insulating film and the first insulating film have a moisture permeation preventing function higher than that of the second interlayer insulating film.

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