JPH0423465A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To improve a yield of manufacture and the reliability of a wiring by a method wherein a double-layer film is used for an interlayer insulation film, an upper-layer film is etched off on the occasion of patterning a capacitor electrode or a bit line and etching is stopped at a lower-layer film. CONSTITUTION:A double-layer film is used for a first or second interlayer insulation film, an upper-layer film 8N is etched off on the occasion of patterning a capacitor electrode 2 or a bit line 3 and etching is stopped at a lower-layer film 8. In this way, the interlayer insulation film in the part wherein a contact hole 5 is formed is thinned by etching off to the SiN film 8N in self-alignment with a wiring by the same etchant at the time when the wiring is patterned, and thereby the contact hole can be formed to be shallow. According to this method, a yield of manufacture and the reliability of the wiring can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] This invention relates to a back wiring method for word lines of a MOS DRAM (dynamic random access memory).

The purpose is to improve the step coverage of the backing wiring in the contact hole with the word line and improve manufacturing yield and wiring reliability.

l) Field oxide film (102) in the isolation region on the semiconductor substrate (101), gate oxide film (103) in the element region
forming a word line (1) on the substrate, forming capacitors (2) and (7) via a first interlayer insulating film; A step of forming a bit line (3) by depositing a third interlayer insulating film over the entire surface of the substrate, and forming a contact hole (5) penetrating the interlayer insulating film on the isolation region to form a word line. (1), and forming a backing wiring (4) on the substrate to cover the contact hole (5), at least one of the first or second interlayer insulating films
In this method, a two-layer film consisting of a lower layer film and an upper layer film is used, and when patterning the capacitor electrode (2) or bit line (3), the upper layer film is etched off in self-alignment with the wiring pattern to prevent etching. It is configured to stop at the lower layer film.

2) The two-layer film is configured such that the lower layer is a silicon dioxide film and the upper layer is a silicon nitride film.

[Industrial application field]

The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device.
The present invention relates to a method of forming backing wiring for a word line of a RAM.

With the recent increase in the degree of integration of MOS DRAMs, there has been a demand for finer patterns, and with the demand for higher speeds, it has become necessary to back the word lines with metal wiring in order to suppress word line signal delays.

At this time, since the diameter of the contact hole between the backing wiring and the word line is minute, it is necessary to form the contact hole shallowly in order to improve the step coverage of the backing wiring.

The present invention can be used as a wiring method that meets this requirement.

[Conventional technology]

In conventional MOS DRAMs, the capacitor structure is of a planar type, so the aspect ratio of the contact hole is small; however, in the case of a stacked capacitor, which is often used in highly integrated DRAMs.

The contact hole between the backing wiring and the word line in the memory cell becomes deep, and the step coverage of the backing wiring becomes poor.

FIG. 4 is a sectional view illustrating a backing wiring using A1 alloy according to a conventional example.

In the figure, ■ is a word line (gate 1-), 2 is a storage electrode of a capacitor, 3 is a bit line, 4 is a backing wiring,
5 is a contact hole for backing wiring and word line, 6,
8 to 10 are interlayer insulating films, 7 is a counter electrode of the capacitor,
101 is a semiconductor substrate, which is a silicon substrate, 102 is a field oxide film, and 103 is a gate insulating film.

Note that in FIG. 9, the dielectric film of the capacitor between the storage electrode 2 and the counter electrode 7 is omitted.

When the backing wiring 4 is made of A1 alloy, it has a low melting point, so the backing wiring 4 is formed on it after the capacitor electrode 3 is formed, so that the contact hole 5 with the word line 1 becomes deep especially when a stacked capacitor is included. , the step coverage at the contact hole portion of the backing wiring 4 becomes very poor (resulting in a decrease in the reliability of the wiring).

[Problem to be solved by the invention]

Therefore, in order to improve the 9-step coverage, methods such as etching the shape of the contact hole into a tapered shape or applying an isotropic component of etching to the upper part of the contact hole (isotropic etching + anisotropic etching) are recommended. However, both of these methods go against the pattern miniaturization specifications and are difficult to implement.

Another possible method is to use a mask to form a shallow contact hole, but this increases the number of steps and costs.

Therefore, by self-aligning with wiring such as bit lines and etching off the interlayer insulating film, the contact hole is made shallow (
There are several ways to form the wiring layer, but if the 5-layer interlayer insulating film is only made of conventional silicon dioxide (SiO□), the wiring layer etch (
The etchant used in patterning the wiring layer cannot etch the interlayer insulating film. Therefore, even if the etchant is changed, there are problems such as etching the underlying wiring layer, making it difficult.

Therefore, etching can be performed simultaneously when etching the wiring layer.
Moreover, an interlayer insulating film is required to stop etching without etching the underlying wiring layer.

The present invention selectively employs such an interlayer insulating film.

The purpose of this invention is to improve the step coverage of word line backing wiring in MOS DRAM, and to improve manufacturing yield and wiring reliability.

[Means to solve the problem]

The solution to the above problem is 1) a field oxide film (102) in the isolation region on the semiconductor substrate (lot) and a gate oxide film (103) in the element region.
A word line (1) is formed on the substrate, and a capacitor (2) is formed through a first interlayer insulating film.

(7) and then forming a bit line (3) via a second interlayer insulating film;
forming a contact hole (5) penetrating the interlayer insulating film on the isolation region to expose the word line (1); and depositing the contact hole (5) on the substrate. forming a backing wiring (4) covering the capacitor electrode (2), using a two-layer film consisting of a lower layer film and an upper layer film as at least one of the first or second interlayer insulating film; or 2) a method for manufacturing a semiconductor device, characterized in that when patterning the bit line (3), the upper layer film is etched off in self-alignment with the wiring pattern, and etching is stopped at the lower layer film; or 2) The two-layer film is achieved by the method for manufacturing a semiconductor device described in 1) above, in which the lower layer is a silicon dioxide film and the upper layer is a silicon nitride film.

[Effect]

In the present invention, the interlayer insulating film below the wiring to be patterned is made of silicon nitride (SiN)/silicon dioxide (S
As a two-layer structure of iO□), contact holes can be formed shallowly by self-aligning with the wiring using the same etchant during wiring patterning and etching off down to the SiN film to thin the interlayer insulating film in the contact hole formation area. This is how it was done.

In this case, since SiN/SiO2 has a sufficient etching selection ratio, etching can be stopped at SiO□, so that the underlying wiring is not etched.

〔Example〕

FIGS. 1(a) to 1(C) are a sectional view and a plan view illustrating an embodiment of the present invention.

In the figure, 1 is a word line (gate).

2 is the storage electrode of the capacitor, and 3 is the bit line.

4 is a backing wiring, 5 is a contact hole between the backing wiring and a word line, 6, 8 to 10 are interlayer insulating films, 7 is a counter electrode of a capacitor, and 8N is an interlayer insulating film, which is a SiN film.

101 is a semiconductor substrate, a silicon substrate, 102 is a field oxide film, and 103 is a gate insulating film.

Note that in FIG. 7, the dielectric film of the capacitor between the storage electrode 2 and the counter electrode 7 is omitted.

In this example, S is connected between the bit line 3 and the capacitor electrode 2.
This is an example in which a two-layer film consisting of an iN film 8N and a SiO□ film 8 is used, and the contact hole is slightly shallower than in the conventional example, and one-step difference coverage is improved.

In FIG. 1(a), a field oxide film 102 with a thickness of 4,000 to 6,000 wafers is formed by thermal oxidation in the isolation region on the substrate.
A gate oxide film 103 with a thickness of 150 to 300 mm is formed by thermal oxidation on the element region, for example, with a thickness of 1500 to 300 mm.
A word line 1 made of a 250 OA polysilicon film is formed.

Next, the thickness of the first interlayer insulating film is 500 to 1500.
A storage electrode 2 made of a polysilicon film having a thickness of 1,500 to 3,000 wafers is formed via the 5in2 film 6 of A.

Next, a thickness of 1500 to 3
A counter electrode 7 made of a polysilicon film of 1,000 yen is formed to constitute a capacitor.

Next, a second interlayer insulating film with a thickness of 500 mm is applied over the entire surface of the substrate.
~1000 SiO2 film 8 and thickness 500~100O
A SiN film 8N of A and a polycide film 3 (for forming bit line 3) having a thickness of 2000 to 3000 Å are formed in this order.

Next, a resist film 12 having a thickness of 1 to 2 .mu.m is formed as an etching mask for forming the bit line 3.

In FIG. 1(b), using the resist film 12 as a mask, the polycide film 3 and the SiN film 8N are removed by etching to form a bit line 3.

Etching of polycide and SiN uses a mixed gas of CF4 and 02 as the etching gas, and the etching gas is 0.
9 frequencies 13.56M in an atmosphere reduced to 3Torr
This is done by applying 300 W of power at Hz per substrate.

Next, a 5i02 film 9 is deposited on the entire surface of the substrate as a third interlayer insulating film.
．． BPSG (boron-doped phosphosilicate glass) 10 is deposited, and then these layers and the 5i02 film 8 outside the cell area are deposited.
and 5i (a contact hole 5 penetrating the L film 6 is formed to expose the word line l).

Etching of SiO□ uses CF4 as the etching gas.
This is carried out by applying a power of 800 W per substrate at a frequency of 13.56 MHz in an atmosphere with a reduced pressure of 1 to 2 Torr using a mixed gas of CHF3 and CHF3.

Next, cover the contact hole 5 with a thickness of 5,000 to 10 mm.
000 AI backing wiring 4 is formed.

FIG. 1(C) is a plan view corresponding to FIG. 1(b).

In the figure, word line 1 and bit line 3 are shown in a linear form for simplicity.

FIG. 2 is a sectional view illustrating a second embodiment of the present invention.

In the figure, l is a word line (gate), 2 is a storage electrode of a capacitor, and 3 is a hit line.

4 is a backing wiring, 5 is a contact hole between the backing wiring and a word line, 6, 8 to 1o are interlayer insulating films, which are SiO2 films, 7
is the counter electrode of the capacitor, 6N and 8N are interlayer insulating films, which are SiN films, and 101 is a semiconductor substrate, which is a silicon substrate.

102 is a field oxide film, and 03 is a gate oxide film.

In this example, a two-layer film consisting of an SiN film 8N and a SiO□ film 8 is used between the bit line 3 and the capacitor electrode 2).
Furthermore, there is also Si between the capacitor electrode 2 and the word line 1.
In this example, a two-layer film consisting of N film 6N and SiO□ film 6 is used.
The contact hole is shallower than the embodiment shown in FIG.

FIG. 3 is a sectional view illustrating a third embodiment of the present invention.

This example is a case of a shielded bit line, and the present invention can be applied to this case as well in the same way as the process shown in FIG.

In this figure, D is the dielectric film of the capacitor.

11 is an interlayer insulating film.

” In any of the embodiments described in 2, the symbols 6N, 8N
(2) SiN films were used, but what are the conditions required for these films?

(1) Etching is possible with a polycide or polysilicon etchant. (2) It has a sufficient etching selectivity with SiO□. Furthermore, if it is a film with a low dielectric constant and good insulating properties, an SiN film can be used. It is not limited to.

〔Effect of the invention〕

As explained above, according to the present invention, MOS DRA
In M, we were able to improve the step coverage of the word line backing wiring and improve the manufacturing yield and wiring reliability.

[Brief explanation of the drawing]

FIGS. 1(a) to (C) are a sectional view and a plan view illustrating one embodiment of the present invention. FIG. 2 is a sectional view illustrating a second embodiment of the present invention. FIG. 3 is a sectional view illustrating a third embodiment of the present invention. FIG. 4 is a sectional view illustrating a backing wiring using A1 alloy according to a conventional example. In fig. ■ is a word line (gate). 2 is the storage electrode of the capacitor. 3 is the bit line. 4 is the backing wiring. 5 is the contact hole for the backing wiring and word line. 6.8~IO is an interlayer insulating film and is a 5in2 film. 7 is the counter electrode of the capacitor. 6N and 8N are interlayer insulating films, which are SiN films.

Claims (1)

[Claims] 1) Field oxide film (102) in the isolation region on the semiconductor substrate (101), gate oxide film (103) in the element region
forming a word line (1) on the substrate, forming capacitors (2) and (7) through a first interlayer insulating film, and then forming a word line (1) on the substrate, forming capacitors (2) and (7) through a second interlayer insulating film; A step of forming a bit line (3), depositing a third interlayer insulating film on the entire surface of the substrate, forming a contact hole (5) penetrating the interlayer insulating film on the isolation region, and forming a word line (3). 1), and forming a backing wiring (4) on the substrate to cover the contact hole (5), and at least one of the first or second interlayer insulating film. A capacitor electrode (2
) or when patterning the bit line (3), self-aligning with the wiring pattern and etching off the upper layer film,
A method for manufacturing a semiconductor device, characterized in that etching is stopped at the lower layer film. 2) The method of manufacturing a semiconductor device according to claim 1, wherein the two-layer film includes a lower layer of a silicon dioxide film and an upper layer of a silicon nitride film.