KR20010003688A - method for fabricating high density memory device - Google Patents
method for fabricating high density memory device Download PDFInfo
- Publication number
- KR20010003688A KR20010003688A KR1019990024064A KR19990024064A KR20010003688A KR 20010003688 A KR20010003688 A KR 20010003688A KR 1019990024064 A KR1019990024064 A KR 1019990024064A KR 19990024064 A KR19990024064 A KR 19990024064A KR 20010003688 A KR20010003688 A KR 20010003688A
- Authority
- KR
- South Korea
- Prior art keywords
- silicon
- rich nitride
- nitride film
- oxide film
- metal
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 28
- 239000011229 interlayer Substances 0.000 claims abstract description 33
- 150000004767 nitrides Chemical class 0.000 claims abstract description 31
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 30
- 229910052751 metal Inorganic materials 0.000 claims abstract description 30
- 239000002184 metal Substances 0.000 claims abstract description 30
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 30
- 239000010703 silicon Substances 0.000 claims abstract description 30
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 12
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 12
- 239000010937 tungsten Substances 0.000 claims abstract description 12
- 230000004888 barrier function Effects 0.000 claims abstract description 8
- 238000005498 polishing Methods 0.000 claims description 14
- 238000005530 etching Methods 0.000 claims description 12
- 238000004519 manufacturing process Methods 0.000 claims description 11
- 239000002002 slurry Substances 0.000 claims description 9
- 239000004065 semiconductor Substances 0.000 claims description 6
- 125000006850 spacer group Chemical group 0.000 claims description 6
- 239000000126 substance Substances 0.000 claims description 6
- 239000010949 copper Substances 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- CETPSERCERDGAM-UHFFFAOYSA-N ceric oxide Chemical compound O=[Ce]=O CETPSERCERDGAM-UHFFFAOYSA-N 0.000 claims description 2
- 229910000422 cerium(IV) oxide Inorganic materials 0.000 claims description 2
- 239000010410 layer Substances 0.000 abstract description 22
- 239000000758 substrate Substances 0.000 abstract description 7
- 239000003990 capacitor Substances 0.000 abstract description 6
- 238000010438 heat treatment Methods 0.000 abstract description 4
- 230000003647 oxidation Effects 0.000 abstract description 3
- 238000007254 oxidation reaction Methods 0.000 abstract description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052760 oxygen Inorganic materials 0.000 abstract description 2
- 239000001301 oxygen Substances 0.000 abstract description 2
- 230000002093 peripheral effect Effects 0.000 abstract 1
- 230000015572 biosynthetic process Effects 0.000 description 5
- 239000000463 material Substances 0.000 description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 3
- -1 spacer nitride Chemical class 0.000 description 3
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 230000002542 deteriorative effect Effects 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 229910001930 tungsten oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
본 발명은 고집적 메모리소자 제조방법에 관한 것으로, 특히 메탈(metal) 비트라인을 갖는 1Gb(giga bit)급 이상의 DRAM과 같은 초고집적 메모리소자 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a highly integrated memory device, and more particularly, to a method for manufacturing an ultra-high density memory device, such as a DRAM of 1Gb (giga bit) or more having a metal bit line.
고집적화의 진전으로 3년에 메모리의 용량이 4배씩 증가되어 이미 1Gb(giga bit) DRAM의 개발이 이루어졌고 그 이상의 초고집적 DRAM에 대한 연구가 진행되고 있다. 이와 같이 DRAM의 집적도가 높아질수록 전기 신호를 읽고 기록하는 역할을 하는 셀의 면적은 1Gb의 경우 대략 0.08㎛2이다. 따라서, 이에 상응하는 비트라인의 요구선폭도 매우 감소하게 되었고, 그 결과 기존의 폴리실리콘 또는 단순한 실리사이드와 같은 비트라인 물질로는 1Gb급 이상의 DRAM에서 요구되는 미세선폭으로 낮은 저항값을 구현할 수 없게 되었다. 따라서, 비저항이 약 10μΩ/㎝인 텅스텐(W) 또는 구리(Cu) 등의 메탈로 비트라인을 형성하려는 연구가 꾸준히 진행되고 있다.With the progress of high integration, memory capacity has been increased by four times in three years, and 1Gb (giga bit) DRAM has already been developed. As the density of DRAM increases, the area of a cell that reads and writes an electrical signal is about 0.08 μm 2 for 1Gb. Therefore, the required line width of the corresponding bit line is also greatly reduced. As a result, the bit line material such as polysilicon or simple silicide cannot realize low resistance with the fine line width required in DRAMs of 1Gb or more. . Therefore, studies to form bit lines with metals such as tungsten (W) or copper (Cu) having a specific resistance of about 10 mu OMEGA / cm have been steadily being conducted.
그러나. 메탈 비트라인을 적용한 고집적 메모리소자 제조 공정시 웨이퍼 가장자리 지역에서 메탈 비트라인이 산화되면서 들뜨는 문제점이 발생되는 바, 도1에는 이러한 문제점이 도시되어 있다.But. In the manufacturing process of a highly integrated memory device using a metal bit line, a problem arises in that the metal bit line is oxidized in the wafer edge region, and this problem is illustrated in FIG. 1.
먼저, 도1의 구조가 생성되기 까지의 공정을 살펴보면, 실리콘기판(1) 상에 모스트랜지스터(도시되지 않음) 형성 등 소정공정을 완료하고, 제1층간산화막(2)을 형성한다. 이후 비트라인 콘택홀 형성후 또는 콘택 플러그 형성 후 Ti/TiN과 같은 베리어메탈(barrier metal)(3), 비트라인 물질로서의 텅스텐(4) 및 마스크층으로서의 질화막(5)을 적층하고 비트라인 마스크 및 식각 공정에 의해 적층된 층들을 패터닝한 다음, 상기 패턴의 측벽에 스페이서 질화막(6)을 형성한다. 이에 의해 비트라인 구조는 완성된다.First, referring to the process until the structure of FIG. 1 is produced, a predetermined process such as forming a MOS transistor (not shown) is completed on the silicon substrate 1, and the first interlayer oxide film 2 is formed. After the formation of the bit line contact hole or after the formation of the contact plug, a barrier metal 3 such as Ti / TiN, tungsten 4 as a bit line material and a nitride film 5 as a mask layer are laminated, and a bit line mask and After the layers stacked by the etching process are patterned, a spacer nitride layer 6 is formed on the sidewall of the pattern. This completes the bit line structure.
이어서, 제2층간산화막(7)을 증착하고 상기 제2층간산화막을 화학적기계적연마(CMP : chemical mechanical polishing)하게 되는데, 이때 웨이퍼 중심부에 비해 웨이퍼 가장자리에서의 제2층간산화막(7) 연마 속도가 빨라, 웨이퍼 가장자리에서는 마스크 질화막(5)이 드러나거나 그 상부로 얇게 제2층간산화막이 잔류하는 현상이 나타나며, 이에 의해 커패시터(8) 형성후 N2O 열처리시 텅스텐(4)이 산화되면서 비트라인이 들뜨는 결과를 가져온다.Subsequently, the second interlayer oxide film 7 is deposited and the second interlayer oxide film is chemical mechanical polishing (CMP), wherein the polishing rate of the second interlayer oxide film 7 at the edge of the wafer is higher than the center of the wafer. As a result, the mask nitride film 5 is exposed or a thin second interlayer oxide film remains on the wafer edge, whereby the tungsten 4 is oxidized during N 2 O heat treatment after the capacitor 8 is formed. This brings exciting results.
한편, 텅스텐 비트라인이 드러나는 문제를 해결하기 위해 도2에서와 같이 제2층간산화막(7) 연마후 추가로 절연막(9)을 1000Å 이상 증착하는 방법이 제시되어 있는데, 이때에는 캐패시터 형성 후, 금속배선 형성시 메탈 콘택의 깊이가 추가한 절연막(9) 두께만큼 증가하여, 콘택 식각시 실리콘기판(1)에 데미지를 주게 되며, 아울러, 콘택홀(10)의 어스펙트비(Aspect ratio)을 증가시켜 이 콘택홀에 배선용 메탈을 매립하기가 어려워진다. 즉, 메탈 층덮힘(step coverage)를 악화시켜 전기적 특성을 나쁘게 하는 역할을 한다. 미설명 도면부호 11은 캐패시터 상부의 제3층간산화막을 나타낸다.Meanwhile, in order to solve the problem in which the tungsten bit line is exposed, a method of depositing an insulating film 9 or more after 1000 Å after polishing the second interlayer oxide film 7 as shown in FIG. 2 is presented. The depth of the metal contact is increased by the thickness of the added insulating layer 9 when the wiring is formed, which causes damage to the silicon substrate 1 when the contact is etched, and also increases the aspect ratio of the contact hole 10. This makes it difficult to embed the wiring metal in the contact hole. That is, it plays a role of deteriorating the electrical properties by deteriorating the metal step coverage. Reference numeral 11 that is not described indicates a third interlayer oxide film on the capacitor.
또한, 도1 및 도2에서의 문제점을 해결하기 위해 도3에 같이, 스페이서 질화막(6) 형성후 그 결과물 전면에 텅스텐 산화방지용 질화막(12)을 약 500Å 이상 증착하고 제2층간산화막(7) 연마 공정을 진행하면 캐패시터 형성후 N2O 열처리시 텅스텐 비트라인이 들뜨는 것을 억제할 수 있으나, 전체적인 층간 절연 구조가 산화막/질화막/산화막의 다중 구조를 가짐으로써 금속배선 형성을 위한 콘택 식각시 다중 식각 처리를 진행해야만 하는 문제점이 있고 이후 세정 공정에서 산화막과 질화막(12)의 식각율 차이로 인해 콘택홀 내부로 질화막(12)이 돌출되는 현상(도면의 A 참조)이 발생하며, 이러한 콘택홀 프로파일(profile)로 인해 메탈(13) 증착시 질화막 돌출부 하단에서 보이드를 유발하는 문제점이 발생된다.In order to solve the problems in FIGS. 1 and 2, as shown in FIG. 3, after forming the spacer nitride film 6, a tungsten oxide nitride film 12 is deposited on the entire surface of the resultant by about 500 GPa or more and the second interlayer oxide film 7 is formed. When the polishing process is performed, the tungsten bit line may be prevented from rising during N 2 O heat treatment after the formation of the capacitor, but the overall interlayer insulating structure has multiple structures of oxide film, nitride film, and oxide film, so that multiple etching is performed during contact etching to form metal wiring. There is a problem that the process must proceed, and afterwards, a phenomenon in which the nitride film 12 protrudes into the contact hole due to the difference in the etch rate between the oxide film and the nitride film 12 (see A in the drawing) occurs. Due to the profile, a problem occurs that causes voids at the bottom of the nitride film protrusion when the metal 13 is deposited.
본 발명은 상술한 바와 같은 종래기술의 문제점을 해결하기 위하여 안출된 것으로서, 메탈 비트라인의 산화 및 들뜸 현상 방지, 후속 메탈 콘택 식각시의 기판 손상 방지, 콘택홀 프로파일 개선을 통한 메탈 층덮힘 개선 등을 위한 반도체메모리소자 제조방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the problems of the prior art as described above, to prevent the oxidation and lifting of the metal bit line, to prevent substrate damage during subsequent metal contact etching, to improve the metal layer covering through the improvement of the contact hole profile, etc. It is an object of the present invention to provide a method for manufacturing a semiconductor memory device.
도1, 도2 및 도3은 종래기술에 따른 텅스텐 비트라인 형성 공정시 나타나는 문제점을 나타낸 단면도,1, 2 and 3 are cross-sectional views showing problems in the tungsten bit line forming process according to the prior art;
도4a 및 도4b는 본 발명의 일실시예에 따른 메모리소자 제조방법.4A and 4B illustrate a method of manufacturing a memory device in accordance with an embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
401 : 실리콘기판 402 : 제1층간절연막401: silicon substrate 402: first interlayer insulating film
403 : 베리어메탈 404 : 텅스텐403: barrier metal 404: tungsten
405 : 마스크용 실리콘-리치 질화막 406 : 스페이서용 실리콘-리치 질화막405 silicon-rich nitride film for mask 406 silicon-rich nitride film for spacer
407 : 1차 제2층간산화막 408 : 2차 제2층간산화막407: primary second interlayer oxide film 408: secondary second interlayer oxide film
409 : 커패시터 410 : 제3층간산화막409: Capacitor 410: Third interlayer oxide film
상기 목적을 달성하기 위한 본 발명은, 메탈 비트라인을 갖는 반도체메모리소자 제조방법에 있어서, 소정공정이 완료된 구조물 상에 베리어메탈, 메탈, 및 제1 실리콘-리치 질화막을 적층하고 비트라인 마스크 및 식각 공정으로 패턴을 형성하는 제1단계; 상기 제1단계가 완료된 결과물의 전면에 제2 실리콘-리치 질화막을 증착하고 상기 제2 실리콘-리치 질화막을 전면 식각하여 상기 패턴의 측벽에 제2 실리콘-리치 질화막 스페이서를 형성하는 제2단계; 상기 제2단계가 완료된 결과물의 전면에 제1층간산화막을 형성하고 상기 제1 실리콘-리치 질화막의 표면이 드러나도록 상기 제1층간산화막을 화학적기계적연마하는 제3단계; 및 상기 제3단계가 완료된 결과물의 전면에 제2층간산화막을 형성하는 제4단계를 포함하여 이루어진다.In order to achieve the above object, the present invention provides a method of manufacturing a semiconductor memory device having a metal bit line, wherein a barrier metal, a metal, and a first silicon-rich nitride film are laminated on a structure on which a predetermined process is completed, and a bit line mask and an etching are performed. Forming a pattern by a process; Depositing a second silicon-rich nitride film on the entire surface of the resultant of which the first step is completed, and etching the second silicon-rich nitride film on the entire surface to form a second silicon-rich nitride film spacer on the sidewall of the pattern; A third step of forming a first interlayer oxide film on the entire surface of the resultant of the second step and chemically mechanically polishing the first interlayer oxide film so that the surface of the first silicon-rich nitride film is exposed; And a fourth step of forming a second interlayer oxide film on the entire surface of the resultant of the third step.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조하여 설명하기로 한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.
아래 실시예는 텅스텐을 비트라인 물질로 적용한 경우를 예로써 설명되었으나, 구리(Cu)를 비트라인으로 적용할 경우에도 본 실시예는 동일하게 적용될 수 있을 것이다.In the following embodiment, a case in which tungsten is applied as a bit line material has been described as an example, but in the case where copper (Cu) is used as a bit line, the present embodiment may be equally applied.
도4a 및 도4b에는 본 발명의 일실시예에 따른 메모리소자 제조 공정이 나타나 있다.4A and 4B illustrate a process of manufacturing a memory device according to an embodiment of the present invention.
도4a를 참조하면, 실리콘기판(401) 상에 모스트랜지스터(도시되지 않음) 형성 등 소정공정을 완료하고, 제1층간산화막(402)을 형성한다. 이후 비트라인 콘택홀 형성후 또는 콘택 플러그 형성 후 Ti/TiN과 같은 베리어메탈(403), 비트라인 물질로서의 텅스텐(404) 및 마스크층으로서의 실리콘-리치 질화막(Si-rich nitride)(405)을 적층하고 비트라인 마스크 및 식각 공정에 의해 적층된 층들을 패터닝한 다음, 그 패턴의 측벽에 스페이서로서 실리콘-리치 질화막(406)을 형성한다. 이에 의해 비트라인 구조는 완성된다.Referring to FIG. 4A, a predetermined process such as forming a MOS transistor (not shown) is completed on the silicon substrate 401, and a first interlayer oxide film 402 is formed. After the formation of the bit line contact hole or after the formation of the contact plug, a barrier metal 403 such as Ti / TiN, tungsten 404 as the bit line material and a silicon-rich nitride 405 as the mask layer are stacked. And layering the stacked layers by a bit line mask and an etching process, and then forming a silicon-rich nitride film 406 as a spacer on the sidewall of the pattern. This completes the bit line structure.
이어서, 1차 제2층간산화막(407)을 증착하고 상기 제2층간산화막을 화학적기계적연마(CMP : chemical mechanical polishing)하되, 상기 마스크용 실리콘-리치 질화막(405)의 표면이 노출될때까지 연마를 실시하여 평탄화한다. 실리콘-리치 질화막(405)은 일반 질화막(Si3N4) 보다 산화막 연마용 슬러리에서 연마속도가 느리기 때문에 실리콘-리치 질화막(405)은 연마정지층으로서 매우 유용한 작용을 하게 된다.Subsequently, a first second interlayer oxide layer 407 is deposited and the second interlayer oxide layer is chemical mechanical polishing (CMP), but polishing is performed until the surface of the mask silicon-rich nitride layer 405 is exposed. To planarize. Since the silicon-rich nitride film 405 has a slower polishing rate in the oxide polishing slurry than the general nitride film (Si 3 N 4 ), the silicon-rich nitride film 405 has a very useful function as a polishing stop layer.
이어서, 도4b에 도시된 바와같이, 상기 결과물 상에 2차 제2층간산화막(408)을 증착하면, 비트라인 상부의 제2층간산화막은 웨이퍼 중심부 및 가장자리에서 단차 없이 평탄화되면서, 층간산화막의 두께 증가라는 문제를 방지할 수 있다.Subsequently, as shown in FIG. 4B, when the secondary second interlayer oxide film 408 is deposited on the resultant, the second interlayer oxide film on the bit line is planarized without a step at the center and the edge of the bit line, and thus the thickness of the interlayer oxide film. The problem of increase can be prevented.
이어서, 통상의 방법으로 커패시터(409)를 형성하고 N2O 열처리를 실시하게되는데, 이때 웨이퍼 가장자리의 비트라인은 제2층간산화막(407)(408)이 두껍게 덮혀있으므로 산소(O2) 침투를 충분히 방지할 수 있다. 이어서, 결과물 상부에 제3층간산화막(410) 형성 및 금속배선 공정 등 후속 공정을 통상의 방법대로 실시한다.Subsequently, the capacitor 409 is formed by a conventional method and an N 2 O heat treatment is performed. At this time, the bit line at the edge of the wafer is thickly covered with the second interlayer oxide film 407 and 408 to prevent oxygen (O 2 ) penetration. It can prevent enough. Subsequently, subsequent steps such as forming the third interlayer oxide film 410 and the metallization process on the resultant are performed as usual.
상기한 바와 같은 본 발명에서, 베리어메탈(403)은 50∼800Å의 Ti/TiN층을 적용하고, 텅스텐(404)은 그 두께를 300∼1200Å으로 적용하고, 마스크용 실리콘-리치 질화막(405)은 그 두께를 700∼2000Å으로 적용하고, 스페이서용 실리콘-리치 질화막(406)은 100∼700Å 두께로 증착한 다음 전면 식각하여 형성하는 것이 바람직하다.In the present invention as described above, the barrier metal 403 applies a Ti / TiN layer of 50 to 800 GPa, the tungsten 404 applies a thickness of 300 to 1200 GPa, and the silicon-rich nitride film 405 for the mask. It is preferable that the thickness is applied to 700 to 2000 GPa, and the silicon-rich nitride film 406 for spacers is formed by depositing a thickness of 100 to 700 GPa and then etching the entire surface.
1차 제2층간산화막(407)은 BPSG, PSG, FSG, TEOS, HDPCVD(high density plasma CVD) 산화막, 비정질폴리(APL)산화막 등을 각기 4000∼10000Å 증착한 다음 화학적기계적연마를 실시하고, 2차 제2층간산화막(408)은 역시 BPSG, PSG, FSG, TEOS, HDPCVD 산화막, APL 산화막 등을 500∼4000Å의 두께로 적용하는 것이 바람직하다.The primary second interlayer oxide film 407 is a BPSG, PSG, FSG, TEOS, HDPCVD (high density plasma CVD) oxide film, amorphous poly (APL) oxide film, etc., respectively deposited 4000-10000Å, and then subjected to chemical mechanical polishing, 2 In the second interlayer oxide film 408, it is also preferable to apply a BPSG, PSG, FSG, TEOS, HDPCVD oxide film, APL oxide film or the like to a thickness of 500 to 4000 GPa.
실리콘-리치 질화막은 PECVD(plasma enhanced chemical vapor deposition) 또는 LPCVD(low pressure chemical vapor deposition) 방법으로 증착한다.The silicon-rich nitride film is deposited by plasma enhanced chemical vapor deposition (PECVD) or low pressure chemical vapor deposition (LPCVD).
아울러, 1차 제2층간산화막(407)의 화학적기계적연마는 세리아 계열의 슬러리를 사용하고, 이 슬러리의 산도를 5∼11 pH로 유지하며 슬러리내 함유된 연마제의 크기를 50∼1000nm로 유지하고, 슬러리 유량을 50∼400㎖/min으로 유지하는 것이 바람직하다.In addition, chemical mechanical polishing of the primary second interlayer oxide film 407 uses a ceria-based slurry, maintains the acidity of the slurry at a pH of 5 to 11, and maintains the size of the abrasive contained in the slurry at 50 to 1000 nm. It is preferable to maintain a slurry flow rate at 50-400 ml / min.
본 발명은 본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the present invention has been described in detail according to the preferred embodiments of the present invention, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
상술한 바와 같이 본 발명은 콘택 식각 및 메탈 증착 공정 등의 마진을 저하시키지 않는 상태에서 메탈 비트라인이 산화되는 문제를 해결할 수 있어, 메탈 비트라인을 적용하는 고집적 메모리소자 특성 향상을 가져오는 효과가 있다.As described above, the present invention can solve the problem that the metal bit line is oxidized without reducing the margin of the contact etching and metal deposition process, thereby improving the characteristics of the highly integrated memory device applying the metal bit line. have.
또한 웨이퍼 가장자리 부분에서의 메탈 비트라인 산화 및 들뜸 현상을 방지할 수 있어, 수율을 증대시키는 효과를 가져온다.In addition, the metal bit line oxidation and lifting phenomenon at the edge of the wafer can be prevented, resulting in an effect of increasing the yield.
Claims (6)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990024064A KR20010003688A (en) | 1999-06-24 | 1999-06-24 | method for fabricating high density memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990024064A KR20010003688A (en) | 1999-06-24 | 1999-06-24 | method for fabricating high density memory device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20010003688A true KR20010003688A (en) | 2001-01-15 |
Family
ID=19595074
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019990024064A KR20010003688A (en) | 1999-06-24 | 1999-06-24 | method for fabricating high density memory device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR20010003688A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101026002B1 (en) * | 2004-12-07 | 2011-03-30 | 매그나칩 반도체 유한회사 | Methods for forming pad of semiconductor devices |
| US11751381B2 (en) | 2021-03-05 | 2023-09-05 | SK Hynix Inc. | Semiconductor device and fabrication method of the same |
-
1999
- 1999-06-24 KR KR1019990024064A patent/KR20010003688A/en not_active Application Discontinuation
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101026002B1 (en) * | 2004-12-07 | 2011-03-30 | 매그나칩 반도체 유한회사 | Methods for forming pad of semiconductor devices |
| US11751381B2 (en) | 2021-03-05 | 2023-09-05 | SK Hynix Inc. | Semiconductor device and fabrication method of the same |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6528426B1 (en) | Integrated circuit interconnect and method | |
| KR100363710B1 (en) | Semiconductor device with self-aligned contact structure and method of manufacturing the same | |
| JP2005526378A (en) | Method for forming MIM capacitor | |
| KR20030005111A (en) | Semiconductor device and method of manufacturing the same | |
| KR100583286B1 (en) | Semiconductor device and fabricating method thereof | |
| US6680511B2 (en) | Integrated circuit devices providing improved short prevention | |
| KR100470292B1 (en) | Method of making a ferroelectric memory transistor | |
| KR20010082972A (en) | Wiring of Semiconductor Device and Method for Manufacturing Thereof | |
| US20020142582A1 (en) | Method for forming copper lines for semiconductor devices | |
| US7037821B2 (en) | Method for forming contact of semiconductor device | |
| US5714038A (en) | Method for forming contact hole of semiconductor device | |
| KR20030050951A (en) | Method for forming metal wiring of semiconductor device | |
| JPH10116904A (en) | Manufacture of semiconductor device | |
| KR20010003688A (en) | method for fabricating high density memory device | |
| KR100341573B1 (en) | Method for fabricating high density memory device | |
| KR100399909B1 (en) | Method of forming inter-metal dielectric in a semiconductor device | |
| KR20010003612A (en) | Method for fabricating high density memory device | |
| KR20020082667A (en) | Planarization method using Dummy pattern in semiconductor device | |
| KR100547244B1 (en) | Method for forming metal bit-line in memory device | |
| US7084057B2 (en) | Bit line contact structure and fabrication method thereof | |
| KR20040057485A (en) | Method for fabricating semiconductor device | |
| KR100390838B1 (en) | Method for forming landing plug contact in semiconductor device | |
| KR100492897B1 (en) | Method for fabricating polysilicon plug using polysilicon slurry | |
| KR100605231B1 (en) | Method of fabricating MIM capacitor | |
| KR20010005134A (en) | Method for fabricating memory device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WITN | Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid |