KR20030050951A - Method for forming metal wiring of semiconductor device - Google Patents
Method for forming metal wiring of semiconductor device Download PDFInfo
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- KR20030050951A KR20030050951A KR1020010081673A KR20010081673A KR20030050951A KR 20030050951 A KR20030050951 A KR 20030050951A KR 1020010081673 A KR1020010081673 A KR 1020010081673A KR 20010081673 A KR20010081673 A KR 20010081673A KR 20030050951 A KR20030050951 A KR 20030050951A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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Abstract
Description
본 발명은 반도체 소자의 금속배선 형성방법에 관한 것으로, 보다 상세하게는, 다마신(damascene) 공정에서 층간절연막 물질인 저유전율 절연막의 열화를 방지하기 위한 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wirings in a semiconductor device, and more particularly, to a method for preventing deterioration of a low dielectric insulating film, which is an interlayer insulating film material, in a damascene process.
반도체 소자의 고집적 및 고속화가 진행되면서, 4.0∼4.2 정도의 유전율을 갖는 SiO2막으로된 통상의 층간절연막은 소자의 구동 속도 향상을 방해하는 요인으로서 작용하게 된다. 즉, 반도체 소자의 고집적화는 필연적으로 셀 영역의 크기 감소를 수반하게 되는데, 셀 영역의 크기가 감소되면, 이웃하는 금속배선들간의 기생 캐패시턴스가 증가되어 RC 지연이 증가하게 되고, 이 결과, 소자의 구동 속도를 향상시키는데 한계를 갖게 된다.As the integration and speed of semiconductor devices progress, the conventional interlayer insulating film made of SiO2 film having a dielectric constant of about 4.0 to 4.2 acts as a factor that hinders the improvement of the driving speed of the device. That is, high integration of semiconductor devices inevitably entails a reduction in the size of the cell region. When the size of the cell region is reduced, parasitic capacitance between neighboring metal interconnections increases, resulting in an increase in the RC delay. There is a limit to improving the driving speed.
따라서, 고속 소자의 구현을 위해, 층간절연막 물질에 대한 연구, 즉, 저유전율의 절연막을 반도체 제조 공정에 적용하려는 연구가 활발하게 진행되고 있다.Therefore, in order to realize a high-speed device, research into interlayer insulating film materials, that is, research into applying an insulating film having a low dielectric constant to a semiconductor manufacturing process has been actively conducted.
한편, 주지된 바와 같이, 기존의 금속배선은 RIE(Reaction Ion Etching) 공정, 즉, 금속막 상에 마스크 패턴을 형성한 후, RIE 공정으로 상기 금속막을 직접 식각하는 방법으로 형성되어져 왔다. 그런데, 상기 RIE 공정을 이용한 방법은 금속배선의 임계 치수(critical dimension)가 감소되고 있는 추세에서, 그 전기적 특성의 확보가 어려운 문제점이 있는 바, 새로운 방식의 금속배선 공정이 필요하게 되었고, 이에, 다마신(Damascene) 공정이 제안되었다.On the other hand, as is well known, the existing metal wiring has been formed by a method of directly etching the metal film by a reaction ion etching (RIE) process, that is, after forming a mask pattern on the metal film, the RIE process. However, the method using the RIE process has a problem that it is difficult to secure the electrical characteristics in the trend that the critical dimension of the metal wiring is reduced, and thus a new method of metal wiring is needed. The damascene process has been proposed.
상기 다마신 공정은 금속배선이 형성된 영역을 미리 한정한 후, 금속막의 증착 및 CMP(Chemical Mechanical Polishing)를 수행하여 금속배선을 형성하는 기술이다.The damascene process is a technique of forming a metal interconnection by defining a region in which metal interconnection is formed in advance and then performing deposition of a metal film and chemical mechanical polishing (CMP).
이러한 다마신 공정은 RIE 공정에 의한 금속배선 형성방법 보다 상대적으로 우수한 전기적 특성을 얻을 수 있기 때문에 반도체 소자의 고집적화 추세에서 그이용이 확대되리라 예상된다. 특히, 금속배선의 재질이 기존의 알루미늄에서 텅스텐 또는 구리로 변경되는 추세에서, 기존의 식각 공정으로는 구리막의 식각 매우 어렵기 때문에 상기 다마신 공정의 적용은 필수가 될 것으로 예상된다.Since the damascene process can obtain relatively superior electrical characteristics than the metallization method by the RIE process, its use is expected to expand in the trend of high integration of semiconductor devices. In particular, in the trend that the material of the metal wiring is changed from conventional aluminum to tungsten or copper, it is expected that the application of the damascene process is required because the etching of the copper film is very difficult with the conventional etching process.
그런데, 다마신 공정을 이용하여 금속배선을 형성할 경우, 통상, 2회의 마스킹 및 식각을 통해 층간절연막에 비아홀 및 트렌치로 구성되는 다마신 패턴의 형성한 후, Ar과 같은 비활성 기체를 이용한 스퍼터링 방식의 식각을 행하여 노출된 하부 금속배선 표면의 금속산화막을 제거하고, 그런다음, 베리어막 및 배선용 금속막을 증착하는데, 이때, 층간절연막으로서 저유전 절연막이 적용되면, 상기 금속산화막의 제거를 위한 RF 식각 과정에서 측벽 방향으로 입사되는 비활성 가스에 의해 보잉(bowing)과 같은 측벽 프로파일(profile) 변경이 발생됨으로써, 층간절연막, 즉, 저유전 절연막의 열화가 초래된다.However, in the case of forming the metal wiring by using the damascene process, after forming a damascene pattern composed of via holes and trenches in the interlayer insulating layer through two masking and etching processes, a sputtering method using an inert gas such as Ar is used. Etching to remove the exposed metal oxide film on the lower metal wiring surface, and then depositing the barrier film and the metal film for wiring, if a low dielectric insulating film is applied as an interlayer insulating film, RF etching for removal of the metal oxide film In the process, the sidewall profile change such as bowing is generated by the inert gas incident in the sidewall direction, resulting in deterioration of the interlayer insulating film, that is, the low dielectric insulating film.
또한, 층간절연막으로서 저유전 절연막이 적용되면, 상기 다마신 패턴을 형성하는 과정에서 층간절연막 내에 수분이 함유될 수 있는데, 이러한 수분이 베리어막의 증착 과정에서 아웃개싱(outgassing)됨으로써, 금속막의 매립(gap-fill) 불량을 유발하게 된다.In addition, when a low dielectric insulating film is applied as the interlayer insulating film, water may be contained in the interlayer insulating film in the process of forming the damascene pattern, which is outgassed during the deposition of the barrier film, thereby filling the metal film ( gap-fill).
결국, 종래 기술에 따라 금속배선의 형성을 위해 다마신 공정을 이용하면서, 층간절연막의 재질로 저유전 절연막을 적용하게 되면, 상기 저유전 절연막의 열화가 야기되는 바, 소자의 제조수율 및 신뢰성 저하가 발생된다.As a result, when the low dielectric insulating film is applied as a material of the interlayer insulating film while using the damascene process for forming the metal wiring according to the prior art, deterioration of the low dielectric insulating film is caused. Is generated.
따라서, 본 발명은 상기와 같은 문제점을 해결하기 위해 안출된 것으로서,금속배선 공정에서 층간절연막 물질인 저유전 절연막의 열화를 방지할 수 있는 반도체 소자의 금속배선 형성방법을 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for forming a metal wiring of a semiconductor device capable of preventing deterioration of a low dielectric insulating film, which is an interlayer insulating film material, in the metal wiring process.
도 1a 내지 도 1d는 본 발명의 실시예에 따른 다마신 공정을 이용한 금속배선 형성방법을 설명하기 위한 블럭도.1A to 1D are block diagrams illustrating a method for forming metal wiring using a damascene process according to an embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
1 : 반도체 기판 2 : 하부 금속배선1 semiconductor substrate 2 lower metal wiring
3 : 제1층간절연막 4 : 제1식각정지막3: first interlayer insulating film 4: first etch stop film
5 : 제1절연막 6 : 제2식각정지막5: first insulating film 6: second etch stop film
7 : 제2절연막 8 : 하드마스크막7: second insulating film 8: hard mask film
9 : 비아홀 10 : 트렌치9: via hole 10: trench
11 : 캡핑층 12 : 베리어막11 capping layer 12 barrier film
20 : 상부 금속배선20: upper metal wiring
상기와 같은 목적을 달성하기 위한 본 발명의 금속배선 형성방법은, 하부 금속배선이 형성되고, 상기 하부 금속배선의 상면을 노출시키도록 제1층간절연막이 형성된 반도체 기판을 제공하는 단계; 상기 제1층간절연막과 하부 금속배선 상에 저유전 절연막으로 이루어진 제2층간절연막을 형성하는 단계; 상기 제2층간절연막을 식각하여 상기 하부 금속배선을 노출시키는 비아홀과 상부 금속배선 형성 영역을 한정하는 트렌치를 형성하는 단계; 상기 비아홀 및 트렌치의 측면과 노출된 하부 금속배선 및 제2층간절연막 상에 캡핑층을 증착하는 단계; 상기 캡핑층을 플라즈마 처리하는 단계; 상기 결과물에 대해 RF 식각을 수행하여 상기 제2층간절연막과 트렌치의 저면 및 하부 금속배선 상에 증착된 캡핑층을 제거하는 단계; 상기 비아홀 및 트렌치가 매립되도록 베리어막과 배선용 금속막을 차례로 증착하는 단계; 및 상기 제2층간절연막이 노출될 때까지 상기 배선용 금속막과 베리어막을 연마하는 단계를 포함한다.According to another aspect of the present invention, there is provided a method of forming a metal wiring, the method comprising: providing a semiconductor substrate on which a lower metal wiring is formed and a first interlayer insulating film is formed to expose an upper surface of the lower metal wiring; Forming a second interlayer insulating film made of a low dielectric insulating film on the first interlayer insulating film and the lower metal wiring; Etching the second interlayer insulating film to form a trench defining a via hole exposing the lower metal wiring and an upper metal wiring forming region; Depositing a capping layer on sidewalls of the via holes and trenches, the exposed lower metal interconnections, and a second interlayer dielectric layer; Plasma treating the capping layer; Performing RF etching on the resultant to remove the capping layer deposited on the bottom and lower metal interconnections of the second interlayer dielectric layer and the trench; Sequentially depositing a barrier film and a wiring metal film to fill the via hole and the trench; And polishing the wiring metal film and the barrier film until the second interlayer insulating film is exposed.
여기서, 상기 캡핑층은 PECVD 방식으로 증착되는 SiO2, SiN, SiON 및 SiC로 이루어지는 그룹으로부터 선택되는 어느 하나로 이루어지며, 50∼1,000Å의 두께로 증착된다. 또한, 상기 캡핑층에 대한 플라즈마 처리는 O2, N2O 및 CO2로 이루어지는 그룹으로부터 선택되는 어느 하나의 산소 원자를 함유한 가스를 사용하여 수행한다.Here, the capping layer is made of any one selected from the group consisting of SiO 2, SiN, SiON, and SiC deposited by PECVD, and is deposited to a thickness of 50 to 1,000 Å. Further, plasma treatment of the capping layer is performed using a gas containing any one oxygen atom selected from the group consisting of O 2, N 2 O and CO 2.
본 발명에 따르면, 다마신 패턴의 형성 후에 캡핑층의 형성 및 이에 대한 플라즈마 처리를 수행함으로써, 저유전 절연막에 함유된 수분의 아웃개싱에 의한 불량 및 다마신 패턴의 측벽 프로파일 변경에 의한 불량 발생을 방지할 수 있다.According to the present invention, the formation of the capping layer and the plasma treatment are performed after the formation of the damascene pattern, thereby preventing the occurrence of defects due to the outgassing of moisture contained in the low-k dielectric layer and change of the sidewall profile of the damascene pattern. You can prevent it.
(실시예)(Example)
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세하게 설명하도록 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2d는 본 발명의 실시예에 따른 저유전 절연막 및 다마신 공정을 이용한 금속배선 형성방법을 설명하기 위한 공정별 단면도이다.2A through 2D are cross-sectional views illustrating processes of forming metal wirings using a low dielectric insulating film and a damascene process according to an exemplary embodiment of the present invention.
도 2a를 참조하면, 공지의 반도체 제조 공정에 따라 구리 재질의 하부 금속배선(2)이 형성된 반도체 기판(1) 상에 저유전 절연막으로된 제1층간절연막(3)을 증착하고, 상기 하부 금속배선(2)이 노출되도록 그 표면을 평탄화시킨다.Referring to FIG. 2A, a first interlayer insulating film 3 made of a low dielectric insulating film 3 is deposited on a semiconductor substrate 1 on which a lower metal wiring 2 of copper is formed according to a known semiconductor manufacturing process. The surface is planarized so that the wiring 2 is exposed.
그런다음, 상기 하부금속배선(2)을 포함한 제1층간절연막(3) 상에 제2층간절연막으로서 제1식각정지막(4), 제1절연막(5), 제2식각정지막(6), 제2절연막(7) 및 하드마스크막(8)을 차례로 형성한 상태에서, 2회의 마스킹 및 식각 공정을 통해 상기 막들을 식각함으로써, 상기 하부 금속배선(2)을 노출시키는 콘택홀(9) 및 상부 금속배선 형성 영역을 한정하는 트렌치(10)를 형성한다.Then, the first etch stop film 4, the first insulating film 5, and the second etch stop film 6 as a second interlayer insulating film on the first interlayer insulating film 3 including the lower metal wiring 2. And a contact hole 9 exposing the lower metal wiring 2 by etching the layers through two masking and etching processes in a state in which the second insulating layer 7 and the hard mask layer 8 are sequentially formed. And a trench 10 defining an upper metal wiring formation region.
도 2b를 참조하면, 비아홀(9) 및 트렌치(10)의 측면과 노출된 하부 금속배선 부분 및 하드마스크막(8) 상에 PECVD 방식으로 SiO2, SiN, SiON 및 SiC 중의 어느 하나의 절연막을 50∼1,000Å의 두께로 증착하여 캡핑층(11)을 형성한다. 그런다음, 상기 결과물에 대해 상기 캡핑층(11)을 치밀화시킴과 동시에, 막 내에 질소성분을 함유하고 있을 경우, 막 표면에 존재하는 질소성분을 안정한 상태로 변화시키기 위해, O2, N2O 및 CO2와 같은 산소를 함유한 가스를 이용하여 플라즈마(plasma) 처리한다.Referring to FIG. 2B, an insulating film of any one of SiO 2, SiN, SiON, and SiC may be formed by PECVD on the side surfaces of the via holes 9 and the trenches 10, the exposed lower metallization portions, and the hard mask layer 8. The capping layer 11 is formed by depositing a thickness of ˜1,000 mm. Then, in order to densify the capping layer 11 with respect to the resultant, and in the case of containing a nitrogen component in the film, in order to change the nitrogen component present on the surface of the film to a stable state, O2, N2O and CO2 and Plasma treatment is performed using a gas containing the same oxygen.
도 1c를 참조하면, 상기 결과물에 대해 Ar 가스를 이용한 스퍼터링, 즉, RF 식각을 수행하여, 트렌치(10)의 저면에 형성된 캡핑층 부분과 비아홀(9)의 저면, 즉, 하부 금속배선(2) 상에 형성된 캡핑층 부분을 제거한다. 이 결과, 캡핑층(11)은 제1 및 제2절연막(5, 7)의 측벽에만 잔류된다.Referring to FIG. 1C, sputtering using Ar gas, that is, RF etching, is performed on the resultant, so that the capping layer formed on the bottom surface of the trench 10 and the bottom surface of the via hole 9, that is, the lower metal wiring 2. Remove the portion of the capping layer formed on the). As a result, the capping layer 11 remains only on the sidewalls of the first and second insulating films 5 and 7.
도 1d를 참조하면, 비아홀 및 트렌치의 표면과 하드마스크막(8) 상에 베리어막(12)을 증착하고, 상기 베리어막(12) 상에 상기 비아홀 및 트렌치가 완전 매립되도록 두껍게 배선용 금속막을 증착한다. 그런다음, 상기 하드마스크막(8)이 노출될 때까지 상기 배선용 금속막과 베리어막을 CMP하여, 하부 금속배선(2)과 콘택되는 상부 금속배선(20)을 형성한다.Referring to FIG. 1D, the barrier layer 12 is deposited on the surface of the via hole and the trench and the hard mask layer 8, and the wiring metal layer is thickly deposited on the barrier layer 12 so as to completely fill the via hole and the trench. do. Then, the wiring metal film and the barrier film are CMP until the hard mask film 8 is exposed to form the upper metal wiring 20 in contact with the lower metal wiring 2.
전술한 바와 같은 본 발명의 금속배선 형성방법에 따르면, 다마신 패턴의 형성후에 캡핑층의 형성과 상기 캡핑층의 치밀화를 위한 플라즈마 처리를 추가 수행함으로써, 첫째, 저유전 절연막, 즉, 제2층간절연막 내에 함유된 수분의 아웃개싱을 방지할 수 있으며, 이에 따라, 베리어막 및 배선용 금속막의 매립 불량을 방지할 수 있고, 둘째, 금속산화막의 제거를 위한 RF 식각시에 비아홀 및 트렌치의 프로파일 변경이 일어나는 것을 방지할 수 있으며, 이에 따라, 베리어막의 증착 불량이 유발되는 것을 방지할 수 있다.According to the metal wiring forming method of the present invention as described above, after the formation of the damascene pattern by further performing a plasma treatment for forming the capping layer and densification of the capping layer, firstly, a low dielectric insulating film, that is, between the second layer Outgassing of moisture contained in the insulating film can be prevented, and thus, a poor filling of the barrier film and the wiring metal film can be prevented. Second, the change of the profile of the via hole and the trench during the RF etching for removing the metal oxide film is prevented. It can be prevented from occurring, and accordingly, the deposition failure of the barrier film can be prevented from occurring.
결국, 본 발명에 따라 금속배선을 형성하게 되며, 층간절연막의 재질인 저유전 절연막의 열화를 방지할 수 있어서, 금속배선의 제조수율 및 신뢰성을 향상시킬 수 있다.As a result, according to the present invention, the metal wiring is formed, and the degradation of the low dielectric insulating film, which is a material of the interlayer insulating film, can be prevented, thereby improving the production yield and reliability of the metal wiring.
이상에서와 같이, 본 발명은 캡핑층의 형성 및 이에 대한 플라즈마 처리를 통해 저유전 절연막이 보호되도록 함으로써, 저유전 절연막에 함유된 수분의 아웃개싱을 방지할 수 있음은 물론 그 측면 프로파일의 변동을 방지할 수 있으며, 따라서, 금속배선 공정의 수율 및 그 신뢰성을 향상시킬 수 있고, 더나아가, 저유전 절연막의 적용을 통해 고속으로 동작하는 반도체 소자를 용이하게 제공할 수 있다.As described above, the present invention allows the low dielectric insulating film to be protected by forming the capping layer and plasma treatment, thereby preventing the outgassing of moisture contained in the low dielectric insulating film, and of course, fluctuations in the side profile thereof. Therefore, the yield and reliability of a metal wiring process can be improved, and furthermore, the semiconductor element which operates at high speed can be easily provided through application of a low dielectric insulating film.
기타, 본 발명은 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다.In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100724217B1 (en) * | 2005-12-28 | 2007-05-31 | 동부일렉트로닉스 주식회사 | Method for forming sin layer on a copper line process |
| KR100739255B1 (en) * | 2005-05-23 | 2007-07-12 | 주식회사 하이닉스반도체 | method of forming a metal line in semiconductor device |
| KR100924546B1 (en) * | 2007-07-27 | 2009-11-02 | 주식회사 하이닉스반도체 | Metal line of semiconductor device and method for manufacturing the same |
| KR101107746B1 (en) * | 2005-05-23 | 2012-01-20 | 주식회사 하이닉스반도체 | method of forming a metal line in semiconductor device |
| CN102412192A (en) * | 2011-05-23 | 2012-04-11 | 上海华力微电子有限公司 | Process method for metal interconnection sidewall mending |
| CN105470225A (en) * | 2015-12-09 | 2016-04-06 | 西安交通大学 | Method for manufacturing three-dimensional capacitively coupled interconnection structure based on through-silicon capacitor |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100258875B1 (en) * | 1998-01-15 | 2000-06-15 | 김영환 | Method of forming via for multilayer wiring |
| KR100568791B1 (en) * | 1999-06-23 | 2006-04-06 | 주식회사 하이닉스반도체 | Method of forming a via hole in a semiconductor device |
| KR100505451B1 (en) * | 2000-05-31 | 2005-08-04 | 주식회사 하이닉스반도체 | Method for forming metal wire of semiconductor device |
| US6232217B1 (en) * | 2000-06-05 | 2001-05-15 | Chartered Semiconductor Manufacturing Ltd. | Post treatment of via opening by N-containing plasma or H-containing plasma for elimination of fluorine species in the FSG near the surfaces of the via opening |
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| KR100739255B1 (en) * | 2005-05-23 | 2007-07-12 | 주식회사 하이닉스반도체 | method of forming a metal line in semiconductor device |
| KR101107746B1 (en) * | 2005-05-23 | 2012-01-20 | 주식회사 하이닉스반도체 | method of forming a metal line in semiconductor device |
| KR100724217B1 (en) * | 2005-12-28 | 2007-05-31 | 동부일렉트로닉스 주식회사 | Method for forming sin layer on a copper line process |
| KR100924546B1 (en) * | 2007-07-27 | 2009-11-02 | 주식회사 하이닉스반도체 | Metal line of semiconductor device and method for manufacturing the same |
| CN102412192A (en) * | 2011-05-23 | 2012-04-11 | 上海华力微电子有限公司 | Process method for metal interconnection sidewall mending |
| KR20220038540A (en) * | 2014-12-23 | 2022-03-28 | 인텔 코포레이션 | Via blocking layer |
| CN105990218A (en) * | 2015-01-30 | 2016-10-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN105470225A (en) * | 2015-12-09 | 2016-04-06 | 西安交通大学 | Method for manufacturing three-dimensional capacitively coupled interconnection structure based on through-silicon capacitor |
| CN105470225B (en) * | 2015-12-09 | 2018-04-17 | 西安交通大学 | Production method based on the three-dimensional capacitive coupling interconnection structure for wearing silicon capacitance |
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