CN105470225A - Method for manufacturing three-dimensional capacitively coupled interconnection structure based on through-silicon capacitor - Google Patents
Method for manufacturing three-dimensional capacitively coupled interconnection structure based on through-silicon capacitor Download PDFInfo
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Abstract
The invention discloses a method for manufacturing a three-dimensional capacitively coupled interconnection structure based on a through-silicon capacitor. The method comprises: forming two silicon substrates same in structure by machining, and bonding the back surface of one silicon substrate to the other silicon substrate in an alignment manner; forming the three-dimensional capacitively coupled interconnection structure based on the through-silicon capacitor; coaxially arranging copper columns at the upper part and the lower part of the interconnection structure; enabling the top of the copper column at the lower part to be in contact with a silicon dioxide insulation layer on the back surface of the silicon substrate at the upper part; and taking the copper column at the upper part and the copper column at the lower part as an upper electrode plate and a lower electrode plate of the capacitance respectively, taking an insulation layer between the copper column at the upper part and the copper column at the lower part as an inter-capacitance medium, and forming a through-silicon capacitor structure. Compared with a conventional TSV process, the method has the characteristics that the technological processes of making metal convex points on the front surface of a wafer, thinning the back surface to expose copper, performing insulation treatment, making micro-convex points and the like in a TSV structure making process are removed, the technological processes are remarkably reduced, the yield is increased, and required process devices are correspondingly reduced.
Description
Technical field
The invention belongs to microelectronics technology, particularly a kind of manufacture method of three-dimensional capacitive coupling interconnection structure.
Background technology
The at present conventional integrated interconnection structure of solid mainly contains to be worn silicon through hole (TSV:ThroughSiliconVia) and capacitive/inductive and to be coupled two classes.TSV comes from the United States Patent (USP) " Semiconductivewaferandmethodofmakingthesame " (3 of WILLIAMS-DARLING Ton holder gram (WilliamShockley) application in 1958 the earliest, 0044,909) employing " deeppits " structure proposed in realizes signal by front transmission rearwardly.TSV vertical interconnecting structure is with document " ThroughSiliconViaTechnology – ProcessesandReliabilityforWafer-Level3DSystemIntegration " (Ramm, and Wolf P., M.J2008 is published in ECTC58th) and " Through-SiliconVia (TSV) " (MakotoMotoyoshi2009 is published in ProceedingsoftheIEEE) in propose structure be main, this structure needs to make TSV vertical through hole at inside wafer, then barrier/seed layers making is carried out at through-hole side wall, and via metal, finally by thinning back side dew copper, insulating backside, stud bump making, the techniques such as lamination bonding realize the perpendicular interconnection of chip.But TSV structure complex manufacturing technology, device performance and yield can be caused to reduce, which limits the large-scale application (JinOuyang etc. of TSV structure at 3D-IC, Evaluationofusinginductive/capacitive-couplingverticalin terconnectsin3Dnetwork-on-chip, is published in ProceedingsoftheInternationalConferenceonComputer-AidedD esign in 2010).For addressing this problem, propose capacitive/inductive coupling vertical interconnecting structure, with document " 2.8Gb/sInductivelyCoupledInterconnectfor3-DICs ", (JianXu etc. are published in VLSICircuits in 2005 to this structure, 2005) and " 3Dcapacitiveinterconnectionswithmono-andbi-directionalca pabilities " (Fazzi, Alberto etc. are published in Solid-StateCircuitsConference in 2007, 2007) structure proposed in is main, this structure usually uses large-area top-level metallic as parallel capacitance plate or makes specific inductance coil, the perpendicular interconnection of chip is realized by inductance or capacitance coupling effect.This structure fabrication processes is simple, only can need be completed by traditional planar technique.But the three-dimensional integrated interconnection structure of capacitive coupling only can realize the aspectant perpendicular interconnection of layers of chips, the solid that cannot realize multilayer chiop is integrated, and the three-dimensional integrated interconnection structure of inductance coupling high, area occupied is excessive, the capacitive/inductive coupling vertical interconnecting structure area occupied of usual report is about hundreds of to tens thousand of square micron (JinOuyang etc., Evaluationofusinginductive/capacitive-couplingverticalin terconnectsin3Dnetwork-on-chip, within 2010, be published in ProceedingsoftheInternationalConferenceonComputer-AidedD esign).Even if increase other means such as custom-designed auxiliary circuit extra, capacitive/inductive coupling vertical interconnecting structure area occupied is still obviously greater than up-to-date TSV interconnection structure area.This just constrains the range of application of this structure, make capacitive/inductive be coupled vertical interconnecting structure substantially for three-dimensional coupling interconnection can only be realized at chip periphery (such as pad place), 3D-IC chip internal cannot be directly used in realize three-dimensional integrated interconnection as TSV structure.
Summary of the invention
The object of the present invention is to provide a kind of manufacture method of three-dimensional capacitive coupling interconnection structure based on wearing silicon electric capacity, the three-dimensional integrated rear performance of device and yield is caused to reduce to solve TSV vertical interconnecting structure complex manufacturing technology, and capacitive/inductive coupling vertical interconnecting structure cannot realize multilayer chiop lamination and realize three-dimensional coupling interconnection because area occupied can only be used for chip periphery (such as pad place) greatly substantially, cannot be directly used in the problem that 3D-IC chip internal realizes three-dimensional integrated interconnection as TSV structure.The invention provides a kind of manufacture method of wearing the three-dimensional capacitive coupling interconnection structure of silicon electric capacity (TSC:Through-siliconCapacitor) based on having merged vertical interconnecting structure and capacitive/inductive coupling vertical interconnecting structure advantage.This manufacture method can realize area occupied and be coupled vertical interconnecting structure (basically identical with TSV structure area occupied) much smaller than capacitive/inductive, and process complexity obviously reduces compared with TSV, three-dimensional integrated device performance and yield are affected to the making of the novel three-dimensional capacitive coupling interconnection structure significantly reduced.For the three-dimensional integrated Integrated Way providing a kind of new high area utilization, succinct, low cost, high yield of device three-dimensional.
To achieve these goals, the present invention adopts following technical scheme:
Based on the manufacture method of three-dimensional capacitive coupling interconnection structure of wearing silicon electric capacity, comprise the following steps:
(1) at surface of silicon growth layer of silicon dioxide mask layer;
(2) at earth silicon mask layer surface resist coating, exposure, development, exposes the window needing to etch top layer silicon;
(3) stop at window place etching silicon dioxide mask layer silicon substrate; The further etch silicon substrate at window place, forms through hole, then removes photomask surface glue;
(4) at substrate surface deposit layer of silicon dioxide insulating barrier, make through-hole side wall and bottom deposit layer of silicon dioxide insulating barrier, form through hole electric insulation layer;
(5) and then in silicon substrate front one deck barrier layer and one deck copper seed layer is grown successively;
(6) in the electro-coppering of silicon substrate front face surface, stop when copper all fills up through hole;
(7) carry out chemical machinery to mill copper, be milled to silicon dioxide insulating layer surface, front;
(8) at silicon substrate front face surface deposit layer of silicon dioxide insulating barrier, front insulation process is completed;
(9) interim bonding technology is adopted to be bonded on temporary carrier the substrate completing front insulation;
(10) carry out thinning from the back side to silicon substrate, until expose the bottom silicon dioxide silicon insulating barrier of through hole, complete a silicon substrate technique;
(11) the silicon substrate back side completing technique is aimed at the silicon substrate front of other a slice completing steps (1) ~ (10), and adopt SiO
2-SiO
2or SiO
2the two is bonded together by-Si bonding technology (TSV adopts copper-Xi eutectic bonding or copper-copper bonding usually);
(12) separate bonding and remove temporary carrier; Formed based on the three-dimensional capacitive coupling interconnection structure wearing silicon electric capacity.
Further, coaxially arrange based on the three-dimensional copper post of capacitive coupling interconnection structure middle and upper part and the copper post of bottom of wearing silicon electric capacity; The silicon dioxide insulating layer at the silicon substrate back side, contact top, copper column top of bottom; The copper post on top and the copper post of bottom are respectively as the upper bottom crown of electric capacity, and the insulating barrier between the copper post on top and the copper post of bottom, as medium between electric capacity, is formed and wears silicon capacitance structure.
Further, described silicon substrate is P type or N-type silicon.
Further, the step that through hole is cleaned also is comprised in step (3); Described in step (5), barrier layer is tantalum/tantalum nitride.
Further, the thickness of the earth silicon mask layer in silicon substrate front is 2 μm; The degree of depth of through hole is 30 μm, diameter 5 μm; The thickness of the silicon dioxide insulating layer of through-hole side wall and bottom deposit is 0.2 μm.
Based on the manufacture method of three-dimensional capacitive coupling interconnection structure of wearing silicon electric capacity, comprise the following steps:
(1) at SOI substrate front resist coating, exposure, development, exposes the window needing to etch top layer silicon;
(2) stop forming through hole to silicon dioxide oxygen buried layer in window place etching top layer silicon, then remove photomask surface glue;
(3) at substrate surface deposit layer of silicon dioxide insulating barrier, make through-hole side wall and bottom deposit layer of silicon dioxide insulating barrier, form through hole electric insulation layer; Then at growth barrier layer, SOI substrate front and one deck copper seed layer;
(4) in the electro-coppering of SOI substrate front face surface, treat that copper all fills up through hole and stops;
(5) carry out chemical machinery to mill copper in SOI substrate front, be milled to silicon dioxide insulating layer surface, front;
(6) at SOI substrate front face surface deposit layer of silicon dioxide insulating barrier, front insulation process is completed;
(7) interim bonding technology is adopted to be bonded on temporary carrier the SOI substrate completing front insulation;
(8) carry out thinning from the back side to SOI substrate, until expose the oxygen buried layer of SOI substrate;
(9) the SOI substrate back side completing technique is aimed at the SOI substrate front of other a slice completing steps (1) ~ (8), and adopt SiO
2-SiO
2or SiO
2the two is bonded together by-Si bonding technology (TSV adopts copper-Xi eutectic bonding or copper-copper bonding usually);
(10) separate bonding and remove temporary carrier; Obtain based on the three-dimensional capacitive coupling interconnection structure wearing silicon electric capacity.
Further, coaxially arrange based on the three-dimensional copper post of capacitive coupling interconnection structure middle and upper part and the copper post of bottom of wearing silicon electric capacity; The silicon dioxide oxygen buried layer at the copper pillar bump contact silicon substrate back side, top of the copper column top of bottom; The copper post on top and the copper post of bottom are respectively as the upper bottom crown of electric capacity, and the insulating barrier between the copper post on top and the copper post of bottom, as medium between electric capacity, is formed and wears silicon capacitance structure.
Further, the oxygen buried layer thickness of SOI substrate is
top layer silicon thickness
Further, described barrier layer is tantalum/tantalum nitride barrier layer.
Relative to prior art, the present invention has following beneficial effect:
The present invention propose based on the manufacture method of three-dimensional capacitive coupling interconnection structure of wearing silicon electric capacity (TSC) and the TSV process of routine and capacitive/inductive be coupled perpendicular interconnection manufacture craft compared with:
(1) produce based on the novel three-dimensional capacitive coupling interconnection structure wearing silicon electric capacity (TSC), the 1st layer crystal circle in copper metal column as parallel capacitance top crown, thin SiO
2layer is as medium between electric capacity, and the copper metal column in the 2nd layer crystal circle is as parallel capacitance bottom crown.When circuit carries out work, the 1st layer of circuit signal passes through capacitance coupling effect by the 1st layer of copper metal column layer, makes the 2nd layer of copper metal column layer induce corresponding signal, thus realizes the signal transmission between two-tier circuit.
(2) based on the process of three-dimensional capacitive coupling interconnection structure of wearing silicon electric capacity (TSC), significant improvement has been carried out to TSV technique, compared with the TSV technique of routine, present invention eliminates the technical processs such as wafer frontside metal salient point in TSV structure manufacturing process makes, thinning back side dew copper, insulation, micro convex point making, technical process obviously shortens, the corresponding minimizing of required process equipment.In three-dimensional integrated device, the impact of defective workmanship on device performance and yield significantly reduces simultaneously.
Accompanying drawing explanation
Fig. 1 (1)-Fig. 1 (17) is the existing TSV process method flow chart based on silicon substrate;
Fig. 2 is the manufacture method schematic flow sheet that the present invention is based on the three-dimensional capacitive coupling interconnection structure wearing silicon electric capacity (TSC);
Fig. 3 (1)-Fig. 3 (12) is the manufacture method schematic diagram that the present invention is based on the three-dimensional capacitive coupling interconnection structure wearing silicon electric capacity (TSC);
Wherein, 1-silicon substrate, 2-earth silicon mask layer, 3-photoresist, 4-tantalum nitride barrier layer and metal seed layer, 5-copper metal column, 6-temporary carrier, the silicon dioxide insulating layer of 7-back side deposit; Glue is filled under 8-.
Embodiment
Now in conjunction with the embodiments, the invention will be further described for accompanying drawing:
Embodiment 1:
A kind of manufacture method of three-dimensional capacitive coupling interconnection structure based on wearing silicon electric capacity of the present invention, the wafer substrate of employing is P-type silicon, and Si-Substrate Thickness is 675 μm, specifically comprises the following steps:
(1) at silicon substrate 1 superficial growth layer of silicon dioxide mask layer 2, mask layer thickness 2 μm;
(2) at the surperficial resist coating of earth silicon mask layer 2
exposure, development, exposes the window W1 needing to etch top layer silicon, and this window is circular, and diameter is 5 μm;
(3) stop at window W1 place etching silicon dioxide mask layer 2 to silicon substrate 1, etching depth is 2 μm; At the further etch silicon substrate 1 in window W1 place, stop when the degree of depth of etching is 30 μm forming through hole, then remove photomask surface glue 3, through hole is cleaned (deionized water+IPA+EKC);
(4) use PECVD (plasma enhanced chemical vapor deposition) method sinking to the bottom 1 surface deposition layer of silicon dioxide insulating barrier, make through-hole side wall and bottom deposit layer of silicon dioxide insulating barrier, form through hole electric insulation layer.
And then adopt the method for ion sputtering to grow tantalum/tantalum nitride barrier layer 4 and a layer thickness that a layer thickness is 0.8 μm (5)
copper seed layer;
(6) in the electro-coppering of silicon substrate 1 front face surface, stop when copper all fills up through hole;
(7) carry out chemical machinery to mill copper, be milled to the silicon dioxide insulating layer surface of step (4) institute deposit;
(8) at silicon substrate 1 front face surface deposit layer of silicon dioxide insulating barrier, front insulation process is completed;
(9) interim bonding technology is adopted to be bonded on temporary carrier 6 substrate 1 completing front insulation;
(10) carry out thinning from the back side to silicon substrate 1, until expose the bottom silicon dioxide silicon insulating barrier of through hole, complete a silicon substrate technique;
(11) silicon substrate 1 back side completing technique is aimed at silicon substrate 1 front of other a slice completing steps (1) ~ (10), and adopt SiO
2-SiO
2or SiO
2the two is bonded together by-Si bonding technology (TSV adopts copper-Xi eutectic bonding or copper-copper bonding usually);
(12) separate bonding and remove temporary carrier 6; Formed based on the three-dimensional capacitive coupling interconnection structure wearing silicon electric capacity.
Prepared by the inventive method based on the three-dimensional capacitive coupling interconnection structure wearing silicon electric capacity, the copper post on top and the copper post of bottom are coaxially arranged; The silicon dioxide insulating layer at the silicon substrate back side, contact top, copper column top of bottom; The copper post on top and the copper post of bottom are respectively as the upper bottom crown of electric capacity, and the insulating barrier between the copper post on top and the copper post of bottom, as medium between electric capacity, is formed and wears silicon capacitance structure; The signal of upper chip passes through capacitance coupling effect by the TSV metal column on top, makes the TSV metal column of bottom induce corresponding signal, realizes the signal transmission between upper and lower two chip blocks.
Embodiment 2:
A kind of manufacture method of three-dimensional capacitive coupling interconnection structure based on wearing silicon electric capacity of the present invention, adopts SOI wafer substrate to be P-type silicon, oxygen buried layer thickness
top layer silicon thickness
specifically comprise the following steps:
(1) at SOI substrate surface resist coating
exposure, development, exposes the window W1 needing to etch top layer silicon, and this window is circular, and diameter is 5 μm;
(2) stop forming through hole to silicon dioxide oxygen buried layer in window W1 place etching top layer silicon, etching depth is
then remove photomask surface glue, through hole is cleaned (deionized water+IPA+EKC); ;
(3) use PECVD (plasma enhanced chemical vapor deposition) method at substrate surface deposit a layer thickness 1 μm of silicon dioxide insulating layer, make the silicon dioxide insulating layer thickness of through-hole side wall and bottom deposit be 0.1 μm, form through hole electric insulation layer.And then adopt the method for ion sputtering to grow tantalum/tantalum nitride barrier layer and a layer thickness that a layer thickness is 0.05 μm
copper seed layer;
(4) in the electro-coppering of SOI substrate front face surface, stop when copper all fills up through hole;
(5) carry out chemical machinery to mill copper in SOI substrate front, be milled to silicon dioxide insulating layer surface, front;
(6) at SOI substrate front face surface deposit thick layer 0.2 μm of silicon dioxide insulating layer, front insulation process is completed;
(7) interim bonding technology is adopted to be bonded on temporary carrier the SOI substrate completing front insulation;
(8) carry out thinning from the back side to SOI substrate, until expose the oxygen buried layer of SOI substrate;
(9) the SOI substrate back side completing technique is aimed at the SOI substrate front of other a slice completing steps (1) ~ (8), and adopt SiO
2-SiO
2or SiO
2the two is bonded together by-Si bonding technology (TSV adopts copper-Xi eutectic bonding or copper-copper bonding usually);
(10) separate bonding and remove temporary carrier; Obtain based on the three-dimensional capacitive coupling interconnection structure wearing silicon electric capacity.
Claims (9)
1., based on the manufacture method of three-dimensional capacitive coupling interconnection structure of wearing silicon electric capacity, it is characterized in that, comprise the following steps:
(1) in silicon substrate (1) superficial growth layer of silicon dioxide mask layer (2);
(2) at earth silicon mask layer (2) surperficial resist coating (3), exposure, development, exposes the window (W1) needing to etch top layer silicon;
(3) stop to silicon substrate (1) at window (W1) place etching silicon dioxide mask layer (2); The further etch silicon substrate (1) at window (W1) place, forms through hole, then removes photomask surface glue (3);
(4) at silicon substrate (1) surface deposition layer of silicon dioxide insulating barrier, make through-hole side wall and bottom deposit layer of silicon dioxide insulating barrier, form through hole electric insulation layer;
(5) and then in silicon substrate (1) front one deck barrier layer (4) and one deck copper seed layer is grown successively;
(6) in silicon substrate (1) front face surface electro-coppering, stop when copper all fills up through hole;
(7) carry out chemical machinery to mill copper, be milled to the silicon dioxide insulating layer surface of step (4) institute deposit;
(8) at silicon substrate (1) front face surface deposit layer of silicon dioxide insulating barrier, front insulation process is completed;
(9) interim bonding technology is adopted to be bonded on temporary carrier (6) silicon substrate (1) completing front insulation;
(10) carry out thinning from the back side to silicon substrate (1), until expose the bottom silicon dioxide silicon insulating barrier of through hole, complete a silicon substrate technique;
(11) silicon substrate (1) back side completing technique is aimed at silicon substrate (1) front of other a slice completing steps (1) ~ (10), and adopt SiO
2-SiO
2or SiO
2the two is bonded together by-Si bonding technology;
(12) separate bonding and remove temporary carrier (6); Formed based on the three-dimensional capacitive coupling interconnection structure wearing silicon electric capacity.
2. the manufacture method of three-dimensional capacitive coupling interconnection structure based on wearing silicon electric capacity according to claim 1, is characterized in that, coaxially arrange based on the three-dimensional copper post of capacitive coupling interconnection structure middle and upper part and the copper post of bottom wearing silicon electric capacity; The silicon dioxide insulating layer at the silicon substrate back side, contact top, copper column top of bottom; The copper post on top and the copper post of bottom are respectively as the upper bottom crown of electric capacity, and the insulating barrier between the copper post on top and the copper post of bottom, as medium between electric capacity, is formed and wears silicon capacitance structure.
3. the manufacture method of three-dimensional capacitive coupling interconnection structure based on wearing silicon electric capacity according to claim 1, it is characterized in that, described silicon substrate is P type or N-type silicon.
4. the manufacture method of three-dimensional capacitive coupling interconnection structure based on wearing silicon electric capacity according to claim 1, it is characterized in that, step also comprises the step of cleaning through hole in (3); Described in step (5), barrier layer is tantalum/tantalum nitride.
5. the manufacture method of three-dimensional capacitive coupling interconnection structure based on wearing silicon electric capacity according to claim 1, it is characterized in that, the thickness of the earth silicon mask layer in silicon substrate front is 2 μm; The degree of depth of through hole is 30 μm, diameter 5 μm; The thickness of the silicon dioxide insulating layer of through-hole side wall and bottom deposit is 0.2 μm.
6., based on the manufacture method of three-dimensional capacitive coupling interconnection structure of wearing silicon electric capacity, it is characterized in that, comprise the following steps:
(1) at SOI substrate front resist coating, exposure, development, exposes the window (W1) needing to etch top layer silicon;
(2) stop forming through hole to silicon dioxide oxygen buried layer in window (W1) place etching top layer silicon, then remove photomask surface glue;
(3) sink to the bottom front deposit layer of silicon dioxide insulating barrier at SOI, make through-hole side wall and bottom deposit layer of silicon dioxide insulating barrier, form through hole electric insulation layer; Then at growth barrier layer, SOI substrate front and one deck copper seed layer;
(4) in the electro-coppering of SOI substrate front face surface, stop when copper all fills up through hole;
(5) carry out chemical machinery to mill copper in SOI substrate front, be milled to the silicon dioxide insulating layer surface of step (3) institute deposit;
(6) at SOI substrate front face surface deposit layer of silicon dioxide insulating barrier, front insulation process is completed;
(7) interim bonding technology is adopted to be bonded on temporary carrier the SOI substrate completing front insulation;
(8) carry out thinning from the back side to SOI substrate, until expose the oxygen buried layer of SOI substrate;
(9) the SOI substrate back side completing technique is aimed at the SOI substrate front of other a slice completing steps (1) ~ (8), and adopt SiO
2-SiO
2or SiO
2the two is bonded together by-Si bonding technology;
(10) separate bonding and remove temporary carrier; Obtain based on the three-dimensional capacitive coupling interconnection structure wearing silicon electric capacity.
7. the manufacture method of three-dimensional capacitive coupling interconnection structure based on wearing silicon electric capacity according to claim 6, is characterized in that, coaxially arrange based on the three-dimensional copper post of capacitive coupling interconnection structure middle and upper part and the copper post of bottom wearing silicon electric capacity; The silicon dioxide oxygen buried layer at the silicon substrate back side, contact top, copper column top of bottom; The copper post on top and the copper post of bottom are respectively as the upper bottom crown of electric capacity, and the insulating barrier between the copper post on top and the copper post of bottom, as medium between electric capacity, is formed and wears silicon capacitance structure.
8. the manufacture method of three-dimensional capacitive coupling interconnection structure based on wearing silicon electric capacity according to claim 6, it is characterized in that, the oxygen buried layer thickness of SOI substrate is
top layer silicon thickness
9. the manufacture method of three-dimensional capacitive coupling interconnection structure based on wearing silicon electric capacity according to claim 6, it is characterized in that, described barrier layer is tantalum/tantalum nitride barrier layer.
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